ia64/xen-unstable

view xen/arch/x86/hvm/vmx/vmx.c @ 11402:0da01d6f7017

[HVM][VMX] Report MCE/MCA features in CPUID.
Required for x86/64 Windows guest.
Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Aug 31 23:56:45 2006 +0100 (2006-08-31)
parents fab84f9c0ce6
children 37e5dfad8425
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <xen/hypercall.h>
29 #include <xen/perfc.h>
30 #include <asm/current.h>
31 #include <asm/io.h>
32 #include <asm/regs.h>
33 #include <asm/cpufeature.h>
34 #include <asm/processor.h>
35 #include <asm/types.h>
36 #include <asm/msr.h>
37 #include <asm/spinlock.h>
38 #include <asm/hvm/hvm.h>
39 #include <asm/hvm/support.h>
40 #include <asm/hvm/vmx/vmx.h>
41 #include <asm/hvm/vmx/vmcs.h>
42 #include <asm/hvm/vmx/cpu.h>
43 #include <asm/shadow.h>
44 #include <public/sched.h>
45 #include <public/hvm/ioreq.h>
46 #include <asm/hvm/vpic.h>
47 #include <asm/hvm/vlapic.h>
49 static DEFINE_PER_CPU(unsigned long, trace_values[5]);
50 #define TRACE_VMEXIT(index,value) this_cpu(trace_values)[index]=value
52 static void vmx_ctxt_switch_from(struct vcpu *v);
53 static void vmx_ctxt_switch_to(struct vcpu *v);
55 static int vmx_initialize_guest_resources(struct vcpu *v)
56 {
57 struct domain *d = v->domain;
58 struct vcpu *vc;
59 void *io_bitmap_a, *io_bitmap_b;
60 int rc;
62 v->arch.schedule_tail = arch_vmx_do_launch;
63 v->arch.ctxt_switch_from = vmx_ctxt_switch_from;
64 v->arch.ctxt_switch_to = vmx_ctxt_switch_to;
66 if ( v->vcpu_id != 0 )
67 return 1;
69 if ( !shadow_mode_external(d) )
70 {
71 DPRINTK("Can't init HVM for dom %u vcpu %u: "
72 "not in shadow external mode\n",
73 d->domain_id, v->vcpu_id);
74 domain_crash(d);
75 }
77 for_each_vcpu ( d, vc )
78 {
79 memset(&vc->arch.hvm_vmx, 0, sizeof(struct arch_vmx_struct));
81 if ( (rc = vmx_create_vmcs(vc)) != 0 )
82 {
83 DPRINTK("Failed to create VMCS for vcpu %d: err=%d.\n",
84 vc->vcpu_id, rc);
85 return 0;
86 }
88 spin_lock_init(&vc->arch.hvm_vmx.vmcs_lock);
90 if ( (io_bitmap_a = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
91 {
92 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
93 vc->vcpu_id);
94 return 0;
95 }
97 if ( (io_bitmap_b = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
98 {
99 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
100 vc->vcpu_id);
101 return 0;
102 }
104 memset(io_bitmap_a, 0xff, 0x1000);
105 memset(io_bitmap_b, 0xff, 0x1000);
107 /* don't bother debug port access */
108 clear_bit(PC_DEBUG_PORT, io_bitmap_a);
110 vc->arch.hvm_vmx.io_bitmap_a = io_bitmap_a;
111 vc->arch.hvm_vmx.io_bitmap_b = io_bitmap_b;
113 }
115 /*
116 * Required to do this once per domain XXX todo: add a seperate function
117 * to do these.
118 */
119 memset(&d->shared_info->evtchn_mask[0], 0xff,
120 sizeof(d->shared_info->evtchn_mask));
122 return 1;
123 }
125 static void vmx_relinquish_guest_resources(struct domain *d)
126 {
127 struct vcpu *v;
129 for_each_vcpu ( d, v )
130 {
131 vmx_destroy_vmcs(v);
132 if ( !test_bit(_VCPUF_initialised, &v->vcpu_flags) )
133 continue;
134 kill_timer(&v->arch.hvm_vcpu.hlt_timer);
135 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
136 {
137 kill_timer(&VLAPIC(v)->vlapic_timer);
138 unmap_domain_page_global(VLAPIC(v)->regs);
139 free_domheap_page(VLAPIC(v)->regs_page);
140 xfree(VLAPIC(v));
141 }
142 hvm_release_assist_channel(v);
143 }
145 kill_timer(&d->arch.hvm_domain.pl_time.periodic_tm.timer);
147 if ( d->arch.hvm_domain.shared_page_va )
148 unmap_domain_page_global(
149 (void *)d->arch.hvm_domain.shared_page_va);
151 if ( d->arch.hvm_domain.buffered_io_va )
152 unmap_domain_page_global((void *)d->arch.hvm_domain.buffered_io_va);
153 }
155 #ifdef __x86_64__
157 static DEFINE_PER_CPU(struct vmx_msr_state, percpu_msr);
159 static u32 msr_data_index[VMX_MSR_COUNT] =
160 {
161 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
162 MSR_SYSCALL_MASK, MSR_EFER,
163 };
165 static void vmx_save_segments(struct vcpu *v)
166 {
167 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
168 }
170 /*
171 * To avoid MSR save/restore at every VM exit/entry time, we restore
172 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
173 * are not modified once set for generic domains, we don't save them,
174 * but simply reset them to the values set at percpu_traps_init().
175 */
176 static void vmx_load_msrs(void)
177 {
178 struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
179 int i;
181 while ( host_state->flags )
182 {
183 i = find_first_set_bit(host_state->flags);
184 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
185 clear_bit(i, &host_state->flags);
186 }
187 }
189 static void vmx_save_init_msrs(void)
190 {
191 struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
192 int i;
194 for ( i = 0; i < VMX_MSR_COUNT; i++ )
195 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
196 }
198 #define CASE_READ_MSR(address) \
199 case MSR_ ## address: \
200 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
201 break
203 #define CASE_WRITE_MSR(address) \
204 case MSR_ ## address: \
205 { \
206 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
207 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
208 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
209 } \
210 wrmsrl(MSR_ ## address, msr_content); \
211 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
212 } \
213 break
215 #define IS_CANO_ADDRESS(add) 1
216 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
217 {
218 u64 msr_content = 0;
219 struct vcpu *v = current;
220 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
222 switch ( regs->ecx ) {
223 case MSR_EFER:
224 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content 0x%"PRIx64, msr_content);
225 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
227 /* the following code may be not needed */
228 if ( test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
229 msr_content |= EFER_LME;
230 else
231 msr_content &= ~EFER_LME;
233 if ( VMX_LONG_GUEST(v) )
234 msr_content |= EFER_LMA;
235 else
236 msr_content &= ~EFER_LMA;
237 break;
239 case MSR_FS_BASE:
240 if ( !(VMX_LONG_GUEST(v)) )
241 /* XXX should it be GP fault */
242 domain_crash_synchronous();
244 __vmread(GUEST_FS_BASE, &msr_content);
245 break;
247 case MSR_GS_BASE:
248 if ( !(VMX_LONG_GUEST(v)) )
249 domain_crash_synchronous();
251 __vmread(GUEST_GS_BASE, &msr_content);
252 break;
254 case MSR_SHADOW_GS_BASE:
255 msr_content = msr->shadow_gs;
256 break;
258 CASE_READ_MSR(STAR);
259 CASE_READ_MSR(LSTAR);
260 CASE_READ_MSR(CSTAR);
261 CASE_READ_MSR(SYSCALL_MASK);
263 default:
264 return 0;
265 }
267 HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
269 regs->eax = msr_content & 0xffffffff;
270 regs->edx = msr_content >> 32;
272 return 1;
273 }
275 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
276 {
277 u64 msr_content = regs->eax | ((u64)regs->edx << 32);
278 struct vcpu *v = current;
279 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
280 struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
282 HVM_DBG_LOG(DBG_LEVEL_1, "msr 0x%lx msr_content 0x%"PRIx64"\n",
283 (unsigned long)regs->ecx, msr_content);
285 switch ( regs->ecx ) {
286 case MSR_EFER:
287 /* offending reserved bit will cause #GP */
288 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
289 {
290 printk("trying to set reserved bit in EFER\n");
291 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
292 return 0;
293 }
295 /* LME: 0 -> 1 */
296 if ( msr_content & EFER_LME &&
297 !test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
298 {
299 if ( vmx_paging_enabled(v) ||
300 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
301 &v->arch.hvm_vmx.cpu_state) )
302 {
303 printk("trying to set LME bit when "
304 "in paging mode or PAE bit is not set\n");
305 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
306 return 0;
307 }
309 set_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state);
310 }
312 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
313 break;
315 case MSR_FS_BASE:
316 case MSR_GS_BASE:
317 if ( !(VMX_LONG_GUEST(v)) )
318 domain_crash_synchronous();
320 if ( !IS_CANO_ADDRESS(msr_content) )
321 {
322 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
323 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
324 return 0;
325 }
327 if ( regs->ecx == MSR_FS_BASE )
328 __vmwrite(GUEST_FS_BASE, msr_content);
329 else
330 __vmwrite(GUEST_GS_BASE, msr_content);
332 break;
334 case MSR_SHADOW_GS_BASE:
335 if ( !(VMX_LONG_GUEST(v)) )
336 domain_crash_synchronous();
338 v->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
339 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
340 break;
342 CASE_WRITE_MSR(STAR);
343 CASE_WRITE_MSR(LSTAR);
344 CASE_WRITE_MSR(CSTAR);
345 CASE_WRITE_MSR(SYSCALL_MASK);
347 default:
348 return 0;
349 }
351 return 1;
352 }
354 static void vmx_restore_msrs(struct vcpu *v)
355 {
356 int i = 0;
357 struct vmx_msr_state *guest_state;
358 struct vmx_msr_state *host_state;
359 unsigned long guest_flags ;
361 guest_state = &v->arch.hvm_vmx.msr_content;;
362 host_state = &this_cpu(percpu_msr);
364 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
365 guest_flags = guest_state->flags;
366 if (!guest_flags)
367 return;
369 while (guest_flags){
370 i = find_first_set_bit(guest_flags);
372 HVM_DBG_LOG(DBG_LEVEL_2,
373 "restore guest's index %d msr %lx with %lx\n",
374 i, (unsigned long)msr_data_index[i],
375 (unsigned long)guest_state->msr_items[i]);
376 set_bit(i, &host_state->flags);
377 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
378 clear_bit(i, &guest_flags);
379 }
380 }
382 #else /* __i386__ */
384 #define vmx_save_segments(v) ((void)0)
385 #define vmx_load_msrs() ((void)0)
386 #define vmx_restore_msrs(v) ((void)0)
387 #define vmx_save_init_msrs() ((void)0)
389 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
390 {
391 return 0;
392 }
394 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
395 {
396 return 0;
397 }
399 #endif /* __i386__ */
401 #define loaddebug(_v,_reg) \
402 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
403 #define savedebug(_v,_reg) \
404 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
406 static inline void vmx_save_dr(struct vcpu *v)
407 {
408 if ( v->arch.hvm_vcpu.flag_dr_dirty )
409 {
410 savedebug(&v->arch.guest_context, 0);
411 savedebug(&v->arch.guest_context, 1);
412 savedebug(&v->arch.guest_context, 2);
413 savedebug(&v->arch.guest_context, 3);
414 savedebug(&v->arch.guest_context, 6);
416 v->arch.hvm_vcpu.flag_dr_dirty = 0;
418 v->arch.hvm_vcpu.u.vmx.exec_control |= CPU_BASED_MOV_DR_EXITING;
419 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
420 v->arch.hvm_vcpu.u.vmx.exec_control);
421 }
422 }
424 static inline void __restore_debug_registers(struct vcpu *v)
425 {
426 loaddebug(&v->arch.guest_context, 0);
427 loaddebug(&v->arch.guest_context, 1);
428 loaddebug(&v->arch.guest_context, 2);
429 loaddebug(&v->arch.guest_context, 3);
430 /* No 4 and 5 */
431 loaddebug(&v->arch.guest_context, 6);
432 /* DR7 is loaded from the vmcs. */
433 }
435 /*
436 * DR7 is saved and restored on every vmexit. Other debug registers only
437 * need to be restored if their value is going to affect execution -- i.e.,
438 * if one of the breakpoints is enabled. So mask out all bits that don't
439 * enable some breakpoint functionality.
440 *
441 * This is in part necessary because bit 10 of DR7 is hardwired to 1, so a
442 * simple if( guest_dr7 ) will always return true. As long as we're masking,
443 * we might as well do it right.
444 */
445 #define DR7_ACTIVE_MASK 0xff
447 static inline void vmx_restore_dr(struct vcpu *v)
448 {
449 unsigned long guest_dr7;
451 __vmread(GUEST_DR7, &guest_dr7);
453 /* Assumes guest does not have DR access at time of context switch. */
454 if ( unlikely(guest_dr7 & DR7_ACTIVE_MASK) )
455 __restore_debug_registers(v);
456 }
458 static void vmx_freeze_time(struct vcpu *v)
459 {
460 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
462 if ( pt->enabled && pt->first_injected && !v->arch.hvm_vcpu.guest_time ) {
463 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
464 stop_timer(&(pt->timer));
465 }
466 }
468 static void vmx_ctxt_switch_from(struct vcpu *v)
469 {
470 vmx_freeze_time(v);
471 vmx_save_segments(v);
472 vmx_load_msrs();
473 vmx_save_dr(v);
474 }
476 static void vmx_ctxt_switch_to(struct vcpu *v)
477 {
478 vmx_restore_msrs(v);
479 vmx_restore_dr(v);
480 }
482 static void stop_vmx(void)
483 {
484 if (read_cr4() & X86_CR4_VMXE)
485 __vmxoff();
486 }
488 void vmx_migrate_timers(struct vcpu *v)
489 {
490 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
492 if ( pt->enabled ) {
493 migrate_timer(&pt->timer, v->processor);
494 migrate_timer(&v->arch.hvm_vcpu.hlt_timer, v->processor);
495 }
496 if ( hvm_apic_support(v->domain) && VLAPIC(v))
497 migrate_timer(&(VLAPIC(v)->vlapic_timer), v->processor);
498 }
500 static void vmx_store_cpu_guest_regs(
501 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
502 {
503 vmx_vmcs_enter(v);
505 if ( regs != NULL )
506 {
507 __vmread(GUEST_RFLAGS, &regs->eflags);
508 __vmread(GUEST_SS_SELECTOR, &regs->ss);
509 __vmread(GUEST_CS_SELECTOR, &regs->cs);
510 __vmread(GUEST_DS_SELECTOR, &regs->ds);
511 __vmread(GUEST_ES_SELECTOR, &regs->es);
512 __vmread(GUEST_GS_SELECTOR, &regs->gs);
513 __vmread(GUEST_FS_SELECTOR, &regs->fs);
514 __vmread(GUEST_RIP, &regs->eip);
515 __vmread(GUEST_RSP, &regs->esp);
516 }
518 if ( crs != NULL )
519 {
520 __vmread(CR0_READ_SHADOW, &crs[0]);
521 __vmread(GUEST_CR3, &crs[3]);
522 __vmread(CR4_READ_SHADOW, &crs[4]);
523 }
525 vmx_vmcs_exit(v);
526 }
528 /*
529 * The VMX spec (section 4.3.1.2, Checks on Guest Segment
530 * Registers) says that virtual-8086 mode guests' segment
531 * base-address fields in the VMCS must be equal to their
532 * corresponding segment selector field shifted right by
533 * four bits upon vmentry.
534 *
535 * This function (called only for VM86-mode guests) fixes
536 * the bases to be consistent with the selectors in regs
537 * if they're not already. Without this, we can fail the
538 * vmentry check mentioned above.
539 */
540 static void fixup_vm86_seg_bases(struct cpu_user_regs *regs)
541 {
542 int err = 0;
543 unsigned long base;
545 err |= __vmread(GUEST_ES_BASE, &base);
546 if (regs->es << 4 != base)
547 err |= __vmwrite(GUEST_ES_BASE, regs->es << 4);
548 err |= __vmread(GUEST_CS_BASE, &base);
549 if (regs->cs << 4 != base)
550 err |= __vmwrite(GUEST_CS_BASE, regs->cs << 4);
551 err |= __vmread(GUEST_SS_BASE, &base);
552 if (regs->ss << 4 != base)
553 err |= __vmwrite(GUEST_SS_BASE, regs->ss << 4);
554 err |= __vmread(GUEST_DS_BASE, &base);
555 if (regs->ds << 4 != base)
556 err |= __vmwrite(GUEST_DS_BASE, regs->ds << 4);
557 err |= __vmread(GUEST_FS_BASE, &base);
558 if (regs->fs << 4 != base)
559 err |= __vmwrite(GUEST_FS_BASE, regs->fs << 4);
560 err |= __vmread(GUEST_GS_BASE, &base);
561 if (regs->gs << 4 != base)
562 err |= __vmwrite(GUEST_GS_BASE, regs->gs << 4);
564 BUG_ON(err);
565 }
567 static void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
568 {
569 vmx_vmcs_enter(v);
571 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
572 __vmwrite(GUEST_DS_SELECTOR, regs->ds);
573 __vmwrite(GUEST_ES_SELECTOR, regs->es);
574 __vmwrite(GUEST_GS_SELECTOR, regs->gs);
575 __vmwrite(GUEST_FS_SELECTOR, regs->fs);
577 __vmwrite(GUEST_RSP, regs->esp);
579 __vmwrite(GUEST_RFLAGS, regs->eflags);
580 if (regs->eflags & EF_TF)
581 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
582 else
583 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
584 if (regs->eflags & EF_VM)
585 fixup_vm86_seg_bases(regs);
587 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
588 __vmwrite(GUEST_RIP, regs->eip);
590 vmx_vmcs_exit(v);
591 }
593 static int vmx_instruction_length(struct vcpu *v)
594 {
595 unsigned long inst_len;
597 if (__vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len))
598 return 0;
599 return inst_len;
600 }
602 static unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
603 {
604 switch ( num )
605 {
606 case 0:
607 return v->arch.hvm_vmx.cpu_cr0;
608 case 2:
609 return v->arch.hvm_vmx.cpu_cr2;
610 case 3:
611 return v->arch.hvm_vmx.cpu_cr3;
612 case 4:
613 return v->arch.hvm_vmx.cpu_shadow_cr4;
614 default:
615 BUG();
616 }
617 return 0; /* dummy */
618 }
622 /* Make sure that xen intercepts any FP accesses from current */
623 static void vmx_stts(struct vcpu *v)
624 {
625 unsigned long cr0;
627 /* VMX depends on operating on the current vcpu */
628 ASSERT(v == current);
630 /*
631 * If the guest does not have TS enabled then we must cause and handle an
632 * exception on first use of the FPU. If the guest *does* have TS enabled
633 * then this is not necessary: no FPU activity can occur until the guest
634 * clears CR0.TS, and we will initialise the FPU when that happens.
635 */
636 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
637 if ( !(cr0 & X86_CR0_TS) )
638 {
639 __vmread_vcpu(v, GUEST_CR0, &cr0);
640 __vmwrite(GUEST_CR0, cr0 | X86_CR0_TS);
641 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
642 }
643 }
646 static void vmx_set_tsc_offset(struct vcpu *v, u64 offset)
647 {
648 /* VMX depends on operating on the current vcpu */
649 ASSERT(v == current);
651 __vmwrite(TSC_OFFSET, offset);
652 #if defined (__i386__)
653 __vmwrite(TSC_OFFSET_HIGH, offset >> 32);
654 #endif
655 }
659 /* SMP VMX guest support */
660 static void vmx_init_ap_context(struct vcpu_guest_context *ctxt,
661 int vcpuid, int trampoline_vector)
662 {
663 int i;
665 memset(ctxt, 0, sizeof(*ctxt));
667 /*
668 * Initial register values:
669 */
670 ctxt->user_regs.eip = VMXASSIST_BASE;
671 ctxt->user_regs.edx = vcpuid;
672 ctxt->user_regs.ebx = trampoline_vector;
674 ctxt->flags = VGCF_HVM_GUEST;
676 /* Virtual IDT is empty at start-of-day. */
677 for ( i = 0; i < 256; i++ )
678 {
679 ctxt->trap_ctxt[i].vector = i;
680 ctxt->trap_ctxt[i].cs = FLAT_KERNEL_CS;
681 }
683 /* No callback handlers. */
684 #if defined(__i386__)
685 ctxt->event_callback_cs = FLAT_KERNEL_CS;
686 ctxt->failsafe_callback_cs = FLAT_KERNEL_CS;
687 #endif
688 }
690 void do_nmi(struct cpu_user_regs *);
692 static int check_vmx_controls(u32 ctrls, u32 msr)
693 {
694 u32 vmx_msr_low, vmx_msr_high;
696 rdmsr(msr, vmx_msr_low, vmx_msr_high);
697 if ( (ctrls < vmx_msr_low) || (ctrls > vmx_msr_high) )
698 {
699 printk("Insufficient VMX capability 0x%x, "
700 "msr=0x%x,low=0x%8x,high=0x%x\n",
701 ctrls, msr, vmx_msr_low, vmx_msr_high);
702 return 0;
703 }
704 return 1;
705 }
707 static void vmx_init_hypercall_page(struct domain *d, void *hypercall_page)
708 {
709 char *p;
710 int i;
712 memset(hypercall_page, 0, PAGE_SIZE);
714 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
715 {
716 p = (char *)(hypercall_page + (i * 32));
717 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
718 *(u32 *)(p + 1) = i;
719 *(u8 *)(p + 5) = 0x0f; /* vmcall */
720 *(u8 *)(p + 6) = 0x01;
721 *(u8 *)(p + 7) = 0xc1;
722 *(u8 *)(p + 8) = 0xc3; /* ret */
723 }
725 /* Don't support HYPERVISOR_iret at the moment */
726 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
727 }
729 /* Setup HVM interfaces */
730 static void vmx_setup_hvm_funcs(void)
731 {
732 if ( hvm_enabled )
733 return;
735 hvm_funcs.disable = stop_vmx;
737 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
738 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
740 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
741 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
743 hvm_funcs.realmode = vmx_realmode;
744 hvm_funcs.paging_enabled = vmx_paging_enabled;
745 hvm_funcs.long_mode_enabled = vmx_long_mode_enabled;
746 hvm_funcs.guest_x86_mode = vmx_guest_x86_mode;
747 hvm_funcs.instruction_length = vmx_instruction_length;
748 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
750 hvm_funcs.update_host_cr3 = vmx_update_host_cr3;
752 hvm_funcs.stts = vmx_stts;
753 hvm_funcs.set_tsc_offset = vmx_set_tsc_offset;
755 hvm_funcs.init_ap_context = vmx_init_ap_context;
757 hvm_funcs.init_hypercall_page = vmx_init_hypercall_page;
758 }
760 int start_vmx(void)
761 {
762 u32 eax, edx;
763 struct vmcs_struct *vmcs;
765 /*
766 * Xen does not fill x86_capability words except 0.
767 */
768 boot_cpu_data.x86_capability[4] = cpuid_ecx(1);
770 if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
771 return 0;
773 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
775 if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
776 {
777 if ( (eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0 )
778 {
779 printk("VMX disabled by Feature Control MSR.\n");
780 return 0;
781 }
782 }
783 else
784 {
785 wrmsr(IA32_FEATURE_CONTROL_MSR,
786 IA32_FEATURE_CONTROL_MSR_LOCK |
787 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
788 }
790 if ( !check_vmx_controls(MONITOR_PIN_BASED_EXEC_CONTROLS,
791 MSR_IA32_VMX_PINBASED_CTLS_MSR) )
792 return 0;
793 if ( !check_vmx_controls(MONITOR_CPU_BASED_EXEC_CONTROLS,
794 MSR_IA32_VMX_PROCBASED_CTLS_MSR) )
795 return 0;
796 if ( !check_vmx_controls(MONITOR_VM_EXIT_CONTROLS,
797 MSR_IA32_VMX_EXIT_CTLS_MSR) )
798 return 0;
799 if ( !check_vmx_controls(MONITOR_VM_ENTRY_CONTROLS,
800 MSR_IA32_VMX_ENTRY_CTLS_MSR) )
801 return 0;
803 set_in_cr4(X86_CR4_VMXE);
805 vmx_init_vmcs_config();
807 if(!smp_processor_id())
808 setup_vmcs_dump();
810 if ( (vmcs = vmx_alloc_host_vmcs()) == NULL )
811 {
812 printk("Failed to allocate host VMCS\n");
813 return 0;
814 }
816 if ( __vmxon(virt_to_maddr(vmcs)) )
817 {
818 printk("VMXON failed\n");
819 vmx_free_host_vmcs(vmcs);
820 return 0;
821 }
823 printk("VMXON is done\n");
825 vmx_save_init_msrs();
827 vmx_setup_hvm_funcs();
829 hvm_enabled = 1;
831 return 1;
832 }
834 /*
835 * Not all cases receive valid value in the VM-exit instruction length field.
836 */
837 #define __get_instruction_length(len) \
838 __vmread(VM_EXIT_INSTRUCTION_LEN, &(len)); \
839 if ((len) < 1 || (len) > 15) \
840 __hvm_bug(&regs);
842 static void inline __update_guest_eip(unsigned long inst_len)
843 {
844 unsigned long current_eip;
846 __vmread(GUEST_RIP, &current_eip);
847 __vmwrite(GUEST_RIP, current_eip + inst_len);
848 __vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
849 }
851 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
852 {
853 int result;
855 #if 0 /* keep for debugging */
856 {
857 unsigned long eip, cs;
859 __vmread(GUEST_CS_BASE, &cs);
860 __vmread(GUEST_RIP, &eip);
861 HVM_DBG_LOG(DBG_LEVEL_VMMU,
862 "vmx_do_page_fault = 0x%lx, cs_base=%lx, "
863 "eip = %lx, error_code = %lx\n",
864 va, cs, eip, (unsigned long)regs->error_code);
865 }
866 #endif
868 result = shadow_fault(va, regs);
870 TRACE_VMEXIT (2,result);
871 #if 0
872 if ( !result )
873 {
874 __vmread(GUEST_RIP, &eip);
875 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
876 }
877 #endif
879 return result;
880 }
882 static void vmx_do_no_device_fault(void)
883 {
884 unsigned long cr0;
885 struct vcpu *v = current;
887 setup_fpu(current);
888 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
890 /* Disable TS in guest CR0 unless the guest wants the exception too. */
891 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
892 if ( !(cr0 & X86_CR0_TS) )
893 {
894 __vmread_vcpu(v, GUEST_CR0, &cr0);
895 cr0 &= ~X86_CR0_TS;
896 __vmwrite(GUEST_CR0, cr0);
897 }
898 }
900 #define bitmaskof(idx) (1U << ((idx)&31))
901 static void vmx_vmexit_do_cpuid(struct cpu_user_regs *regs)
902 {
903 unsigned int input = (unsigned int)regs->eax;
904 unsigned int count = (unsigned int)regs->ecx;
905 unsigned int eax, ebx, ecx, edx;
906 unsigned long eip;
907 struct vcpu *v = current;
909 __vmread(GUEST_RIP, &eip);
911 HVM_DBG_LOG(DBG_LEVEL_3, "(eax) 0x%08lx, (ebx) 0x%08lx, "
912 "(ecx) 0x%08lx, (edx) 0x%08lx, (esi) 0x%08lx, (edi) 0x%08lx",
913 (unsigned long)regs->eax, (unsigned long)regs->ebx,
914 (unsigned long)regs->ecx, (unsigned long)regs->edx,
915 (unsigned long)regs->esi, (unsigned long)regs->edi);
917 if ( input == CPUID_LEAF_0x4 )
918 {
919 cpuid_count(input, count, &eax, &ebx, &ecx, &edx);
920 eax &= NUM_CORES_RESET_MASK;
921 }
922 else if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
923 {
924 cpuid(input, &eax, &ebx, &ecx, &edx);
926 if ( input == CPUID_LEAF_0x1 )
927 {
928 /* mask off reserved bits */
929 ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
931 if ( !hvm_apic_support(v->domain) ||
932 !vlapic_global_enabled((VLAPIC(v))) )
933 {
934 /* Since the apic is disabled, avoid any
935 confusion about SMP cpus being available */
937 clear_bit(X86_FEATURE_APIC, &edx);
938 }
940 #if CONFIG_PAGING_LEVELS >= 3
941 if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
942 #endif
943 clear_bit(X86_FEATURE_PAE, &edx);
944 clear_bit(X86_FEATURE_PSE36, &edx);
946 ebx &= NUM_THREADS_RESET_MASK;
948 /* Unsupportable for virtualised CPUs. */
949 ecx &= ~(bitmaskof(X86_FEATURE_VMXE) |
950 bitmaskof(X86_FEATURE_EST) |
951 bitmaskof(X86_FEATURE_TM2) |
952 bitmaskof(X86_FEATURE_CID) |
953 bitmaskof(X86_FEATURE_MWAIT) );
955 edx &= ~( bitmaskof(X86_FEATURE_HT) |
956 bitmaskof(X86_FEATURE_ACPI) |
957 bitmaskof(X86_FEATURE_ACC) );
958 }
959 else if ( ( input == CPUID_LEAF_0x6 )
960 || ( input == CPUID_LEAF_0x9 )
961 || ( input == CPUID_LEAF_0xA ))
962 {
963 eax = ebx = ecx = edx = 0x0;
964 }
965 #ifdef __i386__
966 else if ( input == CPUID_LEAF_0x80000001 )
967 {
968 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
970 clear_bit(X86_FEATURE_LM & 31, &edx);
971 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
972 }
973 #endif
974 }
976 regs->eax = (unsigned long) eax;
977 regs->ebx = (unsigned long) ebx;
978 regs->ecx = (unsigned long) ecx;
979 regs->edx = (unsigned long) edx;
981 HVM_DBG_LOG(DBG_LEVEL_3, "eip@%lx, input: 0x%lx, "
982 "output: eax = 0x%08lx, ebx = 0x%08lx, "
983 "ecx = 0x%08lx, edx = 0x%08lx",
984 (unsigned long)eip, (unsigned long)input,
985 (unsigned long)eax, (unsigned long)ebx,
986 (unsigned long)ecx, (unsigned long)edx);
987 }
989 #define CASE_GET_REG_P(REG, reg) \
990 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
992 #ifdef __i386__
993 #define CASE_EXTEND_GET_REG_P
994 #else
995 #define CASE_EXTEND_GET_REG_P \
996 CASE_GET_REG_P(R8, r8); \
997 CASE_GET_REG_P(R9, r9); \
998 CASE_GET_REG_P(R10, r10); \
999 CASE_GET_REG_P(R11, r11); \
1000 CASE_GET_REG_P(R12, r12); \
1001 CASE_GET_REG_P(R13, r13); \
1002 CASE_GET_REG_P(R14, r14); \
1003 CASE_GET_REG_P(R15, r15)
1004 #endif
1006 static void vmx_dr_access(unsigned long exit_qualification,
1007 struct cpu_user_regs *regs)
1009 struct vcpu *v = current;
1011 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1013 /* We could probably be smarter about this */
1014 __restore_debug_registers(v);
1016 /* Allow guest direct access to DR registers */
1017 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_MOV_DR_EXITING;
1018 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
1019 v->arch.hvm_vcpu.u.vmx.exec_control);
1022 /*
1023 * Invalidate the TLB for va. Invalidate the shadow page corresponding
1024 * the address va.
1025 */
1026 static void vmx_vmexit_do_invlpg(unsigned long va)
1028 unsigned long eip;
1029 struct vcpu *v = current;
1031 __vmread(GUEST_RIP, &eip);
1033 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
1034 eip, va);
1036 /*
1037 * We do the safest things first, then try to update the shadow
1038 * copying from guest
1039 */
1040 shadow_invlpg(v, va);
1044 static int check_for_null_selector(unsigned long eip)
1046 unsigned char inst[MAX_INST_LEN];
1047 unsigned long sel;
1048 int i, inst_len;
1049 int inst_copy_from_guest(unsigned char *, unsigned long, int);
1051 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1052 memset(inst, 0, MAX_INST_LEN);
1053 if (inst_copy_from_guest(inst, eip, inst_len) != inst_len) {
1054 printf("check_for_null_selector: get guest instruction failed\n");
1055 domain_crash_synchronous();
1058 for (i = 0; i < inst_len; i++) {
1059 switch (inst[i]) {
1060 case 0xf3: /* REPZ */
1061 case 0xf2: /* REPNZ */
1062 case 0xf0: /* LOCK */
1063 case 0x66: /* data32 */
1064 case 0x67: /* addr32 */
1065 continue;
1066 case 0x2e: /* CS */
1067 __vmread(GUEST_CS_SELECTOR, &sel);
1068 break;
1069 case 0x36: /* SS */
1070 __vmread(GUEST_SS_SELECTOR, &sel);
1071 break;
1072 case 0x26: /* ES */
1073 __vmread(GUEST_ES_SELECTOR, &sel);
1074 break;
1075 case 0x64: /* FS */
1076 __vmread(GUEST_FS_SELECTOR, &sel);
1077 break;
1078 case 0x65: /* GS */
1079 __vmread(GUEST_GS_SELECTOR, &sel);
1080 break;
1081 case 0x3e: /* DS */
1082 /* FALLTHROUGH */
1083 default:
1084 /* DS is the default */
1085 __vmread(GUEST_DS_SELECTOR, &sel);
1087 return sel == 0 ? 1 : 0;
1090 return 0;
1093 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
1094 unsigned long count, int size, long value,
1095 int dir, int pvalid);
1097 static void vmx_io_instruction(unsigned long exit_qualification,
1098 unsigned long inst_len)
1100 struct cpu_user_regs *regs;
1101 struct hvm_io_op *pio_opp;
1102 unsigned long eip, cs, eflags;
1103 unsigned long port, size, dir;
1104 int vm86;
1106 pio_opp = &current->arch.hvm_vcpu.io_op;
1107 pio_opp->instr = INSTR_PIO;
1108 pio_opp->flags = 0;
1110 regs = &pio_opp->io_context;
1112 /* Copy current guest state into io instruction state structure. */
1113 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1114 hvm_store_cpu_guest_regs(current, regs, NULL);
1116 eip = regs->eip;
1117 cs = regs->cs;
1118 eflags = regs->eflags;
1120 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
1122 HVM_DBG_LOG(DBG_LEVEL_IO,
1123 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
1124 "exit_qualification = %lx",
1125 vm86, cs, eip, exit_qualification);
1127 if (test_bit(6, &exit_qualification))
1128 port = (exit_qualification >> 16) & 0xFFFF;
1129 else
1130 port = regs->edx & 0xffff;
1131 TRACE_VMEXIT(1, port);
1132 size = (exit_qualification & 7) + 1;
1133 dir = test_bit(3, &exit_qualification); /* direction */
1135 if (test_bit(4, &exit_qualification)) { /* string instruction */
1136 unsigned long addr, count = 1;
1137 int sign = regs->eflags & EF_DF ? -1 : 1;
1139 __vmread(GUEST_LINEAR_ADDRESS, &addr);
1141 /*
1142 * In protected mode, guest linear address is invalid if the
1143 * selector is null.
1144 */
1145 if (!vm86 && check_for_null_selector(eip))
1146 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
1148 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
1149 pio_opp->flags |= REPZ;
1150 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
1153 /*
1154 * Handle string pio instructions that cross pages or that
1155 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
1156 */
1157 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
1158 unsigned long value = 0;
1160 pio_opp->flags |= OVERLAP;
1161 if (dir == IOREQ_WRITE)
1162 hvm_copy(&value, addr, size, HVM_COPY_IN);
1163 send_pio_req(regs, port, 1, size, value, dir, 0);
1164 } else {
1165 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
1166 if (sign > 0)
1167 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1168 else
1169 count = (addr & ~PAGE_MASK) / size;
1170 } else
1171 regs->eip += inst_len;
1173 send_pio_req(regs, port, count, size, addr, dir, 1);
1175 } else {
1176 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1177 hvm_print_line(current, regs->eax); /* guest debug output */
1179 regs->eip += inst_len;
1180 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
1184 int
1185 vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
1187 unsigned long inst_len;
1188 int error = 0;
1190 error |= __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1191 error |= __vmread(GUEST_RIP, &c->eip);
1192 c->eip += inst_len; /* skip transition instruction */
1193 error |= __vmread(GUEST_RSP, &c->esp);
1194 error |= __vmread(GUEST_RFLAGS, &c->eflags);
1196 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
1197 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
1198 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
1200 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
1201 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
1203 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
1204 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
1206 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
1207 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
1208 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
1209 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
1211 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
1212 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
1213 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
1214 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
1216 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
1217 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
1218 error |= __vmread(GUEST_ES_BASE, &c->es_base);
1219 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
1221 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
1222 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
1223 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
1224 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
1226 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
1227 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
1228 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
1229 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
1231 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
1232 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
1233 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
1234 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
1236 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
1237 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
1238 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
1239 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
1241 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
1242 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
1243 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
1244 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
1246 return !error;
1249 int
1250 vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
1252 unsigned long mfn, old_cr4, old_base_mfn;
1253 int error = 0;
1255 error |= __vmwrite(GUEST_RIP, c->eip);
1256 error |= __vmwrite(GUEST_RSP, c->esp);
1257 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
1259 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
1261 if (!vmx_paging_enabled(v))
1262 goto skip_cr3;
1264 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
1265 /*
1266 * This is simple TLB flush, implying the guest has
1267 * removed some translation or changed page attributes.
1268 * We simply invalidate the shadow.
1269 */
1270 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1271 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1272 printk("Invalid CR3 value=%x", c->cr3);
1273 domain_crash_synchronous();
1274 return 0;
1276 } else {
1277 /*
1278 * If different, make a shadow. Check if the PDBR is valid
1279 * first.
1280 */
1281 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1282 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1283 printk("Invalid CR3 value=%x", c->cr3);
1284 domain_crash_synchronous();
1285 return 0;
1287 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1288 if(!get_page(mfn_to_page(mfn), v->domain))
1289 return 0;
1290 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1291 v->arch.guest_table = pagetable_from_pfn(mfn);
1292 if (old_base_mfn)
1293 put_page(mfn_to_page(old_base_mfn));
1294 /*
1295 * arch.shadow_table should now hold the next CR3 for shadow
1296 */
1297 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1300 skip_cr3:
1302 shadow_update_paging_modes(v);
1303 if (!vmx_paging_enabled(v))
1304 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
1305 else
1306 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1307 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1309 error |= __vmread(CR4_READ_SHADOW, &old_cr4);
1310 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1311 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1313 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1314 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1316 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1317 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1319 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1320 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1321 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1322 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1324 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1325 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1326 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1327 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1329 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1330 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1331 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1332 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1334 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1335 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1336 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1337 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1339 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1340 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1341 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1342 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1344 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1345 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1346 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1347 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1349 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1350 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1351 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1352 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1354 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1355 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1356 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1357 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1359 return !error;
1362 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1364 int
1365 vmx_assist(struct vcpu *v, int mode)
1367 struct vmx_assist_context c;
1368 u32 magic;
1369 u32 cp;
1371 /* make sure vmxassist exists (this is not an error) */
1372 if (!hvm_copy(&magic, VMXASSIST_MAGIC_OFFSET, sizeof(magic), HVM_COPY_IN))
1373 return 0;
1374 if (magic != VMXASSIST_MAGIC)
1375 return 0;
1377 switch (mode) {
1378 /*
1379 * Transfer control to vmxassist.
1380 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1381 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1382 * by vmxassist and will transfer control to it.
1383 */
1384 case VMX_ASSIST_INVOKE:
1385 /* save the old context */
1386 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1387 goto error;
1388 if (cp != 0) {
1389 if (!vmx_world_save(v, &c))
1390 goto error;
1391 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_OUT))
1392 goto error;
1395 /* restore the new context, this should activate vmxassist */
1396 if (!hvm_copy(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp), HVM_COPY_IN))
1397 goto error;
1398 if (cp != 0) {
1399 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1400 goto error;
1401 if (!vmx_world_restore(v, &c))
1402 goto error;
1403 return 1;
1405 break;
1407 /*
1408 * Restore the VMXASSIST_OLD_CONTEXT that was saved by VMX_ASSIST_INVOKE
1409 * above.
1410 */
1411 case VMX_ASSIST_RESTORE:
1412 /* save the old context */
1413 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1414 goto error;
1415 if (cp != 0) {
1416 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1417 goto error;
1418 if (!vmx_world_restore(v, &c))
1419 goto error;
1420 return 1;
1422 break;
1425 error:
1426 printf("Failed to transfer to vmxassist\n");
1427 domain_crash_synchronous();
1428 return 0;
1431 static int vmx_set_cr0(unsigned long value)
1433 struct vcpu *v = current;
1434 unsigned long mfn;
1435 unsigned long eip;
1436 int paging_enabled;
1437 unsigned long vm_entry_value;
1438 unsigned long old_cr0;
1439 unsigned long old_base_mfn;
1441 /*
1442 * CR0: We don't want to lose PE and PG.
1443 */
1444 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1445 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1447 /* TS cleared? Then initialise FPU now. */
1448 if ( !(value & X86_CR0_TS) )
1450 setup_fpu(v);
1451 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1454 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1455 __vmwrite(CR0_READ_SHADOW, value);
1457 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1459 if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
1461 /*
1462 * Trying to enable guest paging.
1463 * The guest CR3 must be pointing to the guest physical.
1464 */
1465 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1466 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1467 !get_page(mfn_to_page(mfn), v->domain) )
1469 printk("Invalid CR3 value = %lx (mfn=%lx)\n",
1470 v->arch.hvm_vmx.cpu_cr3, mfn);
1471 domain_crash_synchronous(); /* need to take a clean path */
1474 #if defined(__x86_64__)
1475 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1476 &v->arch.hvm_vmx.cpu_state) &&
1477 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
1478 &v->arch.hvm_vmx.cpu_state) )
1480 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enabled\n");
1481 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1484 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1485 &v->arch.hvm_vmx.cpu_state) )
1487 /* Here the PAE is should be opened */
1488 HVM_DBG_LOG(DBG_LEVEL_1, "Enable long mode\n");
1489 set_bit(VMX_CPU_STATE_LMA_ENABLED,
1490 &v->arch.hvm_vmx.cpu_state);
1492 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1493 vm_entry_value |= VM_ENTRY_CONTROLS_IA32E_MODE;
1494 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1496 #endif
1498 /*
1499 * Now arch.guest_table points to machine physical.
1500 */
1501 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1502 v->arch.guest_table = pagetable_from_pfn(mfn);
1503 if (old_base_mfn)
1504 put_page(mfn_to_page(old_base_mfn));
1505 shadow_update_paging_modes(v);
1507 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1508 (unsigned long) (mfn << PAGE_SHIFT));
1510 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1511 /*
1512 * arch->shadow_table should hold the next CR3 for shadow
1513 */
1514 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1515 v->arch.hvm_vmx.cpu_cr3, mfn);
1518 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1519 if ( v->arch.hvm_vmx.cpu_cr3 ) {
1520 put_page(mfn_to_page(get_mfn_from_gpfn(
1521 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1522 v->arch.guest_table = pagetable_null();
1525 /*
1526 * VMX does not implement real-mode virtualization. We emulate
1527 * real-mode by performing a world switch to VMXAssist whenever
1528 * a partition disables the CR0.PE bit.
1529 */
1530 if ( (value & X86_CR0_PE) == 0 )
1532 if ( value & X86_CR0_PG ) {
1533 /* inject GP here */
1534 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1535 return 0;
1536 } else {
1537 /*
1538 * Disable paging here.
1539 * Same to PE == 1 && PG == 0
1540 */
1541 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED,
1542 &v->arch.hvm_vmx.cpu_state) )
1544 clear_bit(VMX_CPU_STATE_LMA_ENABLED,
1545 &v->arch.hvm_vmx.cpu_state);
1546 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1547 vm_entry_value &= ~VM_ENTRY_CONTROLS_IA32E_MODE;
1548 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1552 if ( vmx_assist(v, VMX_ASSIST_INVOKE) ) {
1553 set_bit(VMX_CPU_STATE_ASSIST_ENABLED, &v->arch.hvm_vmx.cpu_state);
1554 __vmread(GUEST_RIP, &eip);
1555 HVM_DBG_LOG(DBG_LEVEL_1,
1556 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1557 return 0; /* do not update eip! */
1559 } else if ( test_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1560 &v->arch.hvm_vmx.cpu_state) )
1562 __vmread(GUEST_RIP, &eip);
1563 HVM_DBG_LOG(DBG_LEVEL_1,
1564 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1565 if ( vmx_assist(v, VMX_ASSIST_RESTORE) )
1567 clear_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1568 &v->arch.hvm_vmx.cpu_state);
1569 __vmread(GUEST_RIP, &eip);
1570 HVM_DBG_LOG(DBG_LEVEL_1,
1571 "Restoring to %%eip 0x%lx\n", eip);
1572 return 0; /* do not update eip! */
1575 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1577 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1578 shadow_update_paging_modes(v);
1581 return 1;
1584 #define CASE_SET_REG(REG, reg) \
1585 case REG_ ## REG: regs->reg = value; break
1586 #define CASE_GET_REG(REG, reg) \
1587 case REG_ ## REG: value = regs->reg; break
1589 #define CASE_EXTEND_SET_REG \
1590 CASE_EXTEND_REG(S)
1591 #define CASE_EXTEND_GET_REG \
1592 CASE_EXTEND_REG(G)
1594 #ifdef __i386__
1595 #define CASE_EXTEND_REG(T)
1596 #else
1597 #define CASE_EXTEND_REG(T) \
1598 CASE_ ## T ## ET_REG(R8, r8); \
1599 CASE_ ## T ## ET_REG(R9, r9); \
1600 CASE_ ## T ## ET_REG(R10, r10); \
1601 CASE_ ## T ## ET_REG(R11, r11); \
1602 CASE_ ## T ## ET_REG(R12, r12); \
1603 CASE_ ## T ## ET_REG(R13, r13); \
1604 CASE_ ## T ## ET_REG(R14, r14); \
1605 CASE_ ## T ## ET_REG(R15, r15)
1606 #endif
1608 /*
1609 * Write to control registers
1610 */
1611 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1613 unsigned long value;
1614 unsigned long old_cr;
1615 struct vcpu *v = current;
1617 switch ( gp ) {
1618 CASE_GET_REG(EAX, eax);
1619 CASE_GET_REG(ECX, ecx);
1620 CASE_GET_REG(EDX, edx);
1621 CASE_GET_REG(EBX, ebx);
1622 CASE_GET_REG(EBP, ebp);
1623 CASE_GET_REG(ESI, esi);
1624 CASE_GET_REG(EDI, edi);
1625 CASE_EXTEND_GET_REG;
1626 case REG_ESP:
1627 __vmread(GUEST_RSP, &value);
1628 break;
1629 default:
1630 printk("invalid gp: %d\n", gp);
1631 __hvm_bug(regs);
1634 HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
1636 switch ( cr ) {
1637 case 0:
1638 return vmx_set_cr0(value);
1639 case 3:
1641 unsigned long old_base_mfn, mfn;
1643 /*
1644 * If paging is not enabled yet, simply copy the value to CR3.
1645 */
1646 if (!vmx_paging_enabled(v)) {
1647 v->arch.hvm_vmx.cpu_cr3 = value;
1648 break;
1651 /*
1652 * We make a new one if the shadow does not exist.
1653 */
1654 if (value == v->arch.hvm_vmx.cpu_cr3) {
1655 /*
1656 * This is simple TLB flush, implying the guest has
1657 * removed some translation or changed page attributes.
1658 * We simply invalidate the shadow.
1659 */
1660 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1661 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1662 __hvm_bug(regs);
1663 shadow_update_cr3(v);
1664 } else {
1665 /*
1666 * If different, make a shadow. Check if the PDBR is valid
1667 * first.
1668 */
1669 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1670 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1671 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1672 !get_page(mfn_to_page(mfn), v->domain) )
1674 printk("Invalid CR3 value=%lx", value);
1675 domain_crash_synchronous(); /* need to take a clean path */
1677 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1678 v->arch.guest_table = pagetable_from_pfn(mfn);
1679 if (old_base_mfn)
1680 put_page(mfn_to_page(old_base_mfn));
1681 /*
1682 * arch.shadow_table should now hold the next CR3 for shadow
1683 */
1684 v->arch.hvm_vmx.cpu_cr3 = value;
1685 update_cr3(v);
1686 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1687 value);
1688 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1690 break;
1692 case 4: /* CR4 */
1694 __vmread(CR4_READ_SHADOW, &old_cr);
1696 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1698 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1700 if ( vmx_pgbit_test(v) )
1702 /* The guest is a 32-bit PAE guest. */
1703 #if CONFIG_PAGING_LEVELS >= 3
1704 unsigned long mfn, old_base_mfn;
1706 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1707 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1708 !get_page(mfn_to_page(mfn), v->domain) )
1710 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1711 domain_crash_synchronous(); /* need to take a clean path */
1715 /*
1716 * Now arch.guest_table points to machine physical.
1717 */
1719 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1720 v->arch.guest_table = pagetable_from_pfn(mfn);
1721 if ( old_base_mfn )
1722 put_page(mfn_to_page(old_base_mfn));
1724 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1725 (unsigned long) (mfn << PAGE_SHIFT));
1727 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1729 /*
1730 * arch->shadow_table should hold the next CR3 for shadow
1731 */
1733 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1734 v->arch.hvm_vmx.cpu_cr3, mfn);
1735 #endif
1738 else if ( value & X86_CR4_PAE )
1739 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1740 else
1742 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED, &v->arch.hvm_vmx.cpu_state) )
1743 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1745 clear_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1748 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1749 __vmwrite(CR4_READ_SHADOW, value);
1751 /*
1752 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1753 * all TLB entries except global entries.
1754 */
1755 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1756 shadow_update_paging_modes(v);
1757 break;
1759 default:
1760 printk("invalid cr: %d\n", gp);
1761 __hvm_bug(regs);
1764 return 1;
1767 /*
1768 * Read from control registers. CR0 and CR4 are read from the shadow.
1769 */
1770 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1772 unsigned long value;
1773 struct vcpu *v = current;
1775 if ( cr != 3 )
1776 __hvm_bug(regs);
1778 value = (unsigned long) v->arch.hvm_vmx.cpu_cr3;
1780 switch ( gp ) {
1781 CASE_SET_REG(EAX, eax);
1782 CASE_SET_REG(ECX, ecx);
1783 CASE_SET_REG(EDX, edx);
1784 CASE_SET_REG(EBX, ebx);
1785 CASE_SET_REG(EBP, ebp);
1786 CASE_SET_REG(ESI, esi);
1787 CASE_SET_REG(EDI, edi);
1788 CASE_EXTEND_SET_REG;
1789 case REG_ESP:
1790 __vmwrite(GUEST_RSP, value);
1791 regs->esp = value;
1792 break;
1793 default:
1794 printk("invalid gp: %d\n", gp);
1795 __hvm_bug(regs);
1798 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
1801 static int vmx_cr_access(unsigned long exit_qualification, struct cpu_user_regs *regs)
1803 unsigned int gp, cr;
1804 unsigned long value;
1805 struct vcpu *v = current;
1807 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1808 case TYPE_MOV_TO_CR:
1809 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1810 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1811 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1812 TRACE_VMEXIT(2,cr);
1813 TRACE_VMEXIT(3,gp);
1814 return mov_to_cr(gp, cr, regs);
1815 case TYPE_MOV_FROM_CR:
1816 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1817 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1818 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1819 TRACE_VMEXIT(2,cr);
1820 TRACE_VMEXIT(3,gp);
1821 mov_from_cr(cr, gp, regs);
1822 break;
1823 case TYPE_CLTS:
1824 TRACE_VMEXIT(1,TYPE_CLTS);
1826 /* We initialise the FPU now, to avoid needing another vmexit. */
1827 setup_fpu(v);
1828 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1830 __vmread_vcpu(v, GUEST_CR0, &value);
1831 value &= ~X86_CR0_TS; /* clear TS */
1832 __vmwrite(GUEST_CR0, value);
1834 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1835 value &= ~X86_CR0_TS; /* clear TS */
1836 __vmwrite(CR0_READ_SHADOW, value);
1837 break;
1838 case TYPE_LMSW:
1839 TRACE_VMEXIT(1,TYPE_LMSW);
1840 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1841 value = (value & ~0xF) |
1842 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1843 return vmx_set_cr0(value);
1844 break;
1845 default:
1846 __hvm_bug(regs);
1847 break;
1849 return 1;
1852 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1854 u64 msr_content = 0;
1855 u32 eax, edx;
1856 struct vcpu *v = current;
1858 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1859 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1860 (unsigned long)regs->edx);
1861 switch (regs->ecx) {
1862 case MSR_IA32_TIME_STAMP_COUNTER:
1863 msr_content = hvm_get_guest_time(v);
1864 break;
1865 case MSR_IA32_SYSENTER_CS:
1866 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1867 break;
1868 case MSR_IA32_SYSENTER_ESP:
1869 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1870 break;
1871 case MSR_IA32_SYSENTER_EIP:
1872 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1873 break;
1874 case MSR_IA32_APICBASE:
1875 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1876 break;
1877 default:
1878 if (long_mode_do_msr_read(regs))
1879 return;
1881 if ( rdmsr_hypervisor_regs(regs->ecx, &eax, &edx) )
1883 regs->eax = eax;
1884 regs->edx = edx;
1885 return;
1888 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1889 break;
1892 regs->eax = msr_content & 0xFFFFFFFF;
1893 regs->edx = msr_content >> 32;
1895 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1896 "ecx=%lx, eax=%lx, edx=%lx",
1897 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1898 (unsigned long)regs->edx);
1901 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1903 u64 msr_content;
1904 struct vcpu *v = current;
1906 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1907 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1908 (unsigned long)regs->edx);
1910 msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
1912 switch (regs->ecx) {
1913 case MSR_IA32_TIME_STAMP_COUNTER:
1914 hvm_set_guest_time(v, msr_content);
1915 break;
1916 case MSR_IA32_SYSENTER_CS:
1917 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1918 break;
1919 case MSR_IA32_SYSENTER_ESP:
1920 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1921 break;
1922 case MSR_IA32_SYSENTER_EIP:
1923 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1924 break;
1925 case MSR_IA32_APICBASE:
1926 vlapic_msr_set(VLAPIC(v), msr_content);
1927 break;
1928 default:
1929 if ( !long_mode_do_msr_write(regs) )
1930 wrmsr_hypervisor_regs(regs->ecx, regs->eax, regs->edx);
1931 break;
1934 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1935 "ecx=%lx, eax=%lx, edx=%lx",
1936 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1937 (unsigned long)regs->edx);
1940 void vmx_vmexit_do_hlt(void)
1942 unsigned long rflags;
1943 __vmread(GUEST_RFLAGS, &rflags);
1944 hvm_hlt(rflags);
1947 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
1949 unsigned int vector;
1950 int error;
1952 asmlinkage void do_IRQ(struct cpu_user_regs *);
1953 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
1954 fastcall void smp_event_check_interrupt(void);
1955 fastcall void smp_invalidate_interrupt(void);
1956 fastcall void smp_call_function_interrupt(void);
1957 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
1958 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
1959 #ifdef CONFIG_X86_MCE_P4THERMAL
1960 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
1961 #endif
1963 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1964 && !(vector & INTR_INFO_VALID_MASK))
1965 __hvm_bug(regs);
1967 vector &= INTR_INFO_VECTOR_MASK;
1968 TRACE_VMEXIT(1,vector);
1970 switch(vector) {
1971 case LOCAL_TIMER_VECTOR:
1972 smp_apic_timer_interrupt(regs);
1973 break;
1974 case EVENT_CHECK_VECTOR:
1975 smp_event_check_interrupt();
1976 break;
1977 case INVALIDATE_TLB_VECTOR:
1978 smp_invalidate_interrupt();
1979 break;
1980 case CALL_FUNCTION_VECTOR:
1981 smp_call_function_interrupt();
1982 break;
1983 case SPURIOUS_APIC_VECTOR:
1984 smp_spurious_interrupt(regs);
1985 break;
1986 case ERROR_APIC_VECTOR:
1987 smp_error_interrupt(regs);
1988 break;
1989 #ifdef CONFIG_X86_MCE_P4THERMAL
1990 case THERMAL_APIC_VECTOR:
1991 smp_thermal_interrupt(regs);
1992 break;
1993 #endif
1994 default:
1995 regs->entry_vector = vector;
1996 do_IRQ(regs);
1997 break;
2001 #if defined (__x86_64__)
2002 void store_cpu_user_regs(struct cpu_user_regs *regs)
2004 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2005 __vmread(GUEST_RSP, &regs->rsp);
2006 __vmread(GUEST_RFLAGS, &regs->rflags);
2007 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2008 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2009 __vmread(GUEST_ES_SELECTOR, &regs->es);
2010 __vmread(GUEST_RIP, &regs->rip);
2012 #elif defined (__i386__)
2013 void store_cpu_user_regs(struct cpu_user_regs *regs)
2015 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2016 __vmread(GUEST_RSP, &regs->esp);
2017 __vmread(GUEST_RFLAGS, &regs->eflags);
2018 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2019 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2020 __vmread(GUEST_ES_SELECTOR, &regs->es);
2021 __vmread(GUEST_RIP, &regs->eip);
2023 #endif
2025 #ifdef XEN_DEBUGGER
2026 void save_cpu_user_regs(struct cpu_user_regs *regs)
2028 __vmread(GUEST_SS_SELECTOR, &regs->xss);
2029 __vmread(GUEST_RSP, &regs->esp);
2030 __vmread(GUEST_RFLAGS, &regs->eflags);
2031 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
2032 __vmread(GUEST_RIP, &regs->eip);
2034 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
2035 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
2036 __vmread(GUEST_ES_SELECTOR, &regs->xes);
2037 __vmread(GUEST_DS_SELECTOR, &regs->xds);
2040 void restore_cpu_user_regs(struct cpu_user_regs *regs)
2042 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
2043 __vmwrite(GUEST_RSP, regs->esp);
2044 __vmwrite(GUEST_RFLAGS, regs->eflags);
2045 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
2046 __vmwrite(GUEST_RIP, regs->eip);
2048 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
2049 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
2050 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
2051 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
2053 #endif
2055 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs regs)
2057 unsigned int exit_reason;
2058 unsigned long exit_qualification, rip, inst_len = 0;
2059 struct vcpu *v = current;
2061 __vmread(VM_EXIT_REASON, &exit_reason);
2063 perfc_incra(vmexits, exit_reason);
2065 if ( (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT) &&
2066 (exit_reason != EXIT_REASON_VMCALL) &&
2067 (exit_reason != EXIT_REASON_IO_INSTRUCTION) )
2068 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
2070 if ( exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT )
2071 local_irq_enable();
2073 if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
2075 unsigned int failed_vmentry_reason = exit_reason & 0xFFFF;
2077 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2078 printk("Failed vm entry (exit reason 0x%x) ", exit_reason);
2079 switch ( failed_vmentry_reason ) {
2080 case EXIT_REASON_INVALID_GUEST_STATE:
2081 printk("caused by invalid guest state (%ld).\n", exit_qualification);
2082 break;
2083 case EXIT_REASON_MSR_LOADING:
2084 printk("caused by MSR entry %ld loading.\n", exit_qualification);
2085 break;
2086 case EXIT_REASON_MACHINE_CHECK:
2087 printk("caused by machine check.\n");
2088 break;
2089 default:
2090 printk("reason not known yet!");
2091 break;
2094 printk("************* VMCS Area **************\n");
2095 vmcs_dump_vcpu();
2096 printk("**************************************\n");
2097 domain_crash_synchronous();
2100 TRACE_VMEXIT(0,exit_reason);
2102 switch ( exit_reason ) {
2103 case EXIT_REASON_EXCEPTION_NMI:
2105 /*
2106 * We don't set the software-interrupt exiting (INT n).
2107 * (1) We can get an exception (e.g. #PG) in the guest, or
2108 * (2) NMI
2109 */
2110 unsigned int vector;
2111 unsigned long va;
2113 if ( __vmread(VM_EXIT_INTR_INFO, &vector) ||
2114 !(vector & INTR_INFO_VALID_MASK) )
2115 domain_crash_synchronous();
2116 vector &= INTR_INFO_VECTOR_MASK;
2118 TRACE_VMEXIT(1,vector);
2119 perfc_incra(cause_vector, vector);
2121 switch ( vector ) {
2122 #ifdef XEN_DEBUGGER
2123 case TRAP_debug:
2125 save_cpu_user_regs(&regs);
2126 pdb_handle_exception(1, &regs, 1);
2127 restore_cpu_user_regs(&regs);
2128 break;
2130 case TRAP_int3:
2132 save_cpu_user_regs(&regs);
2133 pdb_handle_exception(3, &regs, 1);
2134 restore_cpu_user_regs(&regs);
2135 break;
2137 #else
2138 case TRAP_debug:
2140 void store_cpu_user_regs(struct cpu_user_regs *regs);
2142 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2144 store_cpu_user_regs(&regs);
2145 domain_pause_for_debugger();
2146 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2147 PENDING_DEBUG_EXC_BS);
2149 else
2151 vmx_reflect_exception(v);
2152 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2153 PENDING_DEBUG_EXC_BS);
2156 break;
2158 case TRAP_int3:
2160 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2161 domain_pause_for_debugger();
2162 else
2163 vmx_reflect_exception(v);
2164 break;
2166 #endif
2167 case TRAP_no_device:
2169 vmx_do_no_device_fault();
2170 break;
2172 case TRAP_page_fault:
2174 __vmread(EXIT_QUALIFICATION, &va);
2175 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs.error_code);
2177 TRACE_VMEXIT(3,regs.error_code);
2178 TRACE_VMEXIT(4,va);
2180 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2181 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2182 (unsigned long)regs.eax, (unsigned long)regs.ebx,
2183 (unsigned long)regs.ecx, (unsigned long)regs.edx,
2184 (unsigned long)regs.esi, (unsigned long)regs.edi);
2186 if ( !vmx_do_page_fault(va, &regs) ) {
2187 /*
2188 * Inject #PG using Interruption-Information Fields
2189 */
2190 vmx_inject_hw_exception(v, TRAP_page_fault, regs.error_code);
2191 v->arch.hvm_vmx.cpu_cr2 = va;
2192 TRACE_3D(TRC_VMX_INT, v->domain->domain_id, TRAP_page_fault, va);
2194 break;
2196 case TRAP_nmi:
2197 do_nmi(&regs);
2198 break;
2199 default:
2200 vmx_reflect_exception(v);
2201 break;
2203 break;
2205 case EXIT_REASON_EXTERNAL_INTERRUPT:
2206 vmx_vmexit_do_extint(&regs);
2207 break;
2208 case EXIT_REASON_TRIPLE_FAULT:
2209 domain_crash_synchronous();
2210 break;
2211 case EXIT_REASON_PENDING_INTERRUPT:
2212 /*
2213 * Not sure exactly what the purpose of this is. The only bits set
2214 * and cleared at this point are CPU_BASED_VIRTUAL_INTR_PENDING.
2215 * (in io.c:{enable,disable}_irq_window(). So presumably we want to
2216 * set it to the original value...
2217 */
2218 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2219 v->arch.hvm_vcpu.u.vmx.exec_control |=
2220 (MONITOR_CPU_BASED_EXEC_CONTROLS & CPU_BASED_VIRTUAL_INTR_PENDING);
2221 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
2222 v->arch.hvm_vcpu.u.vmx.exec_control);
2223 break;
2224 case EXIT_REASON_TASK_SWITCH:
2225 domain_crash_synchronous();
2226 break;
2227 case EXIT_REASON_CPUID:
2228 vmx_vmexit_do_cpuid(&regs);
2229 __get_instruction_length(inst_len);
2230 __update_guest_eip(inst_len);
2231 break;
2232 case EXIT_REASON_HLT:
2233 __get_instruction_length(inst_len);
2234 __update_guest_eip(inst_len);
2235 vmx_vmexit_do_hlt();
2236 break;
2237 case EXIT_REASON_INVLPG:
2239 unsigned long va;
2241 __vmread(EXIT_QUALIFICATION, &va);
2242 vmx_vmexit_do_invlpg(va);
2243 __get_instruction_length(inst_len);
2244 __update_guest_eip(inst_len);
2245 break;
2247 case EXIT_REASON_VMCALL:
2249 __get_instruction_length(inst_len);
2250 __vmread(GUEST_RIP, &rip);
2251 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2253 hvm_do_hypercall(&regs);
2254 __update_guest_eip(inst_len);
2255 break;
2257 case EXIT_REASON_CR_ACCESS:
2259 __vmread(GUEST_RIP, &rip);
2260 __get_instruction_length(inst_len);
2261 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2263 HVM_DBG_LOG(DBG_LEVEL_1, "rip = %lx, inst_len =%lx, exit_qualification = %lx",
2264 rip, inst_len, exit_qualification);
2265 if ( vmx_cr_access(exit_qualification, &regs) )
2266 __update_guest_eip(inst_len);
2267 TRACE_VMEXIT(3,regs.error_code);
2268 TRACE_VMEXIT(4,exit_qualification);
2269 break;
2271 case EXIT_REASON_DR_ACCESS:
2272 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2273 vmx_dr_access(exit_qualification, &regs);
2274 break;
2275 case EXIT_REASON_IO_INSTRUCTION:
2276 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2277 __get_instruction_length(inst_len);
2278 vmx_io_instruction(exit_qualification, inst_len);
2279 TRACE_VMEXIT(4,exit_qualification);
2280 break;
2281 case EXIT_REASON_MSR_READ:
2282 __get_instruction_length(inst_len);
2283 vmx_do_msr_read(&regs);
2284 __update_guest_eip(inst_len);
2285 break;
2286 case EXIT_REASON_MSR_WRITE:
2287 vmx_do_msr_write(&regs);
2288 __get_instruction_length(inst_len);
2289 __update_guest_eip(inst_len);
2290 break;
2291 case EXIT_REASON_MWAIT_INSTRUCTION:
2292 case EXIT_REASON_MONITOR_INSTRUCTION:
2293 case EXIT_REASON_PAUSE_INSTRUCTION:
2294 domain_crash_synchronous();
2295 break;
2296 case EXIT_REASON_VMCLEAR:
2297 case EXIT_REASON_VMLAUNCH:
2298 case EXIT_REASON_VMPTRLD:
2299 case EXIT_REASON_VMPTRST:
2300 case EXIT_REASON_VMREAD:
2301 case EXIT_REASON_VMRESUME:
2302 case EXIT_REASON_VMWRITE:
2303 case EXIT_REASON_VMXOFF:
2304 case EXIT_REASON_VMXON:
2305 /* Report invalid opcode exception when a VMX guest tries to execute
2306 any of the VMX instructions */
2307 vmx_inject_hw_exception(v, TRAP_invalid_op, VMX_DELIVER_NO_ERROR_CODE);
2308 break;
2310 default:
2311 domain_crash_synchronous(); /* should not happen */
2315 asmlinkage void vmx_load_cr2(void)
2317 struct vcpu *v = current;
2319 local_irq_disable();
2320 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2323 asmlinkage void vmx_trace_vmentry (void)
2325 TRACE_5D(TRC_VMX_VMENTRY,
2326 this_cpu(trace_values)[0],
2327 this_cpu(trace_values)[1],
2328 this_cpu(trace_values)[2],
2329 this_cpu(trace_values)[3],
2330 this_cpu(trace_values)[4]);
2331 TRACE_VMEXIT(0,9);
2332 TRACE_VMEXIT(1,9);
2333 TRACE_VMEXIT(2,9);
2334 TRACE_VMEXIT(3,9);
2335 TRACE_VMEXIT(4,9);
2336 return;
2339 asmlinkage void vmx_trace_vmexit (void)
2341 TRACE_3D(TRC_VMX_VMEXIT,0,0,0);
2342 return;
2345 /*
2346 * Local variables:
2347 * mode: C
2348 * c-set-style: "BSD"
2349 * c-basic-offset: 4
2350 * tab-width: 4
2351 * indent-tabs-mode: nil
2352 * End:
2353 */