ia64/xen-unstable

view xen/include/asm-x86/processor.h @ 10892:0d2ba35c0cf2

[XEN] Add hypercall support for HVM guests. This is
fairly useless at the moment, since all of the hypercalls
fail, since copy_from_user doesn't work correctly in HVM
domains.

Signed-off-by: Steven Smith <ssmith@xensource.com>

Add a CPUID hypervisor platform interface at leaf
0x40000000. Allow hypercall transfer page to be filled
in via MSR 0x40000000.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Tue Aug 01 17:18:05 2006 +0100 (2006-08-01)
parents 8e55c5c11475
children d20e1835c24b
line source
2 /* Portions are: Copyright (c) 1994 Linus Torvalds */
4 #ifndef __ASM_X86_PROCESSOR_H
5 #define __ASM_X86_PROCESSOR_H
7 #ifndef __ASSEMBLY__
8 #include <xen/config.h>
9 #include <xen/cache.h>
10 #include <xen/types.h>
11 #include <public/xen.h>
12 #include <asm/types.h>
13 #include <asm/cpufeature.h>
14 #include <asm/desc.h>
15 #endif
17 /*
18 * CPU vendor IDs
19 */
20 #define X86_VENDOR_INTEL 0
21 #define X86_VENDOR_CYRIX 1
22 #define X86_VENDOR_AMD 2
23 #define X86_VENDOR_UMC 3
24 #define X86_VENDOR_NEXGEN 4
25 #define X86_VENDOR_CENTAUR 5
26 #define X86_VENDOR_RISE 6
27 #define X86_VENDOR_TRANSMETA 7
28 #define X86_VENDOR_NSC 8
29 #define X86_VENDOR_NUM 9
30 #define X86_VENDOR_UNKNOWN 0xff
32 /*
33 * EFLAGS bits
34 */
35 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
36 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
37 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
38 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
39 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
40 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
41 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
42 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
43 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
44 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
45 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
46 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
47 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
48 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
49 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
50 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
51 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
53 /*
54 * Intel CPU flags in CR0
55 */
56 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
57 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
58 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
59 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
60 #define X86_CR0_ET 0x00000010 /* Extension type (RO) */
61 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
62 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
63 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
64 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
65 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
66 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
68 /*
69 * Intel CPU features in CR4
70 */
71 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
72 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
73 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
74 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
75 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
76 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
77 #define X86_CR4_MCE 0x0040 /* Machine check enable */
78 #define X86_CR4_PGE 0x0080 /* enable global pages */
79 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
80 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
81 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
82 #define X86_CR4_VMXE 0x2000 /* enable VMX */
84 /*
85 * Trap/fault mnemonics.
86 */
87 #define TRAP_divide_error 0
88 #define TRAP_debug 1
89 #define TRAP_nmi 2
90 #define TRAP_int3 3
91 #define TRAP_overflow 4
92 #define TRAP_bounds 5
93 #define TRAP_invalid_op 6
94 #define TRAP_no_device 7
95 #define TRAP_double_fault 8
96 #define TRAP_copro_seg 9
97 #define TRAP_invalid_tss 10
98 #define TRAP_no_segment 11
99 #define TRAP_stack_error 12
100 #define TRAP_gp_fault 13
101 #define TRAP_page_fault 14
102 #define TRAP_spurious_int 15
103 #define TRAP_copro_error 16
104 #define TRAP_alignment_check 17
105 #define TRAP_machine_check 18
106 #define TRAP_simd_error 19
107 #define TRAP_deferred_nmi 31
109 /* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ. */
110 /* NB. Same as VGCF_IN_SYSCALL. No bits in common with any other TRAP_ defn. */
111 #define TRAP_syscall 256
113 /*
114 * Non-fatal fault/trap handlers return an error code to the caller. If the
115 * code is non-zero, it means that either the exception was not due to a fault
116 * (i.e., it was a trap) or that the fault has been fixed up so the instruction
117 * replay ought to succeed.
118 */
119 #define EXCRET_not_a_fault 1 /* It was a trap. No instruction replay needed. */
120 #define EXCRET_fault_fixed 1 /* It was fault that we fixed: try a replay. */
122 /* 'trap_bounce' flags values */
123 #define TBF_EXCEPTION 1
124 #define TBF_EXCEPTION_ERRCODE 2
125 #define TBF_INTERRUPT 8
126 #define TBF_FAILSAFE 16
128 /* 'arch_vcpu' flags values */
129 #define _TF_kernel_mode 0
130 #define TF_kernel_mode (1<<_TF_kernel_mode)
132 /* #PF error code values. */
133 #define PGERR_page_present (1U<<0)
134 #define PGERR_write_access (1U<<1)
135 #define PGERR_user_mode (1U<<2)
136 #define PGERR_reserved_bit (1U<<3)
137 #define PGERR_instr_fetch (1U<<4)
139 #ifndef __ASSEMBLY__
141 struct domain;
142 struct vcpu;
144 /*
145 * Default implementation of macro that returns current
146 * instruction pointer ("program counter").
147 */
148 #ifdef __x86_64__
149 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
150 #else
151 #define current_text_addr() \
152 ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
153 #endif
155 struct cpuinfo_x86 {
156 __u8 x86; /* CPU family */
157 __u8 x86_vendor; /* CPU vendor */
158 __u8 x86_model;
159 __u8 x86_mask;
160 char wp_works_ok; /* It doesn't on 386's */
161 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
162 char hard_math;
163 char rfu;
164 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
165 unsigned int x86_capability[NCAPINTS];
166 char x86_vendor_id[16];
167 char x86_model_id[64];
168 int x86_cache_size; /* in KB - valid for CPUS which support this call */
169 int x86_cache_alignment; /* In bytes */
170 char fdiv_bug;
171 char f00f_bug;
172 char coma_bug;
173 char pad0;
174 int x86_power;
175 unsigned char x86_max_cores; /* cpuid returned max cores value */
176 unsigned char booted_cores; /* number of cores as seen by OS */
177 unsigned char apicid;
178 } __cacheline_aligned;
180 /*
181 * capabilities of CPUs
182 */
184 extern struct cpuinfo_x86 boot_cpu_data;
186 #ifdef CONFIG_SMP
187 extern struct cpuinfo_x86 cpu_data[];
188 #define current_cpu_data cpu_data[smp_processor_id()]
189 #else
190 #define cpu_data (&boot_cpu_data)
191 #define current_cpu_data boot_cpu_data
192 #endif
194 extern int phys_proc_id[NR_CPUS];
195 extern int cpu_core_id[NR_CPUS];
197 extern void identify_cpu(struct cpuinfo_x86 *);
198 extern void print_cpu_info(struct cpuinfo_x86 *);
199 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
200 extern void dodgy_tsc(void);
202 #ifdef CONFIG_X86_HT
203 extern void detect_ht(struct cpuinfo_x86 *c);
204 #else
205 static always_inline void detect_ht(struct cpuinfo_x86 *c) {}
206 #endif
208 /*
209 * Generic CPUID function
210 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
211 * resulting in stale register contents being returned.
212 */
213 #define cpuid(_op,_eax,_ebx,_ecx,_edx) \
214 __asm__("cpuid" \
215 : "=a" (*(int *)(_eax)), \
216 "=b" (*(int *)(_ebx)), \
217 "=c" (*(int *)(_ecx)), \
218 "=d" (*(int *)(_edx)) \
219 : "0" (_op), "2" (0))
221 /* Some CPUID calls want 'count' to be placed in ecx */
222 static inline void cpuid_count(
223 int op,
224 int count,
225 unsigned int *eax,
226 unsigned int *ebx,
227 unsigned int *ecx,
228 unsigned int *edx)
229 {
230 __asm__("cpuid"
231 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
232 : "0" (op), "c" (count));
233 }
235 /*
236 * CPUID functions returning a single datum
237 */
238 static always_inline unsigned int cpuid_eax(unsigned int op)
239 {
240 unsigned int eax;
242 __asm__("cpuid"
243 : "=a" (eax)
244 : "0" (op)
245 : "bx", "cx", "dx");
246 return eax;
247 }
248 static always_inline unsigned int cpuid_ebx(unsigned int op)
249 {
250 unsigned int eax, ebx;
252 __asm__("cpuid"
253 : "=a" (eax), "=b" (ebx)
254 : "0" (op)
255 : "cx", "dx" );
256 return ebx;
257 }
258 static always_inline unsigned int cpuid_ecx(unsigned int op)
259 {
260 unsigned int eax, ecx;
262 __asm__("cpuid"
263 : "=a" (eax), "=c" (ecx)
264 : "0" (op)
265 : "bx", "dx" );
266 return ecx;
267 }
268 static always_inline unsigned int cpuid_edx(unsigned int op)
269 {
270 unsigned int eax, edx;
272 __asm__("cpuid"
273 : "=a" (eax), "=d" (edx)
274 : "0" (op)
275 : "bx", "cx");
276 return edx;
277 }
280 #define read_cr0() ({ \
281 unsigned long __dummy; \
282 __asm__( \
283 "mov %%cr0,%0\n\t" \
284 :"=r" (__dummy)); \
285 __dummy; \
286 })
288 #define write_cr0(x) \
289 __asm__("mov %0,%%cr0": :"r" ((unsigned long)x));
291 #define read_cr4() ({ \
292 unsigned long __dummy; \
293 __asm__( \
294 "mov %%cr4,%0\n\t" \
295 :"=r" (__dummy)); \
296 __dummy; \
297 })
299 #define write_cr4(x) \
300 __asm__("mov %0,%%cr4": :"r" ((unsigned long)x));
302 /*
303 * Save the cr4 feature set we're using (ie
304 * Pentium 4MB enable and PPro Global page
305 * enable), so that any CPU's that boot up
306 * after us can get the correct flags.
307 */
308 extern unsigned long mmu_cr4_features;
310 static always_inline void set_in_cr4 (unsigned long mask)
311 {
312 unsigned long dummy;
313 mmu_cr4_features |= mask;
314 __asm__ __volatile__ (
315 "mov %%cr4,%0\n\t"
316 "or %1,%0\n\t"
317 "mov %0,%%cr4\n"
318 : "=&r" (dummy) : "irg" (mask) );
319 }
321 static always_inline void clear_in_cr4 (unsigned long mask)
322 {
323 unsigned long dummy;
324 mmu_cr4_features &= ~mask;
325 __asm__ __volatile__ (
326 "mov %%cr4,%0\n\t"
327 "and %1,%0\n\t"
328 "mov %0,%%cr4\n"
329 : "=&r" (dummy) : "irg" (~mask) );
330 }
332 /*
333 * NSC/Cyrix CPU configuration register indexes
334 */
336 #define CX86_PCR0 0x20
337 #define CX86_GCR 0xb8
338 #define CX86_CCR0 0xc0
339 #define CX86_CCR1 0xc1
340 #define CX86_CCR2 0xc2
341 #define CX86_CCR3 0xc3
342 #define CX86_CCR4 0xe8
343 #define CX86_CCR5 0xe9
344 #define CX86_CCR6 0xea
345 #define CX86_CCR7 0xeb
346 #define CX86_PCR1 0xf0
347 #define CX86_DIR0 0xfe
348 #define CX86_DIR1 0xff
349 #define CX86_ARR_BASE 0xc4
350 #define CX86_RCR_BASE 0xdc
352 /*
353 * NSC/Cyrix CPU indexed register access macros
354 */
356 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
358 #define setCx86(reg, data) do { \
359 outb((reg), 0x22); \
360 outb((data), 0x23); \
361 } while (0)
363 /* Stop speculative execution */
364 static inline void sync_core(void)
365 {
366 int tmp;
367 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
368 }
370 static always_inline void __monitor(const void *eax, unsigned long ecx,
371 unsigned long edx)
372 {
373 /* "monitor %eax,%ecx,%edx;" */
374 asm volatile(
375 ".byte 0x0f,0x01,0xc8;"
376 : :"a" (eax), "c" (ecx), "d"(edx));
377 }
379 static always_inline void __mwait(unsigned long eax, unsigned long ecx)
380 {
381 /* "mwait %eax,%ecx;" */
382 asm volatile(
383 ".byte 0x0f,0x01,0xc9;"
384 : :"a" (eax), "c" (ecx));
385 }
387 #define IOBMP_BYTES 8192
388 #define IOBMP_INVALID_OFFSET 0x8000
390 struct tss_struct {
391 unsigned short back_link,__blh;
392 #ifdef __x86_64__
393 u64 rsp0;
394 u64 rsp1;
395 u64 rsp2;
396 u64 reserved1;
397 u64 ist[7];
398 u64 reserved2;
399 u16 reserved3;
400 #else
401 u32 esp0;
402 u16 ss0,__ss0h;
403 u32 esp1;
404 u16 ss1,__ss1h;
405 u32 esp2;
406 u16 ss2,__ss2h;
407 u32 __cr3;
408 u32 eip;
409 u32 eflags;
410 u32 eax,ecx,edx,ebx;
411 u32 esp;
412 u32 ebp;
413 u32 esi;
414 u32 edi;
415 u16 es, __esh;
416 u16 cs, __csh;
417 u16 ss, __ssh;
418 u16 ds, __dsh;
419 u16 fs, __fsh;
420 u16 gs, __gsh;
421 u16 ldt, __ldth;
422 u16 trace;
423 #endif
424 u16 bitmap;
425 /* Pads the TSS to be cacheline-aligned (total size is 0x80). */
426 u8 __cacheline_filler[24];
427 } __cacheline_aligned __attribute__((packed));
429 #define IDT_ENTRIES 256
430 extern idt_entry_t idt_table[];
431 extern idt_entry_t *idt_tables[];
433 extern struct tss_struct init_tss[NR_CPUS];
435 #ifdef CONFIG_X86_32
437 extern void init_int80_direct_trap(struct vcpu *v);
438 #define set_int80_direct_trap(_ed) \
439 (memcpy(idt_tables[(_ed)->processor] + 0x80, \
440 &((_ed)->arch.int80_desc), 8))
442 #else
444 #define init_int80_direct_trap(_ed) ((void)0)
445 #define set_int80_direct_trap(_ed) ((void)0)
447 #endif
449 extern int gpf_emulate_4gb(struct cpu_user_regs *regs);
451 extern void write_ptbase(struct vcpu *v);
453 void destroy_gdt(struct vcpu *d);
454 long set_gdt(struct vcpu *d,
455 unsigned long *frames,
456 unsigned int entries);
458 long set_debugreg(struct vcpu *p, int reg, unsigned long value);
460 struct microcode_header {
461 unsigned int hdrver;
462 unsigned int rev;
463 unsigned int date;
464 unsigned int sig;
465 unsigned int cksum;
466 unsigned int ldrver;
467 unsigned int pf;
468 unsigned int datasize;
469 unsigned int totalsize;
470 unsigned int reserved[3];
471 };
473 struct microcode {
474 struct microcode_header hdr;
475 unsigned int bits[0];
476 };
478 typedef struct microcode microcode_t;
479 typedef struct microcode_header microcode_header_t;
481 /* microcode format is extended from prescott processors */
482 struct extended_signature {
483 unsigned int sig;
484 unsigned int pf;
485 unsigned int cksum;
486 };
488 struct extended_sigtable {
489 unsigned int count;
490 unsigned int cksum;
491 unsigned int reserved[3];
492 struct extended_signature sigs[0];
493 };
495 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
496 static always_inline void rep_nop(void)
497 {
498 __asm__ __volatile__ ( "rep;nop" : : : "memory" );
499 }
501 #define cpu_relax() rep_nop()
503 /* Prefetch instructions for Pentium III and AMD Athlon */
504 #ifdef CONFIG_MPENTIUMIII
506 #define ARCH_HAS_PREFETCH
507 extern always_inline void prefetch(const void *x)
508 {
509 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
510 }
512 #elif CONFIG_X86_USE_3DNOW
514 #define ARCH_HAS_PREFETCH
515 #define ARCH_HAS_PREFETCHW
516 #define ARCH_HAS_SPINLOCK_PREFETCH
518 extern always_inline void prefetch(const void *x)
519 {
520 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
521 }
523 extern always_inline void prefetchw(const void *x)
524 {
525 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
526 }
527 #define spin_lock_prefetch(x) prefetchw(x)
529 #endif
531 void show_stack(struct cpu_user_regs *regs);
532 void show_stack_overflow(unsigned long esp);
533 void show_registers(struct cpu_user_regs *regs);
534 void show_execution_state(struct cpu_user_regs *regs);
535 void show_page_walk(unsigned long addr);
536 asmlinkage void fatal_trap(int trapnr, struct cpu_user_regs *regs);
538 /* Dumps current register and stack state. */
539 #define dump_execution_state() \
540 /* NB. Needs interrupts enabled else we end up in fatal_trap(). */ \
541 __asm__ __volatile__ ( "pushf ; sti ; ud2 ; .ascii \"dbg\" ; popf" )
543 extern void mtrr_ap_init(void);
544 extern void mtrr_bp_init(void);
546 extern void mcheck_init(struct cpuinfo_x86 *c);
548 int cpuid_hypervisor_leaves(
549 uint32_t idx, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
550 int rdmsr_hypervisor_regs(
551 uint32_t idx, uint32_t *eax, uint32_t *edx);
552 int wrmsr_hypervisor_regs(
553 uint32_t idx, uint32_t eax, uint32_t edx);
555 #endif /* !__ASSEMBLY__ */
557 #endif /* __ASM_X86_PROCESSOR_H */
559 /*
560 * Local variables:
561 * mode: C
562 * c-set-style: "BSD"
563 * c-basic-offset: 4
564 * tab-width: 4
565 * indent-tabs-mode: nil
566 * End:
567 */