ia64/xen-unstable

view tools/misc/xen_cpuperf.c @ 854:0cd58ce5a503

bitkeeper revision 1.531 (3f9da0175ZA8nMoVtg9tCQeXL4osyw)

time.c, xen_log.c, xen_cpuperf.c:
Add 'independent_wallclock' cmdline and sysctl options to xenolinux.
author kaf24@scramble.cl.cam.ac.uk
date Mon Oct 27 22:45:43 2003 +0000 (2003-10-27)
parents 399bb8faf92a
children b5c1b4c684f2
line source
1 /*
2 * User mode program to prod MSR values through /proc/perfcntr
3 *
4 *
5 * $Id$
6 *
7 * $Log$
8 */
10 #include <sys/types.h>
11 #include <sched.h>
12 #include <error.h>
13 #include <stdio.h>
14 #include <unistd.h>
15 #include <stdlib.h>
16 #include <string.h>
18 #include "p4perf.h"
19 #include "dom0_defs.h"
21 void dom0_wrmsr( int cpu_mask, int msr, unsigned int low, unsigned int high )
22 {
23 dom0_op_t op;
24 op.cmd = DOM0_MSR;
25 op.u.msr.write = 1;
26 op.u.msr.msr = msr;
27 op.u.msr.cpu_mask = cpu_mask;
28 op.u.msr.in1 = low;
29 op.u.msr.in2 = high;
30 do_dom0_op(&op);
31 }
33 unsigned long long dom0_rdmsr( int cpu_mask, int msr )
34 {
35 dom0_op_t op;
36 op.cmd = DOM0_MSR;
37 op.u.msr.write = 0;
38 op.u.msr.msr = msr;
39 op.u.msr.cpu_mask = cpu_mask;
40 do_dom0_op(&op);
41 return (((unsigned long long)op.u.msr.out2)<<32) | op.u.msr.out1 ;
42 }
44 struct macros {
45 char *name;
46 unsigned long msr_addr;
47 int number;
48 };
50 struct macros msr[] = {
51 {"BPU_COUNTER0", 0x300, 0},
52 {"BPU_COUNTER1", 0x301, 1},
53 {"BPU_COUNTER2", 0x302, 2},
54 {"BPU_COUNTER3", 0x303, 3},
55 {"MS_COUNTER0", 0x304, 4},
56 {"MS_COUNTER1", 0x305, 5},
57 {"MS_COUNTER2", 0x306, 6},
58 {"MS_COUNTER3", 0x307, 7},
59 {"FLAME_COUNTER0", 0x308, 8},
60 {"FLAME_COUNTER1", 0x309, 9},
61 {"FLAME_COUNTER2", 0x30a, 10},
62 {"FLAME_COUNTER3", 0x30b, 11},
63 {"IQ_COUNTER0", 0x30c, 12},
64 {"IQ_COUNTER1", 0x30d, 13},
65 {"IQ_COUNTER2", 0x30e, 14},
66 {"IQ_COUNTER3", 0x30f, 15},
67 {"IQ_COUNTER4", 0x310, 16},
68 {"IQ_COUNTER5", 0x311, 17},
69 {"BPU_CCCR0", 0x360, 0},
70 {"BPU_CCCR1", 0x361, 1},
71 {"BPU_CCCR2", 0x362, 2},
72 {"BPU_CCCR3", 0x363, 3},
73 {"MS_CCCR0", 0x364, 4},
74 {"MS_CCCR1", 0x365, 5},
75 {"MS_CCCR2", 0x366, 6},
76 {"MS_CCCR3", 0x367, 7},
77 {"FLAME_CCCR0", 0x368, 8},
78 {"FLAME_CCCR1", 0x369, 9},
79 {"FLAME_CCCR2", 0x36a, 10},
80 {"FLAME_CCCR3", 0x36b, 11},
81 {"IQ_CCCR0", 0x36c, 12},
82 {"IQ_CCCR1", 0x36d, 13},
83 {"IQ_CCCR2", 0x36e, 14},
84 {"IQ_CCCR3", 0x36f, 15},
85 {"IQ_CCCR4", 0x370, 16},
86 {"IQ_CCCR5", 0x371, 17},
87 {"BSU_ESCR0", 0x3a0, 7},
88 {"BSU_ESCR1", 0x3a1, 7},
89 {"FSB_ESCR0", 0x3a2, 6},
90 {"FSB_ESCR1", 0x3a3, 6},
91 {"MOB_ESCR0", 0x3aa, 2},
92 {"MOB_ESCR1", 0x3ab, 2},
93 {"PMH_ESCR0", 0x3ac, 4},
94 {"PMH_ESCR1", 0x3ad, 4},
95 {"BPU_ESCR0", 0x3b2, 0},
96 {"BPU_ESCR1", 0x3b3, 0},
97 {"IS_ESCR0", 0x3b4, 1},
98 {"IS_ESCR1", 0x3b5, 1},
99 {"ITLB_ESCR0", 0x3b6, 3},
100 {"ITLB_ESCR1", 0x3b7, 3},
101 {"IX_ESCR0", 0x3c8, 5},
102 {"IX_ESCR1", 0x3c9, 5},
103 {"MS_ESCR0", 0x3c0, 0},
104 {"MS_ESCR1", 0x3c1, 0},
105 {"TBPU_ESCR0", 0x3c2, 2},
106 {"TBPU_ESCR1", 0x3c3, 2},
107 {"TC_ESCR0", 0x3c4, 1},
108 {"TC_ESCR1", 0x3c5, 1},
109 {"FIRM_ESCR0", 0x3a4, 1},
110 {"FIRM_ESCR1", 0x3a5, 1},
111 {"FLAME_ESCR0", 0x3a6, 0},
112 {"FLAME_ESCR1", 0x3a7, 0},
113 {"DAC_ESCR0", 0x3a8, 5},
114 {"DAC_ESCR1", 0x3a9, 5},
115 {"SAAT_ESCR0", 0x3ae, 2},
116 {"SAAT_ESCR1", 0x3af, 2},
117 {"U2L_ESCR0", 0x3b0, 3},
118 {"U2L_ESCR1", 0x3b1, 3},
119 {"CRU_ESCR0", 0x3b8, 4},
120 {"CRU_ESCR1", 0x3b9, 4},
121 {"CRU_ESCR2", 0x3cc, 5},
122 {"CRU_ESCR3", 0x3cd, 5},
123 {"CRU_ESCR4", 0x3e0, 6},
124 {"CRU_ESCR5", 0x3e1, 6},
125 {"IQ_ESCR0", 0x3ba, 0},
126 {"IQ_ESCR1", 0x3bb, 0},
127 {"RAT_ESCR0", 0x3bc, 2},
128 {"RAT_ESCR1", 0x3bd, 2},
129 {"SSU_ESCR0", 0x3be, 3},
130 {"SSU_ESCR1", 0x3bf, 3},
131 {"ALF_ESCR0", 0x3ca, 1},
132 {"ALF_ESCR1", 0x3cb, 1},
133 {"PEBS_ENABLE", 0x3f1, 0},
134 {"PEBS_MATRIX_VERT", 0x3f2, 0},
135 {NULL, 0, 0}
136 };
138 struct macros *lookup_macro(char *str)
139 {
140 struct macros *m;
142 m = msr;
143 while (m->name) {
144 if (strcmp(m->name, str) == 0)
145 return m;
146 m++;
147 }
148 return NULL;
149 }
151 int main(int argc, char **argv)
152 {
153 int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
154 unsigned int cpu_mask = 1;
155 struct macros *escr = NULL, *cccr = NULL;
156 unsigned long escr_val, cccr_val;
157 int debug = 0;
158 unsigned long pebs = 0, pebs_vert = 0;
159 int pebs_x = 0, pebs_vert_x = 0;
160 int read = 0;
162 while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:r")) != -1) {
163 switch((char)c) {
164 case 'P':
165 pebs |= 1 << atoi(optarg);
166 pebs_x = 1;
167 break;
168 case 'V':
169 pebs_vert |= 1 << atoi(optarg);
170 pebs_vert_x = 1;
171 break;
172 case 'd':
173 debug = 1;
174 break;
175 case 'c':
176 {
177 int cpu = atoi(optarg);
178 cpu_mask = (cpu == -1)?(~0):(1<<cpu);
179 break;
180 }
181 case 't': // ESCR thread bits
182 t = atoi(optarg);
183 break;
184 case 'e': // eventsel
185 es = atoi(optarg);
186 break;
187 case 'm': // eventmask
188 em = atoi(optarg);
189 break;
190 case 'T': // tag value
191 tv = atoi(optarg);
192 te = 1;
193 break;
194 case 'E':
195 escr = lookup_macro(optarg);
196 if (!escr) {
197 fprintf(stderr, "Macro '%s' not found.\n", optarg);
198 exit(1);
199 }
200 break;
201 case 'C':
202 cccr = lookup_macro(optarg);
203 if (!cccr) {
204 fprintf(stderr, "Macro '%s' not found.\n", optarg);
205 exit(1);
206 }
207 break;
208 case 'r':
209 read = 1;
210 break;
211 }
212 }
214 if (read) {
215 while((cpu_mask&1)) {
216 int i;
217 for (i=0x300;i<0x312;i++)
218 {
219 printf("%010llx ",dom0_rdmsr( cpu_mask, i ) );
220 }
221 printf("\n");
222 cpu_mask>>=1;
223 }
224 exit(1);
225 }
227 if (!escr) {
228 fprintf(stderr, "Need an ESCR.\n");
229 exit(1);
230 }
231 if (!cccr) {
232 fprintf(stderr, "Need a counter number.\n");
233 exit(1);
234 }
236 escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
237 P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
238 cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
239 P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
241 if (debug) {
242 fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
243 fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
244 cccr->msr_addr, cccr_val, cccr->number);
245 if (pebs_x)
246 fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
247 MSR_P4_PEBS_ENABLE, pebs);
248 if (pebs_vert_x)
249 fprintf(stderr, "PMV 0x%x <= 0x%08lx\n",
250 MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
251 }
253 dom0_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
254 dom0_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
256 if (pebs_x)
257 dom0_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
259 if (pebs_vert_x)
260 dom0_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
262 return 0;
263 }