ia64/xen-unstable

view xen/arch/ia64/xen/vcpu.c @ 6468:0c1f966af47e

Temporary patch to return dom0 stability
author djm@kirby.fc.hp.com
date Thu Sep 08 07:24:08 2005 -0600 (2005-09-08)
parents 89fc07f85b01
children 10b1d30d3f66
line source
1 /*
2 * Virtualized CPU functions
3 *
4 * Copyright (C) 2004-2005 Hewlett-Packard Co.
5 * Dan Magenheimer (dan.magenheimer@hp.com)
6 *
7 */
9 #if 1
10 // TEMPORARY PATCH for match_dtlb uses this, can be removed later
11 // FIXME SMP
12 int in_tpa = 0;
13 #endif
15 #include <linux/sched.h>
16 #include <public/arch-ia64.h>
17 #include <asm/ia64_int.h>
18 #include <asm/vcpu.h>
19 #include <asm/regionreg.h>
20 #include <asm/tlb.h>
21 #include <asm/processor.h>
22 #include <asm/delay.h>
23 #include <asm/vmx_vcpu.h>
25 typedef union {
26 struct ia64_psr ia64_psr;
27 unsigned long i64;
28 } PSR;
30 //typedef struct pt_regs REGS;
31 //typedef struct domain VCPU;
33 // this def for vcpu_regs won't work if kernel stack is present
34 #define vcpu_regs(vcpu) ((struct pt_regs *) vcpu->arch.regs)
35 #define PSCB(x,y) VCPU(x,y)
36 #define PSCBX(x,y) x->arch.y
38 #define TRUE 1
39 #define FALSE 0
40 #define IA64_PTA_SZ_BIT 2
41 #define IA64_PTA_VF_BIT 8
42 #define IA64_PTA_BASE_BIT 15
43 #define IA64_PTA_LFMT (1UL << IA64_PTA_VF_BIT)
44 #define IA64_PTA_SZ(x) (x##UL << IA64_PTA_SZ_BIT)
46 #define STATIC
48 #ifdef PRIVOP_ADDR_COUNT
49 struct privop_addr_count privop_addr_counter[PRIVOP_COUNT_NINSTS] = {
50 { "=ifa", { 0 }, { 0 }, 0 },
51 { "thash", { 0 }, { 0 }, 0 },
52 0
53 };
54 extern void privop_count_addr(unsigned long addr, int inst);
55 #define PRIVOP_COUNT_ADDR(regs,inst) privop_count_addr(regs->cr_iip,inst)
56 #else
57 #define PRIVOP_COUNT_ADDR(x,y) do {} while (0)
58 #endif
60 unsigned long dtlb_translate_count = 0;
61 unsigned long tr_translate_count = 0;
62 unsigned long phys_translate_count = 0;
64 unsigned long vcpu_verbose = 0;
65 #define verbose(a...) do {if (vcpu_verbose) printf(a);} while(0)
67 extern TR_ENTRY *match_tr(VCPU *vcpu, unsigned long ifa);
68 extern TR_ENTRY *match_dtlb(VCPU *vcpu, unsigned long ifa);
70 /**************************************************************************
71 VCPU general register access routines
72 **************************************************************************/
74 UINT64
75 vcpu_get_gr(VCPU *vcpu, unsigned reg)
76 {
77 REGS *regs = vcpu_regs(vcpu);
78 UINT64 val;
80 if (!reg) return 0;
81 getreg(reg,&val,0,regs); // FIXME: handle NATs later
82 return val;
83 }
85 // returns:
86 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
87 // IA64_NO_FAULT otherwise
88 IA64FAULT
89 vcpu_set_gr(VCPU *vcpu, unsigned reg, UINT64 value)
90 {
91 REGS *regs = vcpu_regs(vcpu);
92 long sof = (regs->cr_ifs) & 0x7f;
94 if (!reg) return IA64_ILLOP_FAULT;
95 if (reg >= sof + 32) return IA64_ILLOP_FAULT;
96 setreg(reg,value,0,regs); // FIXME: handle NATs later
97 return IA64_NO_FAULT;
98 }
100 /**************************************************************************
101 VCPU privileged application register access routines
102 **************************************************************************/
104 IA64FAULT vcpu_set_ar(VCPU *vcpu, UINT64 reg, UINT64 val)
105 {
106 if (reg == 44) return (vcpu_set_itc(vcpu,val));
107 else if (reg == 27) return (IA64_ILLOP_FAULT);
108 else if (reg == 24)
109 printf("warning: setting ar.eflg is a no-op; no IA-32 support\n");
110 else if (reg > 7) return (IA64_ILLOP_FAULT);
111 else PSCB(vcpu,krs[reg]) = val;
112 return IA64_NO_FAULT;
113 }
115 IA64FAULT vcpu_get_ar(VCPU *vcpu, UINT64 reg, UINT64 *val)
116 {
117 if (reg == 24)
118 printf("warning: getting ar.eflg is a no-op; no IA-32 support\n");
119 else if (reg > 7) return (IA64_ILLOP_FAULT);
120 else *val = PSCB(vcpu,krs[reg]);
121 return IA64_NO_FAULT;
122 }
124 /**************************************************************************
125 VCPU processor status register access routines
126 **************************************************************************/
128 void vcpu_set_metaphysical_mode(VCPU *vcpu, BOOLEAN newmode)
129 {
130 /* only do something if mode changes */
131 if (!!newmode ^ !!PSCB(vcpu,metaphysical_mode)) {
132 if (newmode) set_metaphysical_rr0();
133 else if (PSCB(vcpu,rrs[0]) != -1)
134 set_one_rr(0, PSCB(vcpu,rrs[0]));
135 PSCB(vcpu,metaphysical_mode) = newmode;
136 }
137 }
139 IA64FAULT vcpu_reset_psr_dt(VCPU *vcpu)
140 {
141 vcpu_set_metaphysical_mode(vcpu,TRUE);
142 return IA64_NO_FAULT;
143 }
145 IA64FAULT vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm24)
146 {
147 struct ia64_psr psr, imm, *ipsr;
148 REGS *regs = vcpu_regs(vcpu);
150 //PRIVOP_COUNT_ADDR(regs,_RSM);
151 // TODO: All of these bits need to be virtualized
152 // TODO: Only allowed for current vcpu
153 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
154 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
155 imm = *(struct ia64_psr *)&imm24;
156 // interrupt flag
157 if (imm.i) PSCB(vcpu,interrupt_delivery_enabled) = 0;
158 if (imm.ic) PSCB(vcpu,interrupt_collection_enabled) = 0;
159 // interrupt collection flag
160 //if (imm.ic) PSCB(vcpu,interrupt_delivery_enabled) = 0;
161 // just handle psr.up and psr.pp for now
162 if (imm24 & ~(IA64_PSR_BE | IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP
163 | IA64_PSR_I | IA64_PSR_IC | IA64_PSR_DT
164 | IA64_PSR_DFL | IA64_PSR_DFH))
165 return (IA64_ILLOP_FAULT);
166 if (imm.dfh) ipsr->dfh = 0;
167 if (imm.dfl) ipsr->dfl = 0;
168 if (imm.pp) { ipsr->pp = 0; psr.pp = 0; }
169 if (imm.up) { ipsr->up = 0; psr.up = 0; }
170 if (imm.sp) { ipsr->sp = 0; psr.sp = 0; }
171 if (imm.be) ipsr->be = 0;
172 if (imm.dt) vcpu_set_metaphysical_mode(vcpu,TRUE);
173 __asm__ __volatile (";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
174 return IA64_NO_FAULT;
175 }
177 extern UINT64 vcpu_check_pending_interrupts(VCPU *vcpu);
178 #define SPURIOUS_VECTOR 0xf
180 IA64FAULT vcpu_set_psr_dt(VCPU *vcpu)
181 {
182 vcpu_set_metaphysical_mode(vcpu,FALSE);
183 return IA64_NO_FAULT;
184 }
186 IA64FAULT vcpu_set_psr_i(VCPU *vcpu)
187 {
188 PSCB(vcpu,interrupt_delivery_enabled) = 1;
189 PSCB(vcpu,interrupt_collection_enabled) = 1;
190 return IA64_NO_FAULT;
191 }
193 IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24)
194 {
195 struct ia64_psr psr, imm, *ipsr;
196 REGS *regs = vcpu_regs(vcpu);
197 UINT64 mask, enabling_interrupts = 0;
199 //PRIVOP_COUNT_ADDR(regs,_SSM);
200 // TODO: All of these bits need to be virtualized
201 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
202 imm = *(struct ia64_psr *)&imm24;
203 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
204 // just handle psr.sp,pp and psr.i,ic (and user mask) for now
205 mask = IA64_PSR_PP|IA64_PSR_SP|IA64_PSR_I|IA64_PSR_IC|IA64_PSR_UM |
206 IA64_PSR_DT|IA64_PSR_DFL|IA64_PSR_DFH;
207 if (imm24 & ~mask) return (IA64_ILLOP_FAULT);
208 if (imm.dfh) ipsr->dfh = 1;
209 if (imm.dfl) ipsr->dfl = 1;
210 if (imm.pp) { ipsr->pp = 1; psr.pp = 1; }
211 if (imm.sp) { ipsr->sp = 1; psr.sp = 1; }
212 if (imm.i) {
213 if (!PSCB(vcpu,interrupt_delivery_enabled)) {
214 //printf("vcpu_set_psr_sm: psr.ic 0->1 ");
215 enabling_interrupts = 1;
216 }
217 PSCB(vcpu,interrupt_delivery_enabled) = 1;
218 }
219 if (imm.ic) PSCB(vcpu,interrupt_collection_enabled) = 1;
220 // TODO: do this faster
221 if (imm.mfl) { ipsr->mfl = 1; psr.mfl = 1; }
222 if (imm.mfh) { ipsr->mfh = 1; psr.mfh = 1; }
223 if (imm.ac) { ipsr->ac = 1; psr.ac = 1; }
224 if (imm.up) { ipsr->up = 1; psr.up = 1; }
225 if (imm.be) {
226 printf("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
227 return (IA64_ILLOP_FAULT);
228 }
229 if (imm.dt) vcpu_set_metaphysical_mode(vcpu,FALSE);
230 __asm__ __volatile (";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
231 #if 0 // now done with deliver_pending_interrupts
232 if (enabling_interrupts) {
233 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR) {
234 //printf("with interrupts pending\n");
235 return IA64_EXTINT_VECTOR;
236 }
237 //else printf("but nothing pending\n");
238 }
239 #endif
240 if (enabling_interrupts &&
241 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
242 PSCB(vcpu,pending_interruption) = 1;
243 return IA64_NO_FAULT;
244 }
246 IA64FAULT vcpu_set_psr_l(VCPU *vcpu, UINT64 val)
247 {
248 struct ia64_psr psr, newpsr, *ipsr;
249 REGS *regs = vcpu_regs(vcpu);
250 UINT64 enabling_interrupts = 0;
252 // TODO: All of these bits need to be virtualized
253 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
254 newpsr = *(struct ia64_psr *)&val;
255 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
256 // just handle psr.up and psr.pp for now
257 //if (val & ~(IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP)) return (IA64_ILLOP_FAULT);
258 // however trying to set other bits can't be an error as it is in ssm
259 if (newpsr.dfh) ipsr->dfh = 1;
260 if (newpsr.dfl) ipsr->dfl = 1;
261 if (newpsr.pp) { ipsr->pp = 1; psr.pp = 1; }
262 if (newpsr.up) { ipsr->up = 1; psr.up = 1; }
263 if (newpsr.sp) { ipsr->sp = 1; psr.sp = 1; }
264 if (newpsr.i) {
265 if (!PSCB(vcpu,interrupt_delivery_enabled))
266 enabling_interrupts = 1;
267 PSCB(vcpu,interrupt_delivery_enabled) = 1;
268 }
269 if (newpsr.ic) PSCB(vcpu,interrupt_collection_enabled) = 1;
270 if (newpsr.mfl) { ipsr->mfl = 1; psr.mfl = 1; }
271 if (newpsr.mfh) { ipsr->mfh = 1; psr.mfh = 1; }
272 if (newpsr.ac) { ipsr->ac = 1; psr.ac = 1; }
273 if (newpsr.up) { ipsr->up = 1; psr.up = 1; }
274 if (newpsr.dt && newpsr.rt) vcpu_set_metaphysical_mode(vcpu,FALSE);
275 else vcpu_set_metaphysical_mode(vcpu,TRUE);
276 if (newpsr.be) {
277 printf("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
278 return (IA64_ILLOP_FAULT);
279 }
280 //__asm__ __volatile (";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
281 #if 0 // now done with deliver_pending_interrupts
282 if (enabling_interrupts) {
283 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
284 return IA64_EXTINT_VECTOR;
285 }
286 #endif
287 if (enabling_interrupts &&
288 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
289 PSCB(vcpu,pending_interruption) = 1;
290 return IA64_NO_FAULT;
291 }
293 IA64FAULT vcpu_get_psr(VCPU *vcpu, UINT64 *pval)
294 {
295 UINT64 psr;
296 struct ia64_psr newpsr;
298 // TODO: This needs to return a "filtered" view of
299 // the psr, not the actual psr. Probably the psr needs
300 // to be a field in regs (in addition to ipsr).
301 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
302 newpsr = *(struct ia64_psr *)&psr;
303 if (newpsr.cpl == 2) newpsr.cpl = 0;
304 if (PSCB(vcpu,interrupt_delivery_enabled)) newpsr.i = 1;
305 else newpsr.i = 0;
306 if (PSCB(vcpu,interrupt_collection_enabled)) newpsr.ic = 1;
307 else newpsr.ic = 0;
308 *pval = *(unsigned long *)&newpsr;
309 return IA64_NO_FAULT;
310 }
312 BOOLEAN vcpu_get_psr_ic(VCPU *vcpu)
313 {
314 return !!PSCB(vcpu,interrupt_collection_enabled);
315 }
317 BOOLEAN vcpu_get_psr_i(VCPU *vcpu)
318 {
319 return !!PSCB(vcpu,interrupt_delivery_enabled);
320 }
322 UINT64 vcpu_get_ipsr_int_state(VCPU *vcpu,UINT64 prevpsr)
323 {
324 UINT64 dcr = PSCBX(vcpu,dcr);
325 PSR psr = {0};
327 //printf("*** vcpu_get_ipsr_int_state (0x%016lx)...",prevpsr);
328 psr.i64 = prevpsr;
329 psr.ia64_psr.be = 0; if (dcr & IA64_DCR_BE) psr.ia64_psr.be = 1;
330 psr.ia64_psr.pp = 0; if (dcr & IA64_DCR_PP) psr.ia64_psr.pp = 1;
331 psr.ia64_psr.ic = PSCB(vcpu,interrupt_collection_enabled);
332 psr.ia64_psr.i = PSCB(vcpu,interrupt_delivery_enabled);
333 psr.ia64_psr.bn = PSCB(vcpu,banknum);
334 psr.ia64_psr.dt = 1; psr.ia64_psr.it = 1; psr.ia64_psr.rt = 1;
335 if (psr.ia64_psr.cpl == 2) psr.ia64_psr.cpl = 0; // !!!! fool domain
336 // psr.pk = 1;
337 //printf("returns 0x%016lx...",psr.i64);
338 return psr.i64;
339 }
341 /**************************************************************************
342 VCPU control register access routines
343 **************************************************************************/
345 IA64FAULT vcpu_get_dcr(VCPU *vcpu, UINT64 *pval)
346 {
347 extern unsigned long privop_trace;
348 //privop_trace=0;
349 //verbose("vcpu_get_dcr: called @%p\n",PSCB(vcpu,iip));
350 // Reads of cr.dcr on Xen always have the sign bit set, so
351 // a domain can differentiate whether it is running on SP or not
352 *pval = PSCBX(vcpu,dcr) | 0x8000000000000000L;
353 return (IA64_NO_FAULT);
354 }
356 IA64FAULT vcpu_get_iva(VCPU *vcpu, UINT64 *pval)
357 {
358 *pval = PSCBX(vcpu,iva) & ~0x7fffL;
359 return (IA64_NO_FAULT);
360 }
362 IA64FAULT vcpu_get_pta(VCPU *vcpu, UINT64 *pval)
363 {
364 *pval = PSCB(vcpu,pta);
365 return (IA64_NO_FAULT);
366 }
368 IA64FAULT vcpu_get_ipsr(VCPU *vcpu, UINT64 *pval)
369 {
370 //REGS *regs = vcpu_regs(vcpu);
371 //*pval = regs->cr_ipsr;
372 *pval = PSCB(vcpu,ipsr);
373 return (IA64_NO_FAULT);
374 }
376 IA64FAULT vcpu_get_isr(VCPU *vcpu, UINT64 *pval)
377 {
378 *pval = PSCB(vcpu,isr);
379 return (IA64_NO_FAULT);
380 }
382 IA64FAULT vcpu_get_iip(VCPU *vcpu, UINT64 *pval)
383 {
384 //REGS *regs = vcpu_regs(vcpu);
385 //*pval = regs->cr_iip;
386 *pval = PSCB(vcpu,iip);
387 return (IA64_NO_FAULT);
388 }
390 IA64FAULT vcpu_get_ifa(VCPU *vcpu, UINT64 *pval)
391 {
392 UINT64 val = PSCB(vcpu,ifa);
393 REGS *regs = vcpu_regs(vcpu);
394 PRIVOP_COUNT_ADDR(regs,_GET_IFA);
395 *pval = val;
396 return (IA64_NO_FAULT);
397 }
399 unsigned long vcpu_get_rr_ps(VCPU *vcpu,UINT64 vadr)
400 {
401 ia64_rr rr;
403 rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
404 return(rr.ps);
405 }
407 unsigned long vcpu_get_rr_rid(VCPU *vcpu,UINT64 vadr)
408 {
409 ia64_rr rr;
411 rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
412 return(rr.rid);
413 }
415 unsigned long vcpu_get_itir_on_fault(VCPU *vcpu, UINT64 ifa)
416 {
417 ia64_rr rr;
419 rr.rrval = 0;
420 rr.ps = vcpu_get_rr_ps(vcpu,ifa);
421 rr.rid = vcpu_get_rr_rid(vcpu,ifa);
422 return (rr.rrval);
423 }
426 IA64FAULT vcpu_get_itir(VCPU *vcpu, UINT64 *pval)
427 {
428 UINT64 val = PSCB(vcpu,itir);
429 *pval = val;
430 return (IA64_NO_FAULT);
431 }
433 IA64FAULT vcpu_get_iipa(VCPU *vcpu, UINT64 *pval)
434 {
435 UINT64 val = PSCB(vcpu,iipa);
436 // SP entry code does not save iipa yet nor does it get
437 // properly delivered in the pscb
438 printf("*** vcpu_get_iipa: cr.iipa not fully implemented yet!!\n");
439 *pval = val;
440 return (IA64_NO_FAULT);
441 }
443 IA64FAULT vcpu_get_ifs(VCPU *vcpu, UINT64 *pval)
444 {
445 //PSCB(vcpu,ifs) = PSCB(vcpu)->regs.cr_ifs;
446 //*pval = PSCB(vcpu,regs).cr_ifs;
447 *pval = PSCB(vcpu,ifs);
448 PSCB(vcpu,incomplete_regframe) = 0;
449 return (IA64_NO_FAULT);
450 }
452 IA64FAULT vcpu_get_iim(VCPU *vcpu, UINT64 *pval)
453 {
454 UINT64 val = PSCB(vcpu,iim);
455 *pval = val;
456 return (IA64_NO_FAULT);
457 }
459 IA64FAULT vcpu_get_iha(VCPU *vcpu, UINT64 *pval)
460 {
461 //return vcpu_thash(vcpu,PSCB(vcpu,ifa),pval);
462 UINT64 val = PSCB(vcpu,iha);
463 REGS *regs = vcpu_regs(vcpu);
464 PRIVOP_COUNT_ADDR(regs,_THASH);
465 *pval = val;
466 return (IA64_NO_FAULT);
467 }
469 IA64FAULT vcpu_set_dcr(VCPU *vcpu, UINT64 val)
470 {
471 extern unsigned long privop_trace;
472 //privop_trace=1;
473 // Reads of cr.dcr on SP always have the sign bit set, so
474 // a domain can differentiate whether it is running on SP or not
475 // Thus, writes of DCR should ignore the sign bit
476 //verbose("vcpu_set_dcr: called\n");
477 PSCBX(vcpu,dcr) = val & ~0x8000000000000000L;
478 return (IA64_NO_FAULT);
479 }
481 IA64FAULT vcpu_set_iva(VCPU *vcpu, UINT64 val)
482 {
483 PSCBX(vcpu,iva) = val & ~0x7fffL;
484 return (IA64_NO_FAULT);
485 }
487 IA64FAULT vcpu_set_pta(VCPU *vcpu, UINT64 val)
488 {
489 if (val & IA64_PTA_LFMT) {
490 printf("*** No support for VHPT long format yet!!\n");
491 return (IA64_ILLOP_FAULT);
492 }
493 if (val & (0x3f<<9)) /* reserved fields */ return IA64_RSVDREG_FAULT;
494 if (val & 2) /* reserved fields */ return IA64_RSVDREG_FAULT;
495 PSCB(vcpu,pta) = val;
496 return IA64_NO_FAULT;
497 }
499 IA64FAULT vcpu_set_ipsr(VCPU *vcpu, UINT64 val)
500 {
501 PSCB(vcpu,ipsr) = val;
502 return IA64_NO_FAULT;
503 }
505 IA64FAULT vcpu_set_isr(VCPU *vcpu, UINT64 val)
506 {
507 PSCB(vcpu,isr) = val;
508 return IA64_NO_FAULT;
509 }
511 IA64FAULT vcpu_set_iip(VCPU *vcpu, UINT64 val)
512 {
513 PSCB(vcpu,iip) = val;
514 return IA64_NO_FAULT;
515 }
517 IA64FAULT vcpu_increment_iip(VCPU *vcpu)
518 {
519 REGS *regs = vcpu_regs(vcpu);
520 struct ia64_psr *ipsr = (struct ia64_psr *)&regs->cr_ipsr;
521 if (ipsr->ri == 2) { ipsr->ri=0; regs->cr_iip += 16; }
522 else ipsr->ri++;
523 return (IA64_NO_FAULT);
524 }
526 IA64FAULT vcpu_set_ifa(VCPU *vcpu, UINT64 val)
527 {
528 PSCB(vcpu,ifa) = val;
529 return IA64_NO_FAULT;
530 }
532 IA64FAULT vcpu_set_itir(VCPU *vcpu, UINT64 val)
533 {
534 PSCB(vcpu,itir) = val;
535 return IA64_NO_FAULT;
536 }
538 IA64FAULT vcpu_set_iipa(VCPU *vcpu, UINT64 val)
539 {
540 // SP entry code does not save iipa yet nor does it get
541 // properly delivered in the pscb
542 printf("*** vcpu_set_iipa: cr.iipa not fully implemented yet!!\n");
543 PSCB(vcpu,iipa) = val;
544 return IA64_NO_FAULT;
545 }
547 IA64FAULT vcpu_set_ifs(VCPU *vcpu, UINT64 val)
548 {
549 //REGS *regs = vcpu_regs(vcpu);
550 PSCB(vcpu,ifs) = val;
551 return IA64_NO_FAULT;
552 }
554 IA64FAULT vcpu_set_iim(VCPU *vcpu, UINT64 val)
555 {
556 PSCB(vcpu,iim) = val;
557 return IA64_NO_FAULT;
558 }
560 IA64FAULT vcpu_set_iha(VCPU *vcpu, UINT64 val)
561 {
562 PSCB(vcpu,iha) = val;
563 return IA64_NO_FAULT;
564 }
566 /**************************************************************************
567 VCPU interrupt control register access routines
568 **************************************************************************/
570 void vcpu_pend_unspecified_interrupt(VCPU *vcpu)
571 {
572 PSCB(vcpu,pending_interruption) = 1;
573 }
575 void vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector)
576 {
577 if (vector & ~0xff) {
578 printf("vcpu_pend_interrupt: bad vector\n");
579 return;
580 }
581 #ifdef CONFIG_VTI
582 if ( VMX_DOMAIN(vcpu) ) {
583 set_bit(vector,VPD_CR(vcpu,irr));
584 } else
585 #endif // CONFIG_VTI
586 {
587 /* if (!test_bit(vector,PSCB(vcpu,delivery_mask))) return; */
588 if (test_bit(vector,PSCBX(vcpu,irr))) {
589 //printf("vcpu_pend_interrupt: overrun\n");
590 }
591 set_bit(vector,PSCBX(vcpu,irr));
592 PSCB(vcpu,pending_interruption) = 1;
593 }
595 #if 0
596 /* Keir: I think you should unblock when an interrupt is pending. */
597 {
598 int running = test_bit(_VCPUF_running, &vcpu->vcpu_flags);
599 vcpu_unblock(vcpu);
600 if ( running )
601 smp_send_event_check_cpu(vcpu->processor);
602 }
603 #endif
604 }
606 void early_tick(VCPU *vcpu)
607 {
608 UINT64 *p = &PSCBX(vcpu,irr[3]);
609 printf("vcpu_check_pending: about to deliver early tick\n");
610 printf("&irr[0]=%p, irr[0]=0x%lx\n",p,*p);
611 }
613 #define IA64_TPR_MMI 0x10000
614 #define IA64_TPR_MIC 0x000f0
616 /* checks to see if a VCPU has any unmasked pending interrupts
617 * if so, returns the highest, else returns SPURIOUS_VECTOR */
618 /* NOTE: Since this gets called from vcpu_get_ivr() and the
619 * semantics of "mov rx=cr.ivr" ignore the setting of the psr.i bit,
620 * this routine also ignores pscb.interrupt_delivery_enabled
621 * and this must be checked independently; see vcpu_deliverable interrupts() */
622 UINT64 vcpu_check_pending_interrupts(VCPU *vcpu)
623 {
624 UINT64 *p, *q, *r, bits, bitnum, mask, i, vector;
626 p = &PSCBX(vcpu,irr[3]);
627 /* q = &PSCB(vcpu,delivery_mask[3]); */
628 r = &PSCBX(vcpu,insvc[3]);
629 for (i = 3; ; p--, q--, r--, i--) {
630 bits = *p /* & *q */;
631 if (bits) break; // got a potential interrupt
632 if (*r) {
633 // nothing in this word which is pending+inservice
634 // but there is one inservice which masks lower
635 return SPURIOUS_VECTOR;
636 }
637 if (i == 0) {
638 // checked all bits... nothing pending+inservice
639 return SPURIOUS_VECTOR;
640 }
641 }
642 // have a pending,deliverable interrupt... see if it is masked
643 bitnum = ia64_fls(bits);
644 //printf("XXXXXXX vcpu_check_pending_interrupts: got bitnum=%p...",bitnum);
645 vector = bitnum+(i*64);
646 mask = 1L << bitnum;
647 //printf("XXXXXXX vcpu_check_pending_interrupts: got vector=%p...",vector);
648 if (*r >= mask) {
649 // masked by equal inservice
650 //printf("but masked by equal inservice\n");
651 return SPURIOUS_VECTOR;
652 }
653 if (PSCB(vcpu,tpr) & IA64_TPR_MMI) {
654 // tpr.mmi is set
655 //printf("but masked by tpr.mmi\n");
656 return SPURIOUS_VECTOR;
657 }
658 if (((PSCB(vcpu,tpr) & IA64_TPR_MIC) + 15) >= vector) {
659 //tpr.mic masks class
660 //printf("but masked by tpr.mic\n");
661 return SPURIOUS_VECTOR;
662 }
664 //printf("returned to caller\n");
665 #if 0
666 if (vector == (PSCB(vcpu,itv) & 0xff)) {
667 UINT64 now = ia64_get_itc();
668 UINT64 itm = PSCBX(vcpu,domain_itm);
669 if (now < itm) early_tick(vcpu);
671 }
672 #endif
673 return vector;
674 }
676 UINT64 vcpu_deliverable_interrupts(VCPU *vcpu)
677 {
678 return (vcpu_get_psr_i(vcpu) &&
679 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR);
680 }
682 UINT64 vcpu_deliverable_timer(VCPU *vcpu)
683 {
684 return (vcpu_get_psr_i(vcpu) &&
685 vcpu_check_pending_interrupts(vcpu) == PSCB(vcpu,itv));
686 }
688 IA64FAULT vcpu_get_lid(VCPU *vcpu, UINT64 *pval)
689 {
690 extern unsigned long privop_trace;
691 //privop_trace=1;
692 //TODO: Implement this
693 printf("vcpu_get_lid: WARNING: Getting cr.lid always returns zero\n");
694 //*pval = 0;
695 *pval = ia64_getreg(_IA64_REG_CR_LID);
696 return IA64_NO_FAULT;
697 }
699 IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT64 *pval)
700 {
701 int i;
702 UINT64 vector, mask;
704 #define HEARTBEAT_FREQ 16 // period in seconds
705 #ifdef HEARTBEAT_FREQ
706 #define N_DOMS 16 // period in seconds
707 static long count[N_DOMS] = { 0 };
708 static long nonclockcount[N_DOMS] = { 0 };
709 REGS *regs = vcpu_regs(vcpu);
710 unsigned domid = vcpu->domain->domain_id;
711 #endif
712 #ifdef IRQ_DEBUG
713 static char firstivr = 1;
714 static char firsttime[256];
715 if (firstivr) {
716 int i;
717 for (i=0;i<256;i++) firsttime[i]=1;
718 firstivr=0;
719 }
720 #endif
722 vector = vcpu_check_pending_interrupts(vcpu);
723 if (vector == SPURIOUS_VECTOR) {
724 PSCB(vcpu,pending_interruption) = 0;
725 *pval = vector;
726 return IA64_NO_FAULT;
727 }
728 #ifdef HEARTBEAT_FREQ
729 if (domid >= N_DOMS) domid = N_DOMS-1;
730 if (vector == (PSCB(vcpu,itv) & 0xff)) {
731 if (!(++count[domid] & ((HEARTBEAT_FREQ*1024)-1))) {
732 printf("Dom%d heartbeat... ticks=%lx,nonticks=%lx\n",
733 domid, count[domid], nonclockcount[domid]);
734 //count[domid] = 0;
735 //dump_runq();
736 }
737 }
738 else nonclockcount[domid]++;
739 #endif
740 // now have an unmasked, pending, deliverable vector!
741 // getting ivr has "side effects"
742 #ifdef IRQ_DEBUG
743 if (firsttime[vector]) {
744 printf("*** First get_ivr on vector=%d,itc=%lx\n",
745 vector,ia64_get_itc());
746 firsttime[vector]=0;
747 }
748 #endif
749 i = vector >> 6;
750 mask = 1L << (vector & 0x3f);
751 //printf("ZZZZZZ vcpu_get_ivr: setting insvc mask for vector %ld\n",vector);
752 PSCBX(vcpu,insvc[i]) |= mask;
753 PSCBX(vcpu,irr[i]) &= ~mask;
754 //PSCB(vcpu,pending_interruption)--;
755 *pval = vector;
756 // if delivering a timer interrupt, remember domain_itm
757 if (vector == (PSCB(vcpu,itv) & 0xff)) {
758 PSCBX(vcpu,domain_itm_last) = PSCBX(vcpu,domain_itm);
759 }
760 return IA64_NO_FAULT;
761 }
763 IA64FAULT vcpu_get_tpr(VCPU *vcpu, UINT64 *pval)
764 {
765 *pval = PSCB(vcpu,tpr);
766 return (IA64_NO_FAULT);
767 }
769 IA64FAULT vcpu_get_eoi(VCPU *vcpu, UINT64 *pval)
770 {
771 *pval = 0L; // reads of eoi always return 0
772 return (IA64_NO_FAULT);
773 }
775 IA64FAULT vcpu_get_irr0(VCPU *vcpu, UINT64 *pval)
776 {
777 #ifndef IRR_USE_FIXED
778 printk("vcpu_get_irr: called, not implemented yet\n");
779 return IA64_ILLOP_FAULT;
780 #else
781 *pval = vcpu->irr[0];
782 return (IA64_NO_FAULT);
783 #endif
784 }
786 IA64FAULT vcpu_get_irr1(VCPU *vcpu, UINT64 *pval)
787 {
788 #ifndef IRR_USE_FIXED
789 printk("vcpu_get_irr: called, not implemented yet\n");
790 return IA64_ILLOP_FAULT;
791 #else
792 *pval = vcpu->irr[1];
793 return (IA64_NO_FAULT);
794 #endif
795 }
797 IA64FAULT vcpu_get_irr2(VCPU *vcpu, UINT64 *pval)
798 {
799 #ifndef IRR_USE_FIXED
800 printk("vcpu_get_irr: called, not implemented yet\n");
801 return IA64_ILLOP_FAULT;
802 #else
803 *pval = vcpu->irr[2];
804 return (IA64_NO_FAULT);
805 #endif
806 }
808 IA64FAULT vcpu_get_irr3(VCPU *vcpu, UINT64 *pval)
809 {
810 #ifndef IRR_USE_FIXED
811 printk("vcpu_get_irr: called, not implemented yet\n");
812 return IA64_ILLOP_FAULT;
813 #else
814 *pval = vcpu->irr[3];
815 return (IA64_NO_FAULT);
816 #endif
817 }
819 IA64FAULT vcpu_get_itv(VCPU *vcpu, UINT64 *pval)
820 {
821 *pval = PSCB(vcpu,itv);
822 return (IA64_NO_FAULT);
823 }
825 IA64FAULT vcpu_get_pmv(VCPU *vcpu, UINT64 *pval)
826 {
827 *pval = PSCB(vcpu,pmv);
828 return (IA64_NO_FAULT);
829 }
831 IA64FAULT vcpu_get_cmcv(VCPU *vcpu, UINT64 *pval)
832 {
833 *pval = PSCB(vcpu,cmcv);
834 return (IA64_NO_FAULT);
835 }
837 IA64FAULT vcpu_get_lrr0(VCPU *vcpu, UINT64 *pval)
838 {
839 // fix this when setting values other than m-bit is supported
840 printf("vcpu_get_lrr0: Unmasked interrupts unsupported\n");
841 *pval = (1L << 16);
842 return (IA64_NO_FAULT);
843 }
845 IA64FAULT vcpu_get_lrr1(VCPU *vcpu, UINT64 *pval)
846 {
847 // fix this when setting values other than m-bit is supported
848 printf("vcpu_get_lrr1: Unmasked interrupts unsupported\n");
849 *pval = (1L << 16);
850 return (IA64_NO_FAULT);
851 }
853 IA64FAULT vcpu_set_lid(VCPU *vcpu, UINT64 val)
854 {
855 printf("vcpu_set_lid: Setting cr.lid is unsupported\n");
856 return (IA64_ILLOP_FAULT);
857 }
859 IA64FAULT vcpu_set_tpr(VCPU *vcpu, UINT64 val)
860 {
861 if (val & 0xff00) return IA64_RSVDREG_FAULT;
862 PSCB(vcpu,tpr) = val;
863 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
864 PSCB(vcpu,pending_interruption) = 1;
865 return (IA64_NO_FAULT);
866 }
868 IA64FAULT vcpu_set_eoi(VCPU *vcpu, UINT64 val)
869 {
870 UINT64 *p, bits, vec, bitnum;
871 int i;
873 p = &PSCBX(vcpu,insvc[3]);
874 for (i = 3; (i >= 0) && !(bits = *p); i--, p--);
875 if (i < 0) {
876 printf("Trying to EOI interrupt when none are in-service.\r\n");
877 return;
878 }
879 bitnum = ia64_fls(bits);
880 vec = bitnum + (i*64);
881 /* clear the correct bit */
882 bits &= ~(1L << bitnum);
883 *p = bits;
884 /* clearing an eoi bit may unmask another pending interrupt... */
885 if (PSCB(vcpu,interrupt_delivery_enabled)) { // but only if enabled...
886 // worry about this later... Linux only calls eoi
887 // with interrupts disabled
888 printf("Trying to EOI interrupt with interrupts enabled\r\n");
889 }
890 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
891 PSCB(vcpu,pending_interruption) = 1;
892 //printf("YYYYY vcpu_set_eoi: Successful\n");
893 return (IA64_NO_FAULT);
894 }
896 IA64FAULT vcpu_set_lrr0(VCPU *vcpu, UINT64 val)
897 {
898 if (!(val & (1L << 16))) {
899 printf("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
900 return (IA64_ILLOP_FAULT);
901 }
902 // no place to save this state but nothing to do anyway
903 return (IA64_NO_FAULT);
904 }
906 IA64FAULT vcpu_set_lrr1(VCPU *vcpu, UINT64 val)
907 {
908 if (!(val & (1L << 16))) {
909 printf("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
910 return (IA64_ILLOP_FAULT);
911 }
912 // no place to save this state but nothing to do anyway
913 return (IA64_NO_FAULT);
914 }
916 // parameter is a time interval specified in cycles
917 void vcpu_enable_timer(VCPU *vcpu,UINT64 cycles)
918 {
919 PSCBX(vcpu,xen_timer_interval) = cycles;
920 vcpu_set_next_timer(vcpu);
921 printf("vcpu_enable_timer(%d): interval set to %d cycles\n",
922 PSCBX(vcpu,xen_timer_interval));
923 __set_bit(PSCB(vcpu,itv), PSCB(vcpu,delivery_mask));
924 }
926 IA64FAULT vcpu_set_itv(VCPU *vcpu, UINT64 val)
927 {
928 extern unsigned long privop_trace;
929 //privop_trace=1;
930 if (val & 0xef00) return (IA64_ILLOP_FAULT);
931 PSCB(vcpu,itv) = val;
932 if (val & 0x10000) {
933 printf("**** vcpu_set_itv(%d): vitm=%lx, setting to 0\n",val,PSCBX(vcpu,domain_itm));
934 PSCBX(vcpu,domain_itm) = 0;
935 }
936 else vcpu_enable_timer(vcpu,1000000L);
937 return (IA64_NO_FAULT);
938 }
940 IA64FAULT vcpu_set_pmv(VCPU *vcpu, UINT64 val)
941 {
942 if (val & 0xef00) /* reserved fields */ return IA64_RSVDREG_FAULT;
943 PSCB(vcpu,pmv) = val;
944 return (IA64_NO_FAULT);
945 }
947 IA64FAULT vcpu_set_cmcv(VCPU *vcpu, UINT64 val)
948 {
949 if (val & 0xef00) /* reserved fields */ return IA64_RSVDREG_FAULT;
950 PSCB(vcpu,cmcv) = val;
951 return (IA64_NO_FAULT);
952 }
954 /**************************************************************************
955 VCPU temporary register access routines
956 **************************************************************************/
957 UINT64 vcpu_get_tmp(VCPU *vcpu, UINT64 index)
958 {
959 if (index > 7) return 0;
960 return PSCB(vcpu,tmp[index]);
961 }
963 void vcpu_set_tmp(VCPU *vcpu, UINT64 index, UINT64 val)
964 {
965 if (index <= 7) PSCB(vcpu,tmp[index]) = val;
966 }
968 /**************************************************************************
969 Interval timer routines
970 **************************************************************************/
972 BOOLEAN vcpu_timer_disabled(VCPU *vcpu)
973 {
974 UINT64 itv = PSCB(vcpu,itv);
975 return(!itv || !!(itv & 0x10000));
976 }
978 BOOLEAN vcpu_timer_inservice(VCPU *vcpu)
979 {
980 UINT64 itv = PSCB(vcpu,itv);
981 return (test_bit(itv, PSCBX(vcpu,insvc)));
982 }
984 BOOLEAN vcpu_timer_expired(VCPU *vcpu)
985 {
986 unsigned long domain_itm = PSCBX(vcpu,domain_itm);
987 unsigned long now = ia64_get_itc();
989 if (!domain_itm) return FALSE;
990 if (now < domain_itm) return FALSE;
991 if (vcpu_timer_disabled(vcpu)) return FALSE;
992 return TRUE;
993 }
995 void vcpu_safe_set_itm(unsigned long val)
996 {
997 unsigned long epsilon = 100;
998 UINT64 now = ia64_get_itc();
1000 local_irq_disable();
1001 while (1) {
1002 //printf("*** vcpu_safe_set_itm: Setting itm to %lx, itc=%lx\n",val,now);
1003 ia64_set_itm(val);
1004 if (val > (now = ia64_get_itc())) break;
1005 val = now + epsilon;
1006 epsilon <<= 1;
1008 local_irq_enable();
1011 void vcpu_set_next_timer(VCPU *vcpu)
1013 UINT64 d = PSCBX(vcpu,domain_itm);
1014 //UINT64 s = PSCBX(vcpu,xen_itm);
1015 UINT64 s = local_cpu_data->itm_next;
1016 UINT64 now = ia64_get_itc();
1017 //UINT64 interval = PSCBX(vcpu,xen_timer_interval);
1019 /* gloss over the wraparound problem for now... we know it exists
1020 * but it doesn't matter right now */
1022 #if 0
1023 /* ensure at least next SP tick is in the future */
1024 if (!interval) PSCBX(vcpu,xen_itm) = now +
1025 #if 0
1026 (running_on_sim() ? SIM_DEFAULT_CLOCK_RATE :
1027 DEFAULT_CLOCK_RATE);
1028 #else
1029 3000000;
1030 //printf("vcpu_set_next_timer: HACK!\n");
1031 #endif
1032 #if 0
1033 if (PSCBX(vcpu,xen_itm) < now)
1034 while (PSCBX(vcpu,xen_itm) < now + (interval>>1))
1035 PSCBX(vcpu,xen_itm) += interval;
1036 #endif
1037 #endif
1039 if (is_idle_task(vcpu->domain)) {
1040 printf("****** vcpu_set_next_timer called during idle!!\n");
1041 vcpu_safe_set_itm(s);
1042 return;
1044 //s = PSCBX(vcpu,xen_itm);
1045 if (d && (d > now) && (d < s)) {
1046 vcpu_safe_set_itm(d);
1047 //using_domain_as_itm++;
1049 else {
1050 vcpu_safe_set_itm(s);
1051 //using_xen_as_itm++;
1055 IA64FAULT vcpu_set_itm(VCPU *vcpu, UINT64 val)
1057 UINT now = ia64_get_itc();
1059 //if (val < now) val = now + 1000;
1060 //printf("*** vcpu_set_itm: called with %lx\n",val);
1061 PSCBX(vcpu,domain_itm) = val;
1062 vcpu_set_next_timer(vcpu);
1063 return (IA64_NO_FAULT);
1066 IA64FAULT vcpu_set_itc(VCPU *vcpu, UINT64 val)
1069 UINT64 oldnow = ia64_get_itc();
1070 UINT64 olditm = PSCBX(vcpu,domain_itm);
1071 unsigned long d = olditm - oldnow;
1072 unsigned long x = local_cpu_data->itm_next - oldnow;
1074 UINT64 newnow = val, min_delta;
1076 #define DISALLOW_SETTING_ITC_FOR_NOW
1077 #ifdef DISALLOW_SETTING_ITC_FOR_NOW
1078 printf("vcpu_set_itc: Setting ar.itc is currently disabled\n");
1079 #else
1080 local_irq_disable();
1081 if (olditm) {
1082 printf("**** vcpu_set_itc(%lx): vitm changed to %lx\n",val,newnow+d);
1083 PSCBX(vcpu,domain_itm) = newnow + d;
1085 local_cpu_data->itm_next = newnow + x;
1086 d = PSCBX(vcpu,domain_itm);
1087 x = local_cpu_data->itm_next;
1089 ia64_set_itc(newnow);
1090 if (d && (d > newnow) && (d < x)) {
1091 vcpu_safe_set_itm(d);
1092 //using_domain_as_itm++;
1094 else {
1095 vcpu_safe_set_itm(x);
1096 //using_xen_as_itm++;
1098 local_irq_enable();
1099 #endif
1100 return (IA64_NO_FAULT);
1103 IA64FAULT vcpu_get_itm(VCPU *vcpu, UINT64 *pval)
1105 //FIXME: Implement this
1106 printf("vcpu_get_itm: Getting cr.itm is unsupported... continuing\n");
1107 return (IA64_NO_FAULT);
1108 //return (IA64_ILLOP_FAULT);
1111 IA64FAULT vcpu_get_itc(VCPU *vcpu, UINT64 *pval)
1113 //TODO: Implement this
1114 printf("vcpu_get_itc: Getting ar.itc is unsupported\n");
1115 return (IA64_ILLOP_FAULT);
1118 void vcpu_pend_timer(VCPU *vcpu)
1120 UINT64 itv = PSCB(vcpu,itv) & 0xff;
1122 if (vcpu_timer_disabled(vcpu)) return;
1123 //if (vcpu_timer_inservice(vcpu)) return;
1124 if (PSCBX(vcpu,domain_itm_last) == PSCBX(vcpu,domain_itm)) {
1125 // already delivered an interrupt for this so
1126 // don't deliver another
1127 return;
1129 #if 0
1130 // attempt to flag "timer tick before its due" source
1132 UINT64 itm = PSCBX(vcpu,domain_itm);
1133 UINT64 now = ia64_get_itc();
1134 if (now < itm) printf("******* vcpu_pend_timer: pending before due!\n");
1136 #endif
1137 vcpu_pend_interrupt(vcpu, itv);
1140 // returns true if ready to deliver a timer interrupt too early
1141 UINT64 vcpu_timer_pending_early(VCPU *vcpu)
1143 UINT64 now = ia64_get_itc();
1144 UINT64 itm = PSCBX(vcpu,domain_itm);
1146 if (vcpu_timer_disabled(vcpu)) return 0;
1147 if (!itm) return 0;
1148 return (vcpu_deliverable_timer(vcpu) && (now < itm));
1151 //FIXME: This is a hack because everything dies if a timer tick is lost
1152 void vcpu_poke_timer(VCPU *vcpu)
1154 UINT64 itv = PSCB(vcpu,itv) & 0xff;
1155 UINT64 now = ia64_get_itc();
1156 UINT64 itm = PSCBX(vcpu,domain_itm);
1157 UINT64 irr;
1159 if (vcpu_timer_disabled(vcpu)) return;
1160 if (!itm) return;
1161 if (itv != 0xefL) {
1162 printf("vcpu_poke_timer: unimplemented itv=%lx!\n",itv);
1163 while(1);
1165 // using 0xef instead of itv so can get real irr
1166 if (now > itm && !test_bit(0xefL, PSCBX(vcpu,insvc))) {
1167 if (!test_bit(0xefL,PSCBX(vcpu,irr))) {
1168 irr = ia64_getreg(_IA64_REG_CR_IRR3);
1169 if (irr & (1L<<(0xef-0xc0))) return;
1170 if (now-itm>0x800000)
1171 printf("*** poking timer: now=%lx,vitm=%lx,xitm=%lx,itm=%lx\n",now,itm,local_cpu_data->itm_next,ia64_get_itm());
1172 vcpu_pend_timer(vcpu);
1178 /**************************************************************************
1179 Privileged operation emulation routines
1180 **************************************************************************/
1182 IA64FAULT vcpu_force_data_miss(VCPU *vcpu, UINT64 ifa)
1184 PSCB(vcpu,tmp[0]) = ifa; // save ifa in vcpu structure, then specify IA64_FORCED_IFA
1185 return (vcpu_get_rr_ve(vcpu,ifa) ? IA64_DATA_TLB_VECTOR : IA64_ALT_DATA_TLB_VECTOR) | IA64_FORCED_IFA;
1189 IA64FAULT vcpu_rfi(VCPU *vcpu)
1191 // TODO: Only allowed for current vcpu
1192 PSR psr;
1193 UINT64 int_enable, regspsr = 0;
1194 UINT64 ifs;
1195 REGS *regs = vcpu_regs(vcpu);
1196 extern void dorfirfi(void);
1198 psr.i64 = PSCB(vcpu,ipsr);
1199 if (psr.ia64_psr.cpl < 3) psr.ia64_psr.cpl = 2;
1200 if (psr.ia64_psr.i) PSCB(vcpu,interrupt_delivery_enabled) = 1;
1201 int_enable = psr.ia64_psr.i;
1202 if (psr.ia64_psr.ic) PSCB(vcpu,interrupt_collection_enabled) = 1;
1203 if (psr.ia64_psr.dt && psr.ia64_psr.rt && psr.ia64_psr.it) vcpu_set_metaphysical_mode(vcpu,FALSE);
1204 else vcpu_set_metaphysical_mode(vcpu,TRUE);
1205 psr.ia64_psr.ic = 1; psr.ia64_psr.i = 1;
1206 psr.ia64_psr.dt = 1; psr.ia64_psr.rt = 1; psr.ia64_psr.it = 1;
1207 psr.ia64_psr.bn = 1;
1208 //psr.pk = 1; // checking pkeys shouldn't be a problem but seems broken
1209 if (psr.ia64_psr.be) {
1210 printf("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
1211 return (IA64_ILLOP_FAULT);
1213 PSCB(vcpu,incomplete_regframe) = 0; // is this necessary?
1214 ifs = PSCB(vcpu,ifs);
1215 //if ((ifs & regs->cr_ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
1216 //if ((ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
1217 if (ifs & regs->cr_ifs & 0x8000000000000000L) {
1218 // TODO: validate PSCB(vcpu,iip)
1219 // TODO: PSCB(vcpu,ipsr) = psr;
1220 PSCB(vcpu,ipsr) = psr.i64;
1221 // now set up the trampoline
1222 regs->cr_iip = *(unsigned long *)dorfirfi; // function pointer!!
1223 __asm__ __volatile ("mov %0=psr;;":"=r"(regspsr)::"memory");
1224 regs->cr_ipsr = regspsr & ~(IA64_PSR_I | IA64_PSR_IC | IA64_PSR_BN);
1226 else {
1227 regs->cr_ipsr = psr.i64;
1228 regs->cr_iip = PSCB(vcpu,iip);
1230 PSCB(vcpu,interrupt_collection_enabled) = 1;
1231 vcpu_bsw1(vcpu);
1232 PSCB(vcpu,interrupt_delivery_enabled) = int_enable;
1233 return (IA64_NO_FAULT);
1236 IA64FAULT vcpu_cover(VCPU *vcpu)
1238 // TODO: Only allowed for current vcpu
1239 REGS *regs = vcpu_regs(vcpu);
1241 if (!PSCB(vcpu,interrupt_collection_enabled)) {
1242 if (!PSCB(vcpu,incomplete_regframe))
1243 PSCB(vcpu,ifs) = regs->cr_ifs;
1244 else PSCB(vcpu,incomplete_regframe) = 0;
1246 regs->cr_ifs = 0;
1247 return (IA64_NO_FAULT);
1250 IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 vadr, UINT64 *pval)
1252 UINT64 pta = PSCB(vcpu,pta);
1253 UINT64 pta_sz = (pta & IA64_PTA_SZ(0x3f)) >> IA64_PTA_SZ_BIT;
1254 UINT64 pta_base = pta & ~((1UL << IA64_PTA_BASE_BIT)-1);
1255 UINT64 Mask = (1L << pta_sz) - 1;
1256 UINT64 Mask_60_15 = (Mask >> 15) & 0x3fffffffffff;
1257 UINT64 compMask_60_15 = ~Mask_60_15;
1258 //UINT64 rr_ps = RR_TO_PS(get_rr(vadr));
1259 UINT64 rr_ps = vcpu_get_rr_ps(vcpu,vadr);
1260 UINT64 VHPT_offset = (vadr >> rr_ps) << 3;
1261 UINT64 VHPT_addr1 = vadr & 0xe000000000000000L;
1262 UINT64 VHPT_addr2a =
1263 ((pta_base >> 15) & 0x3fffffffffff) & compMask_60_15;
1264 UINT64 VHPT_addr2b =
1265 ((VHPT_offset >> 15) & 0x3fffffffffff) & Mask_60_15;;
1266 UINT64 VHPT_addr3 = VHPT_offset & 0x7fff;
1267 UINT64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
1268 VHPT_addr3;
1270 #if 0
1271 if (VHPT_addr1 == 0xe000000000000000L) {
1272 printf("vcpu_thash: thash unsupported with rr7 @%lx\n",
1273 PSCB(vcpu,iip));
1274 return (IA64_ILLOP_FAULT);
1276 #endif
1277 //verbose("vcpu_thash: vadr=%p, VHPT_addr=%p\n",vadr,VHPT_addr);
1278 *pval = VHPT_addr;
1279 return (IA64_NO_FAULT);
1282 IA64FAULT vcpu_ttag(VCPU *vcpu, UINT64 vadr, UINT64 *padr)
1284 printf("vcpu_ttag: ttag instruction unsupported\n");
1285 return (IA64_ILLOP_FAULT);
1288 #define itir_ps(itir) ((itir >> 2) & 0x3f)
1289 #define itir_mask(itir) (~((1UL << itir_ps(itir)) - 1))
1291 unsigned long vhpt_translate_count = 0;
1293 IA64FAULT vcpu_translate(VCPU *vcpu, UINT64 address, BOOLEAN is_data, UINT64 *pteval, UINT64 *itir)
1295 unsigned long pta, pta_mask, iha, pte, ps;
1296 TR_ENTRY *trp;
1297 ia64_rr rr;
1299 if (!(address >> 61)) {
1300 if (!PSCB(vcpu,metaphysical_mode)) {
1301 REGS *regs = vcpu_regs(vcpu);
1302 unsigned long viip = PSCB(vcpu,iip);
1303 unsigned long vipsr = PSCB(vcpu,ipsr);
1304 unsigned long iip = regs->cr_iip;
1305 unsigned long ipsr = regs->cr_ipsr;
1306 printk("vcpu_translate: bad address %p, viip=%p, vipsr=%p, iip=%p, ipsr=%p continuing\n", address, viip, vipsr, iip, ipsr);
1309 *pteval = (address & _PAGE_PPN_MASK) | __DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX;
1310 *itir = PAGE_SHIFT << 2;
1311 phys_translate_count++;
1312 return IA64_NO_FAULT;
1315 /* check translation registers */
1316 if ((trp = match_tr(vcpu,address))) {
1317 tr_translate_count++;
1318 *pteval = trp->page_flags;
1319 *itir = trp->itir;
1320 return IA64_NO_FAULT;
1323 /* check 1-entry TLB */
1324 if ((trp = match_dtlb(vcpu,address))) {
1325 dtlb_translate_count++;
1326 if (vcpu->domain==dom0 && !in_tpa) *pteval = trp->page_flags;
1327 else *pteval = vcpu->arch.dtlb_pte;
1328 printf("DTLB MATCH... NEW, DOM%s, %s\n", vcpu->domain==dom0?
1329 "0":"U", in_tpa?"vcpu_tpa":"ia64_do_page_fault");
1330 *itir = trp->itir;
1331 return IA64_NO_FAULT;
1334 /* check guest VHPT */
1335 pta = PSCB(vcpu,pta);
1336 rr.rrval = PSCB(vcpu,rrs)[address>>61];
1337 if (rr.ve && (pta & IA64_PTA_VE))
1339 if (pta & IA64_PTA_VF)
1341 /* long format VHPT - not implemented */
1342 return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
1344 else
1346 /* short format VHPT */
1348 /* avoid recursively walking VHPT */
1349 pta_mask = (itir_mask(pta) << 3) >> 3;
1350 if (((address ^ pta) & pta_mask) == 0)
1351 return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
1353 vcpu_thash(vcpu, address, &iha);
1354 if (__copy_from_user(&pte, (void *)iha, sizeof(pte)) != 0)
1355 return IA64_VHPT_TRANS_VECTOR;
1357 /*
1358 * Optimisation: this VHPT walker aborts on not-present pages
1359 * instead of inserting a not-present translation, this allows
1360 * vectoring directly to the miss handler.
1361 \ */
1362 if (pte & _PAGE_P)
1364 *pteval = pte;
1365 *itir = vcpu_get_itir_on_fault(vcpu,address);
1366 vhpt_translate_count++;
1367 return IA64_NO_FAULT;
1369 return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
1372 return (is_data ? IA64_ALT_DATA_TLB_VECTOR : IA64_ALT_INST_TLB_VECTOR);
1375 IA64FAULT vcpu_tpa(VCPU *vcpu, UINT64 vadr, UINT64 *padr)
1377 UINT64 pteval, itir, mask;
1378 IA64FAULT fault;
1380 in_tpa = 1;
1381 fault = vcpu_translate(vcpu, vadr, 1, &pteval, &itir);
1382 in_tpa = 0;
1383 if (fault == IA64_NO_FAULT)
1385 mask = itir_mask(itir);
1386 *padr = (pteval & _PAGE_PPN_MASK & mask) | (vadr & ~mask);
1387 return (IA64_NO_FAULT);
1389 else
1391 PSCB(vcpu,tmp[0]) = vadr; // save ifa in vcpu structure, then specify IA64_FORCED_IFA
1392 return (fault | IA64_FORCED_IFA);
1396 IA64FAULT vcpu_tak(VCPU *vcpu, UINT64 vadr, UINT64 *key)
1398 printf("vcpu_tak: tak instruction unsupported\n");
1399 return (IA64_ILLOP_FAULT);
1400 // HACK ALERT: tak does a thash for now
1401 //return vcpu_thash(vcpu,vadr,key);
1404 /**************************************************************************
1405 VCPU debug breakpoint register access routines
1406 **************************************************************************/
1408 IA64FAULT vcpu_set_dbr(VCPU *vcpu, UINT64 reg, UINT64 val)
1410 // TODO: unimplemented DBRs return a reserved register fault
1411 // TODO: Should set Logical CPU state, not just physical
1412 ia64_set_dbr(reg,val);
1413 return (IA64_NO_FAULT);
1416 IA64FAULT vcpu_set_ibr(VCPU *vcpu, UINT64 reg, UINT64 val)
1418 // TODO: unimplemented IBRs return a reserved register fault
1419 // TODO: Should set Logical CPU state, not just physical
1420 ia64_set_ibr(reg,val);
1421 return (IA64_NO_FAULT);
1424 IA64FAULT vcpu_get_dbr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1426 // TODO: unimplemented DBRs return a reserved register fault
1427 UINT64 val = ia64_get_dbr(reg);
1428 *pval = val;
1429 return (IA64_NO_FAULT);
1432 IA64FAULT vcpu_get_ibr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1434 // TODO: unimplemented IBRs return a reserved register fault
1435 UINT64 val = ia64_get_ibr(reg);
1436 *pval = val;
1437 return (IA64_NO_FAULT);
1440 /**************************************************************************
1441 VCPU performance monitor register access routines
1442 **************************************************************************/
1444 IA64FAULT vcpu_set_pmc(VCPU *vcpu, UINT64 reg, UINT64 val)
1446 // TODO: Should set Logical CPU state, not just physical
1447 // NOTE: Writes to unimplemented PMC registers are discarded
1448 ia64_set_pmc(reg,val);
1449 return (IA64_NO_FAULT);
1452 IA64FAULT vcpu_set_pmd(VCPU *vcpu, UINT64 reg, UINT64 val)
1454 // TODO: Should set Logical CPU state, not just physical
1455 // NOTE: Writes to unimplemented PMD registers are discarded
1456 ia64_set_pmd(reg,val);
1457 return (IA64_NO_FAULT);
1460 IA64FAULT vcpu_get_pmc(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1462 // NOTE: Reads from unimplemented PMC registers return zero
1463 UINT64 val = (UINT64)ia64_get_pmc(reg);
1464 *pval = val;
1465 return (IA64_NO_FAULT);
1468 IA64FAULT vcpu_get_pmd(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1470 // NOTE: Reads from unimplemented PMD registers return zero
1471 UINT64 val = (UINT64)ia64_get_pmd(reg);
1472 *pval = val;
1473 return (IA64_NO_FAULT);
1476 /**************************************************************************
1477 VCPU banked general register access routines
1478 **************************************************************************/
1480 IA64FAULT vcpu_bsw0(VCPU *vcpu)
1482 // TODO: Only allowed for current vcpu
1483 REGS *regs = vcpu_regs(vcpu);
1484 unsigned long *r = &regs->r16;
1485 unsigned long *b0 = &PSCB(vcpu,bank0_regs[0]);
1486 unsigned long *b1 = &PSCB(vcpu,bank1_regs[0]);
1487 int i;
1489 if (PSCB(vcpu,banknum)) {
1490 for (i = 0; i < 16; i++) { *b1++ = *r; *r++ = *b0++; }
1491 PSCB(vcpu,banknum) = 0;
1493 return (IA64_NO_FAULT);
1496 IA64FAULT vcpu_bsw1(VCPU *vcpu)
1498 // TODO: Only allowed for current vcpu
1499 REGS *regs = vcpu_regs(vcpu);
1500 unsigned long *r = &regs->r16;
1501 unsigned long *b0 = &PSCB(vcpu,bank0_regs[0]);
1502 unsigned long *b1 = &PSCB(vcpu,bank1_regs[0]);
1503 int i;
1505 if (!PSCB(vcpu,banknum)) {
1506 for (i = 0; i < 16; i++) { *b0++ = *r; *r++ = *b1++; }
1507 PSCB(vcpu,banknum) = 1;
1509 return (IA64_NO_FAULT);
1512 /**************************************************************************
1513 VCPU cpuid access routines
1514 **************************************************************************/
1517 IA64FAULT vcpu_get_cpuid(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1519 // FIXME: This could get called as a result of a rsvd-reg fault
1520 // if reg > 3
1521 switch(reg) {
1522 case 0:
1523 memcpy(pval,"Xen/ia64",8);
1524 break;
1525 case 1:
1526 *pval = 0;
1527 break;
1528 case 2:
1529 *pval = 0;
1530 break;
1531 case 3:
1532 *pval = ia64_get_cpuid(3);
1533 break;
1534 case 4:
1535 *pval = ia64_get_cpuid(4);
1536 break;
1537 default:
1538 if (reg > (ia64_get_cpuid(3) & 0xff))
1539 return IA64_RSVDREG_FAULT;
1540 *pval = ia64_get_cpuid(reg);
1541 break;
1543 return (IA64_NO_FAULT);
1546 /**************************************************************************
1547 VCPU region register access routines
1548 **************************************************************************/
1550 unsigned long vcpu_get_rr_ve(VCPU *vcpu,UINT64 vadr)
1552 ia64_rr rr;
1554 rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
1555 return(rr.ve);
1558 IA64FAULT vcpu_set_rr(VCPU *vcpu, UINT64 reg, UINT64 val)
1560 PSCB(vcpu,rrs)[reg>>61] = val;
1561 // warning: set_one_rr() does it "live"
1562 set_one_rr(reg,val);
1563 return (IA64_NO_FAULT);
1566 IA64FAULT vcpu_get_rr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1568 UINT val = PSCB(vcpu,rrs)[reg>>61];
1569 *pval = val;
1570 return (IA64_NO_FAULT);
1573 /**************************************************************************
1574 VCPU protection key register access routines
1575 **************************************************************************/
1577 IA64FAULT vcpu_get_pkr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1579 #ifndef PKR_USE_FIXED
1580 printk("vcpu_get_pkr: called, not implemented yet\n");
1581 return IA64_ILLOP_FAULT;
1582 #else
1583 UINT64 val = (UINT64)ia64_get_pkr(reg);
1584 *pval = val;
1585 return (IA64_NO_FAULT);
1586 #endif
1589 IA64FAULT vcpu_set_pkr(VCPU *vcpu, UINT64 reg, UINT64 val)
1591 #ifndef PKR_USE_FIXED
1592 printk("vcpu_set_pkr: called, not implemented yet\n");
1593 return IA64_ILLOP_FAULT;
1594 #else
1595 // if (reg >= NPKRS) return (IA64_ILLOP_FAULT);
1596 vcpu->pkrs[reg] = val;
1597 ia64_set_pkr(reg,val);
1598 return (IA64_NO_FAULT);
1599 #endif
1602 /**************************************************************************
1603 VCPU translation register access routines
1604 **************************************************************************/
1606 static void vcpu_purge_tr_entry(TR_ENTRY *trp)
1608 trp->p = 0;
1611 static void vcpu_set_tr_entry(TR_ENTRY *trp, UINT64 pte, UINT64 itir, UINT64 ifa)
1613 UINT64 ps;
1615 trp->itir = itir;
1616 trp->rid = virtualize_rid(current, get_rr(ifa) & RR_RID_MASK);
1617 trp->p = 1;
1618 ps = trp->ps;
1619 trp->page_flags = pte;
1620 if (trp->pl < 2) trp->pl = 2;
1621 trp->vadr = ifa & ~0xfff;
1622 if (ps > 12) { // "ignore" relevant low-order bits
1623 trp->ppn &= ~((1UL<<(ps-12))-1);
1624 trp->vadr &= ~((1UL<<ps)-1);
1628 TR_ENTRY *vcpu_match_tr_entry(VCPU *vcpu, TR_ENTRY *trp, UINT64 ifa, int count)
1630 unsigned long rid = (get_rr(ifa) & RR_RID_MASK);
1631 int i;
1633 for (i = 0; i < count; i++, trp++) {
1634 if (!trp->p) continue;
1635 if (physicalize_rid(vcpu,trp->rid) != rid) continue;
1636 if (ifa < trp->vadr) continue;
1637 if (ifa >= (trp->vadr + (1L << trp->ps)) - 1) continue;
1638 //if (trp->key && !match_pkr(vcpu,trp->key)) continue;
1639 return trp;
1641 return 0;
1644 TR_ENTRY *match_tr(VCPU *vcpu, unsigned long ifa)
1646 TR_ENTRY *trp;
1648 trp = vcpu_match_tr_entry(vcpu,vcpu->arch.dtrs,ifa,NDTRS);
1649 if (trp) return trp;
1650 trp = vcpu_match_tr_entry(vcpu,vcpu->arch.itrs,ifa,NITRS);
1651 if (trp) return trp;
1652 return 0;
1655 IA64FAULT vcpu_itr_d(VCPU *vcpu, UINT64 slot, UINT64 pte,
1656 UINT64 itir, UINT64 ifa)
1658 TR_ENTRY *trp;
1660 if (slot >= NDTRS) return IA64_RSVDREG_FAULT;
1661 trp = &PSCBX(vcpu,dtrs[slot]);
1662 //printf("***** itr.d: setting slot %d: ifa=%p\n",slot,ifa);
1663 vcpu_set_tr_entry(trp,pte,itir,ifa);
1664 return IA64_NO_FAULT;
1667 IA64FAULT vcpu_itr_i(VCPU *vcpu, UINT64 slot, UINT64 pte,
1668 UINT64 itir, UINT64 ifa)
1670 TR_ENTRY *trp;
1672 if (slot >= NITRS) return IA64_RSVDREG_FAULT;
1673 trp = &PSCBX(vcpu,itrs[slot]);
1674 //printf("***** itr.i: setting slot %d: ifa=%p\n",slot,ifa);
1675 vcpu_set_tr_entry(trp,pte,itir,ifa);
1676 return IA64_NO_FAULT;
1679 /**************************************************************************
1680 VCPU translation cache access routines
1681 **************************************************************************/
1683 void foobar(void) { /*vcpu_verbose = 1;*/ }
1685 extern struct domain *dom0;
1687 void vcpu_itc_no_srlz(VCPU *vcpu, UINT64 IorD, UINT64 vaddr, UINT64 pte, UINT64 mp_pte, UINT64 logps)
1689 unsigned long psr;
1690 unsigned long ps = (vcpu->domain==dom0) ? logps : PAGE_SHIFT;
1692 // FIXME: validate ifa here (not in Xen space), COULD MACHINE CHECK!
1693 // FIXME, must be inlined or potential for nested fault here!
1694 if ((vcpu->domain==dom0) && (logps < PAGE_SHIFT)) {
1695 printf("vcpu_itc_no_srlz: domain0 use of smaller page size!\n");
1696 //FIXME: kill domain here
1697 while(1);
1699 psr = ia64_clear_ic();
1700 ia64_itc(IorD,vaddr,pte,ps); // FIXME: look for bigger mappings
1701 ia64_set_psr(psr);
1702 // ia64_srlz_i(); // no srls req'd, will rfi later
1703 #ifdef VHPT_GLOBAL
1704 if (vcpu->domain==dom0 && ((vaddr >> 61) == 7)) {
1705 // FIXME: this is dangerous... vhpt_flush_address ensures these
1706 // addresses never get flushed. More work needed if this
1707 // ever happens.
1708 //printf("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
1709 if (logps > PAGE_SHIFT) vhpt_multiple_insert(vaddr,pte,logps);
1710 else vhpt_insert(vaddr,pte,logps<<2);
1712 // even if domain pagesize is larger than PAGE_SIZE, just put
1713 // PAGE_SIZE mapping in the vhpt for now, else purging is complicated
1714 else vhpt_insert(vaddr,pte,PAGE_SHIFT<<2);
1715 #endif
1716 if (IorD & 0x4) return; // don't place in 1-entry TLB
1717 if (IorD & 0x1) {
1718 vcpu_set_tr_entry(&PSCBX(vcpu,itlb),pte,ps<<2,vaddr);
1719 PSCBX(vcpu,itlb_pte) = mp_pte;
1721 if (IorD & 0x2) {
1722 vcpu_set_tr_entry(&PSCBX(vcpu,dtlb),pte,ps<<2,vaddr);
1723 PSCBX(vcpu,dtlb_pte) = mp_pte;
1727 // NOTE: returns a physical pte, NOT a "metaphysical" pte, so do not check
1728 // the physical address contained for correctness
1729 TR_ENTRY *match_dtlb(VCPU *vcpu, unsigned long ifa)
1731 TR_ENTRY *trp;
1733 if (trp = vcpu_match_tr_entry(vcpu,&vcpu->arch.dtlb,ifa,1))
1734 return (&vcpu->arch.dtlb);
1735 return 0UL;
1738 IA64FAULT vcpu_itc_d(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
1740 unsigned long pteval, logps = (itir >> 2) & 0x3f;
1741 unsigned long translate_domain_pte(UINT64,UINT64,UINT64);
1743 if (logps < PAGE_SHIFT) {
1744 printf("vcpu_itc_d: domain trying to use smaller page size!\n");
1745 //FIXME: kill domain here
1746 while(1);
1748 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
1749 pteval = translate_domain_pte(pte,ifa,itir);
1750 if (!pteval) return IA64_ILLOP_FAULT;
1751 vcpu_itc_no_srlz(vcpu,2,ifa,pteval,pte,logps);
1752 return IA64_NO_FAULT;
1755 IA64FAULT vcpu_itc_i(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
1757 unsigned long pteval, logps = (itir >> 2) & 0x3f;
1758 unsigned long translate_domain_pte(UINT64,UINT64,UINT64);
1760 // FIXME: validate ifa here (not in Xen space), COULD MACHINE CHECK!
1761 if (logps < PAGE_SHIFT) {
1762 printf("vcpu_itc_i: domain trying to use smaller page size!\n");
1763 //FIXME: kill domain here
1764 while(1);
1766 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
1767 pteval = translate_domain_pte(pte,ifa,itir);
1768 // FIXME: what to do if bad physical address? (machine check?)
1769 if (!pteval) return IA64_ILLOP_FAULT;
1770 vcpu_itc_no_srlz(vcpu, 1,ifa,pteval,pte,logps);
1771 return IA64_NO_FAULT;
1774 IA64FAULT vcpu_ptc_l(VCPU *vcpu, UINT64 vadr, UINT64 addr_range)
1776 printk("vcpu_ptc_l: called, not implemented yet\n");
1777 return IA64_ILLOP_FAULT;
1780 // At privlvl=0, fc performs no access rights or protection key checks, while
1781 // at privlvl!=0, fc performs access rights checks as if it were a 1-byte
1782 // read but no protection key check. Thus in order to avoid an unexpected
1783 // access rights fault, we have to translate the virtual address to a
1784 // physical address (possibly via a metaphysical address) and do the fc
1785 // on the physical address, which is guaranteed to flush the same cache line
1786 IA64FAULT vcpu_fc(VCPU *vcpu, UINT64 vadr)
1788 // TODO: Only allowed for current vcpu
1789 UINT64 mpaddr, paddr;
1790 IA64FAULT fault;
1791 unsigned long translate_domain_mpaddr(unsigned long);
1792 IA64FAULT vcpu_tpa(VCPU *, UINT64, UINT64 *);
1794 fault = vcpu_tpa(vcpu, vadr, &mpaddr);
1795 if (fault == IA64_NO_FAULT) {
1796 paddr = translate_domain_mpaddr(mpaddr);
1797 ia64_fc(__va(paddr));
1799 return fault;
1802 int ptce_count = 0;
1803 IA64FAULT vcpu_ptc_e(VCPU *vcpu, UINT64 vadr)
1805 // Note that this only needs to be called once, i.e. the
1806 // architected loop to purge the entire TLB, should use
1807 // base = stride1 = stride2 = 0, count0 = count 1 = 1
1809 #ifdef VHPT_GLOBAL
1810 vhpt_flush(); // FIXME: This is overdoing it
1811 #endif
1812 local_flush_tlb_all();
1813 // just invalidate the "whole" tlb
1814 vcpu_purge_tr_entry(&PSCBX(vcpu,dtlb));
1815 vcpu_purge_tr_entry(&PSCBX(vcpu,itlb));
1816 return IA64_NO_FAULT;
1819 IA64FAULT vcpu_ptc_g(VCPU *vcpu, UINT64 vadr, UINT64 addr_range)
1821 printk("vcpu_ptc_g: called, not implemented yet\n");
1822 return IA64_ILLOP_FAULT;
1825 IA64FAULT vcpu_ptc_ga(VCPU *vcpu,UINT64 vadr,UINT64 addr_range)
1827 extern ia64_global_tlb_purge(UINT64 start, UINT64 end, UINT64 nbits);
1828 // FIXME: validate not flushing Xen addresses
1829 // if (Xen address) return(IA64_ILLOP_FAULT);
1830 // FIXME: ??breaks if domain PAGE_SIZE < Xen PAGE_SIZE
1831 //printf("######## vcpu_ptc_ga(%p,%p) ##############\n",vadr,addr_range);
1832 #ifdef VHPT_GLOBAL
1833 vhpt_flush_address(vadr,addr_range);
1834 #endif
1835 ia64_global_tlb_purge(vadr,vadr+addr_range,PAGE_SHIFT);
1836 vcpu_purge_tr_entry(&PSCBX(vcpu,dtlb));
1837 vcpu_purge_tr_entry(&PSCBX(vcpu,itlb));
1838 return IA64_NO_FAULT;
1841 IA64FAULT vcpu_ptr_d(VCPU *vcpu,UINT64 vadr,UINT64 addr_range)
1843 printf("vcpu_ptr_d: Purging TLB is unsupported\n");
1844 return (IA64_ILLOP_FAULT);
1847 IA64FAULT vcpu_ptr_i(VCPU *vcpu,UINT64 vadr,UINT64 addr_range)
1849 printf("vcpu_ptr_i: Purging TLB is unsupported\n");
1850 return (IA64_ILLOP_FAULT);
1853 void vcpu_set_regs(VCPU *vcpu, REGS *regs)
1855 vcpu->arch.regs = regs;