ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/kernel/cpu/common.c @ 7606:0b8f92adc679

Fix CPU hotplug -- cpu initialisation functions must be declared
__cpuinit or later hotplug references freed code and data.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Tue Nov 01 16:28:20 2005 +0100 (2005-11-01)
parents 06d84bf87159
children 090e44133d40
line source
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
9 #include <asm/i387.h>
10 #include <asm/msr.h>
11 #include <asm/io.h>
12 #include <asm/mmu_context.h>
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #include <asm/mpspec.h>
15 #include <asm/apic.h>
16 #include <mach_apic.h>
17 #endif
18 #include <asm/hypervisor.h>
20 #include "cpu.h"
22 #ifndef CONFIG_XEN
23 DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
24 EXPORT_PER_CPU_SYMBOL(cpu_gdt_table);
26 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
27 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
28 #endif
30 static int cachesize_override __initdata = -1;
31 static int disable_x86_fxsr __initdata = 0;
32 static int disable_x86_serial_nr __initdata = 1;
34 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
36 extern void mcheck_init(struct cpuinfo_x86 *c);
38 extern void machine_specific_modify_cpu_capabilities(struct cpuinfo_x86 *c);
40 extern int disable_pse;
42 static void default_init(struct cpuinfo_x86 * c)
43 {
44 /* Not much we can do here... */
45 /* Check if at least it has cpuid */
46 if (c->cpuid_level == -1) {
47 /* No cpuid. It must be an ancient CPU */
48 if (c->x86 == 4)
49 strcpy(c->x86_model_id, "486");
50 else if (c->x86 == 3)
51 strcpy(c->x86_model_id, "386");
52 }
53 }
55 static struct cpu_dev default_cpu = {
56 .c_init = default_init,
57 };
58 static struct cpu_dev * this_cpu = &default_cpu;
60 static int __init cachesize_setup(char *str)
61 {
62 get_option (&str, &cachesize_override);
63 return 1;
64 }
65 __setup("cachesize=", cachesize_setup);
67 int __init get_model_name(struct cpuinfo_x86 *c)
68 {
69 unsigned int *v;
70 char *p, *q;
72 if (cpuid_eax(0x80000000) < 0x80000004)
73 return 0;
75 v = (unsigned int *) c->x86_model_id;
76 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
77 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
78 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
79 c->x86_model_id[48] = 0;
81 /* Intel chips right-justify this string for some dumb reason;
82 undo that brain damage */
83 p = q = &c->x86_model_id[0];
84 while ( *p == ' ' )
85 p++;
86 if ( p != q ) {
87 while ( *p )
88 *q++ = *p++;
89 while ( q <= &c->x86_model_id[48] )
90 *q++ = '\0'; /* Zero-pad the rest */
91 }
93 return 1;
94 }
97 void __init display_cacheinfo(struct cpuinfo_x86 *c)
98 {
99 unsigned int n, dummy, ecx, edx, l2size;
101 n = cpuid_eax(0x80000000);
103 if (n >= 0x80000005) {
104 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
105 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
106 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
107 c->x86_cache_size=(ecx>>24)+(edx>>24);
108 }
110 if (n < 0x80000006) /* Some chips just has a large L1. */
111 return;
113 ecx = cpuid_ecx(0x80000006);
114 l2size = ecx >> 16;
116 /* do processor-specific cache resizing */
117 if (this_cpu->c_size_cache)
118 l2size = this_cpu->c_size_cache(c,l2size);
120 /* Allow user to override all this if necessary. */
121 if (cachesize_override != -1)
122 l2size = cachesize_override;
124 if ( l2size == 0 )
125 return; /* Again, no L2 cache is possible */
127 c->x86_cache_size = l2size;
129 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
130 l2size, ecx & 0xFF);
131 }
133 /* Naming convention should be: <Name> [(<Codename>)] */
134 /* This table only is used unless init_<vendor>() below doesn't set it; */
135 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
137 /* Look up CPU names by table lookup. */
138 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
139 {
140 struct cpu_model_info *info;
142 if ( c->x86_model >= 16 )
143 return NULL; /* Range check */
145 if (!this_cpu)
146 return NULL;
148 info = this_cpu->c_models;
150 while (info && info->family) {
151 if (info->family == c->x86)
152 return info->model_names[c->x86_model];
153 info++;
154 }
155 return NULL; /* Not found */
156 }
159 void __init get_cpu_vendor(struct cpuinfo_x86 *c, int early)
160 {
161 char *v = c->x86_vendor_id;
162 int i;
164 for (i = 0; i < X86_VENDOR_NUM; i++) {
165 if (cpu_devs[i]) {
166 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
167 (cpu_devs[i]->c_ident[1] &&
168 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
169 c->x86_vendor = i;
170 if (!early)
171 this_cpu = cpu_devs[i];
172 break;
173 }
174 }
175 }
176 }
179 static int __init x86_fxsr_setup(char * s)
180 {
181 disable_x86_fxsr = 1;
182 return 1;
183 }
184 __setup("nofxsr", x86_fxsr_setup);
187 /* Standard macro to see if a specific flag is changeable */
188 static inline int flag_is_changeable_p(u32 flag)
189 {
190 u32 f1, f2;
192 asm("pushfl\n\t"
193 "pushfl\n\t"
194 "popl %0\n\t"
195 "movl %0,%1\n\t"
196 "xorl %2,%0\n\t"
197 "pushl %0\n\t"
198 "popfl\n\t"
199 "pushfl\n\t"
200 "popl %0\n\t"
201 "popfl\n\t"
202 : "=&r" (f1), "=&r" (f2)
203 : "ir" (flag));
205 return ((f1^f2) & flag) != 0;
206 }
209 /* Probe for the CPUID instruction */
210 static int __init have_cpuid_p(void)
211 {
212 return flag_is_changeable_p(X86_EFLAGS_ID);
213 }
215 /* Do minimum CPU detection early.
216 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
217 The others are not touched to avoid unwanted side effects. */
218 static void __init early_cpu_detect(void)
219 {
220 struct cpuinfo_x86 *c = &boot_cpu_data;
222 c->x86_cache_alignment = 32;
224 if (!have_cpuid_p())
225 return;
227 /* Get vendor name */
228 cpuid(0x00000000, &c->cpuid_level,
229 (int *)&c->x86_vendor_id[0],
230 (int *)&c->x86_vendor_id[8],
231 (int *)&c->x86_vendor_id[4]);
233 get_cpu_vendor(c, 1);
235 c->x86 = 4;
236 if (c->cpuid_level >= 0x00000001) {
237 u32 junk, tfms, cap0, misc;
238 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
239 c->x86 = (tfms >> 8) & 15;
240 c->x86_model = (tfms >> 4) & 15;
241 if (c->x86 == 0xf) {
242 c->x86 += (tfms >> 20) & 0xff;
243 c->x86_model += ((tfms >> 16) & 0xF) << 4;
244 }
245 c->x86_mask = tfms & 15;
246 if (cap0 & (1<<19))
247 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
248 }
250 early_intel_workaround(c);
252 #ifdef CONFIG_X86_HT
253 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
254 #endif
255 }
257 void __init generic_identify(struct cpuinfo_x86 * c)
258 {
259 u32 tfms, xlvl;
260 int junk;
262 if (have_cpuid_p()) {
263 /* Get vendor name */
264 cpuid(0x00000000, &c->cpuid_level,
265 (int *)&c->x86_vendor_id[0],
266 (int *)&c->x86_vendor_id[8],
267 (int *)&c->x86_vendor_id[4]);
269 get_cpu_vendor(c, 0);
270 /* Initialize the standard set of capabilities */
271 /* Note that the vendor-specific code below might override */
273 /* Intel-defined flags: level 0x00000001 */
274 if ( c->cpuid_level >= 0x00000001 ) {
275 u32 capability, excap;
276 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
277 c->x86_capability[0] = capability;
278 c->x86_capability[4] = excap;
279 c->x86 = (tfms >> 8) & 15;
280 c->x86_model = (tfms >> 4) & 15;
281 if (c->x86 == 0xf) {
282 c->x86 += (tfms >> 20) & 0xff;
283 c->x86_model += ((tfms >> 16) & 0xF) << 4;
284 }
285 c->x86_mask = tfms & 15;
286 } else {
287 /* Have CPUID level 0 only - unheard of */
288 c->x86 = 4;
289 }
291 /* AMD-defined flags: level 0x80000001 */
292 xlvl = cpuid_eax(0x80000000);
293 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
294 if ( xlvl >= 0x80000001 ) {
295 c->x86_capability[1] = cpuid_edx(0x80000001);
296 c->x86_capability[6] = cpuid_ecx(0x80000001);
297 }
298 if ( xlvl >= 0x80000004 )
299 get_model_name(c); /* Default name */
300 }
301 }
302 }
304 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
305 {
306 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
307 /* Disable processor serial number */
308 unsigned long lo,hi;
309 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
310 lo |= 0x200000;
311 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
312 printk(KERN_NOTICE "CPU serial number disabled.\n");
313 clear_bit(X86_FEATURE_PN, c->x86_capability);
315 /* Disabling the serial number may affect the cpuid level */
316 c->cpuid_level = cpuid_eax(0);
317 }
318 }
320 static int __init x86_serial_nr_setup(char *s)
321 {
322 disable_x86_serial_nr = 0;
323 return 1;
324 }
325 __setup("serialnumber", x86_serial_nr_setup);
329 /*
330 * This does the hard work of actually picking apart the CPU stuff...
331 */
332 void __init identify_cpu(struct cpuinfo_x86 *c)
333 {
334 int i;
336 c->loops_per_jiffy = loops_per_jiffy;
337 c->x86_cache_size = -1;
338 c->x86_vendor = X86_VENDOR_UNKNOWN;
339 c->cpuid_level = -1; /* CPUID not detected */
340 c->x86_model = c->x86_mask = 0; /* So far unknown... */
341 c->x86_vendor_id[0] = '\0'; /* Unset */
342 c->x86_model_id[0] = '\0'; /* Unset */
343 c->x86_num_cores = 1;
344 memset(&c->x86_capability, 0, sizeof c->x86_capability);
346 if (!have_cpuid_p()) {
347 /* First of all, decide if this is a 486 or higher */
348 /* It's a 486 if we can modify the AC flag */
349 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
350 c->x86 = 4;
351 else
352 c->x86 = 3;
353 }
355 generic_identify(c);
357 printk(KERN_DEBUG "CPU: After generic identify, caps:");
358 for (i = 0; i < NCAPINTS; i++)
359 printk(" %08lx", c->x86_capability[i]);
360 printk("\n");
362 if (this_cpu->c_identify) {
363 this_cpu->c_identify(c);
365 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
366 for (i = 0; i < NCAPINTS; i++)
367 printk(" %08lx", c->x86_capability[i]);
368 printk("\n");
369 }
371 /*
372 * Vendor-specific initialization. In this section we
373 * canonicalize the feature flags, meaning if there are
374 * features a certain CPU supports which CPUID doesn't
375 * tell us, CPUID claiming incorrect flags, or other bugs,
376 * we handle them here.
377 *
378 * At the end of this section, c->x86_capability better
379 * indicate the features this CPU genuinely supports!
380 */
381 if (this_cpu->c_init)
382 this_cpu->c_init(c);
384 /* Disable the PN if appropriate */
385 squash_the_stupid_serial_number(c);
387 /*
388 * The vendor-specific functions might have changed features. Now
389 * we do "generic changes."
390 */
392 /* TSC disabled? */
393 if ( tsc_disable )
394 clear_bit(X86_FEATURE_TSC, c->x86_capability);
396 /* FXSR disabled? */
397 if (disable_x86_fxsr) {
398 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
399 clear_bit(X86_FEATURE_XMM, c->x86_capability);
400 }
402 if (disable_pse)
403 clear_bit(X86_FEATURE_PSE, c->x86_capability);
405 /* If the model name is still unset, do table lookup. */
406 if ( !c->x86_model_id[0] ) {
407 char *p;
408 p = table_lookup_model(c);
409 if ( p )
410 strcpy(c->x86_model_id, p);
411 else
412 /* Last resort... */
413 sprintf(c->x86_model_id, "%02x/%02x",
414 c->x86_vendor, c->x86_model);
415 }
417 machine_specific_modify_cpu_capabilities(c);
419 /* Now the feature flags better reflect actual CPU features! */
421 printk(KERN_DEBUG "CPU: After all inits, caps:");
422 for (i = 0; i < NCAPINTS; i++)
423 printk(" %08lx", c->x86_capability[i]);
424 printk("\n");
426 /*
427 * On SMP, boot_cpu_data holds the common feature set between
428 * all CPUs; so make sure that we indicate which features are
429 * common between the CPUs. The first time this routine gets
430 * executed, c == &boot_cpu_data.
431 */
432 if ( c != &boot_cpu_data ) {
433 /* AND the already accumulated flags with these */
434 for ( i = 0 ; i < NCAPINTS ; i++ )
435 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
436 }
438 /* Init Machine Check Exception if available. */
439 #ifdef CONFIG_X86_MCE
440 mcheck_init(c);
441 #endif
442 }
444 #ifdef CONFIG_X86_HT
445 void __init detect_ht(struct cpuinfo_x86 *c)
446 {
447 u32 eax, ebx, ecx, edx;
448 int index_msb, tmp;
449 int cpu = smp_processor_id();
451 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
452 return;
454 cpuid(1, &eax, &ebx, &ecx, &edx);
455 smp_num_siblings = (ebx & 0xff0000) >> 16;
457 if (smp_num_siblings == 1) {
458 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
459 } else if (smp_num_siblings > 1 ) {
460 index_msb = 31;
462 if (smp_num_siblings > NR_CPUS) {
463 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
464 smp_num_siblings = 1;
465 return;
466 }
467 tmp = smp_num_siblings;
468 while ((tmp & 0x80000000 ) == 0) {
469 tmp <<=1 ;
470 index_msb--;
471 }
472 if (smp_num_siblings & (smp_num_siblings - 1))
473 index_msb++;
474 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
476 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
477 phys_proc_id[cpu]);
479 smp_num_siblings = smp_num_siblings / c->x86_num_cores;
481 tmp = smp_num_siblings;
482 index_msb = 31;
483 while ((tmp & 0x80000000) == 0) {
484 tmp <<=1 ;
485 index_msb--;
486 }
488 if (smp_num_siblings & (smp_num_siblings - 1))
489 index_msb++;
491 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
493 if (c->x86_num_cores > 1)
494 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
495 cpu_core_id[cpu]);
496 }
497 }
498 #endif
500 void __init print_cpu_info(struct cpuinfo_x86 *c)
501 {
502 char *vendor = NULL;
504 if (c->x86_vendor < X86_VENDOR_NUM)
505 vendor = this_cpu->c_vendor;
506 else if (c->cpuid_level >= 0)
507 vendor = c->x86_vendor_id;
509 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
510 printk("%s ", vendor);
512 if (!c->x86_model_id[0])
513 printk("%d86", c->x86);
514 else
515 printk("%s", c->x86_model_id);
517 if (c->x86_mask || c->cpuid_level >= 0)
518 printk(" stepping %02x\n", c->x86_mask);
519 else
520 printk("\n");
521 }
523 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
525 /* This is hacky. :)
526 * We're emulating future behavior.
527 * In the future, the cpu-specific init functions will be called implicitly
528 * via the magic of initcalls.
529 * They will insert themselves into the cpu_devs structure.
530 * Then, when cpu_init() is called, we can just iterate over that array.
531 */
533 extern int intel_cpu_init(void);
534 extern int cyrix_init_cpu(void);
535 extern int nsc_init_cpu(void);
536 extern int amd_init_cpu(void);
537 extern int centaur_init_cpu(void);
538 extern int transmeta_init_cpu(void);
539 extern int rise_init_cpu(void);
540 extern int nexgen_init_cpu(void);
541 extern int umc_init_cpu(void);
543 void __init early_cpu_init(void)
544 {
545 intel_cpu_init();
546 cyrix_init_cpu();
547 nsc_init_cpu();
548 amd_init_cpu();
549 centaur_init_cpu();
550 transmeta_init_cpu();
551 rise_init_cpu();
552 nexgen_init_cpu();
553 umc_init_cpu();
554 early_cpu_detect();
556 #ifdef CONFIG_DEBUG_PAGEALLOC
557 /* pse is not compatible with on-the-fly unmapping,
558 * disable it even if the cpus claim to support it.
559 */
560 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
561 disable_pse = 1;
562 #endif
563 }
565 void __cpuinit cpu_gdt_init(struct Xgt_desc_struct *gdt_descr)
566 {
567 unsigned long frames[16];
568 unsigned long va;
569 int f;
571 for (va = gdt_descr->address, f = 0;
572 va < gdt_descr->address + gdt_descr->size;
573 va += PAGE_SIZE, f++) {
574 frames[f] = virt_to_mfn(va);
575 make_page_readonly((void *)va);
576 }
577 if (HYPERVISOR_set_gdt(frames, gdt_descr->size / 8))
578 BUG();
579 lgdt_finish();
580 }
582 /*
583 * cpu_init() initializes state that is per-CPU. Some data is already
584 * initialized (naturally) in the bootstrap process, such as the GDT
585 * and IDT. We reload them nevertheless, this function acts as a
586 * 'CPU state barrier', nothing should get across.
587 */
588 void __cpuinit cpu_init (void)
589 {
590 int cpu = smp_processor_id();
591 struct tss_struct * t = &per_cpu(init_tss, cpu);
592 struct thread_struct *thread = &current->thread;
594 if (cpu_test_and_set(cpu, cpu_initialized)) {
595 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
596 for (;;) local_irq_enable();
597 }
598 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
600 if (cpu_has_vme || cpu_has_de)
601 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
602 if (tsc_disable && cpu_has_tsc) {
603 printk(KERN_NOTICE "Disabling TSC...\n");
604 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
605 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
606 set_in_cr4(X86_CR4_TSD);
607 }
609 /*
610 * Set up the per-thread TLS descriptor cache:
611 */
612 memcpy(thread->tls_array, &get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN],
613 GDT_ENTRY_TLS_ENTRIES * 8);
615 cpu_gdt_init(&cpu_gdt_descr[cpu]);
617 /*
618 * Delete NT
619 */
620 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
622 /*
623 * Set up and load the per-CPU TSS and LDT
624 */
625 atomic_inc(&init_mm.mm_count);
626 current->active_mm = &init_mm;
627 if (current->mm)
628 BUG();
629 enter_lazy_tlb(&init_mm, current);
631 load_esp0(t, thread);
633 load_LDT(&init_mm.context);
635 /* Clear %fs and %gs. */
636 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
638 /* Clear all 6 debug registers: */
640 #define CD(register) HYPERVISOR_set_debugreg(register, 0)
642 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
644 #undef CD
646 /*
647 * Force FPU initialization:
648 */
649 current_thread_info()->status = 0;
650 clear_used_math();
651 mxcsr_feature_mask_init();
652 }