ia64/xen-unstable

view tools/libxc/xc_aout9.h @ 9488:0a6f5527ca4b

[IA64] set itv handoff as masked and enable reading irr[0-3]

Set initial vcpu itv handoff state to mask the timer vector.
This seems to match hardware and makes logical sense from a
spurious interrupt perspective. Enable vcpu_get_irr[0-3]
functions as they seem to work and have the proper backing.
This enables the check_sal_cache_flush() in arch/ia64/kernel.sal.c
to work unmodified, allowing us to remove the Xen changes from
the file (and thus the file from the sparse tree).

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild.aw
date Tue Apr 04 09:39:45 2006 -0600 (2006-04-04)
parents 0b5f09002630
children
line source
2 typedef struct Exec
3 {
4 long magic; /* magic number */
5 long text; /* size of text segment */
6 long data; /* size of initialized data */
7 long bss; /* size of uninitialized data */
8 long syms; /* size of symbol table */
9 long entry; /* entry point */
10 long spsz; /* size of pc/sp offset table */
11 long pcsz; /* size of pc/line number table */
12 } Exec;
14 #define _MAGIC(b) ((((4*b)+0)*b)+7)
15 #define A_MAGIC _MAGIC(8) /* 68020 */
16 #define I_MAGIC _MAGIC(11) /* intel 386 */
17 #define J_MAGIC _MAGIC(12) /* intel 960 (retired) */
18 #define K_MAGIC _MAGIC(13) /* sparc */
19 #define V_MAGIC _MAGIC(16) /* mips 3000 BE */
20 #define X_MAGIC _MAGIC(17) /* att dsp 3210 (retired) */
21 #define M_MAGIC _MAGIC(18) /* mips 4000 BE */
22 #define D_MAGIC _MAGIC(19) /* amd 29000 (retired) */
23 #define E_MAGIC _MAGIC(20) /* arm */
24 #define Q_MAGIC _MAGIC(21) /* powerpc */
25 #define N_MAGIC _MAGIC(22) /* mips 4000 LE */
26 #define L_MAGIC _MAGIC(23) /* dec alpha */
27 #define P_MAGIC _MAGIC(24) /* mips 3000 LE */
28 #define U_MAGIC _MAGIC(25) /* sparc64 */
29 #define S_MAGIC _MAGIC(26) /* amd64 */