ia64/xen-unstable

view linux-2.6.11-xen-sparse/arch/xen/i386/kernel/smpboot.c @ 5707:05b63285047c

Merge.
author sos22@douglas.cl.cam.ac.uk
date Fri Jul 08 17:38:38 2005 +0000 (2005-07-08)
parents 04d15727e6e8 9b73afea874e
children 215d8b2f3d94
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
41 #include <linux/mm.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/irq.h>
46 #include <linux/bootmem.h>
47 #include <linux/notifier.h>
48 #include <linux/cpu.h>
49 #include <linux/percpu.h>
51 #include <linux/delay.h>
52 #include <linux/mc146818rtc.h>
53 #include <asm/tlbflush.h>
54 #include <asm/desc.h>
55 #include <asm/arch_hooks.h>
57 #include <asm/smp_alt.h>
59 #ifndef CONFIG_X86_IO_APIC
60 #define Dprintk(args...)
61 #endif
62 #include <mach_wakecpu.h>
63 #include <smpboot_hooks.h>
65 /* Set if we find a B stepping CPU */
66 static int __initdata smp_b_stepping;
68 /* Number of siblings per CPU package */
69 int smp_num_siblings = 1;
70 int phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */
71 EXPORT_SYMBOL(phys_proc_id);
73 /* bitmap of online cpus */
74 cpumask_t cpu_online_map;
76 cpumask_t cpu_callin_map;
77 cpumask_t cpu_callout_map;
78 static cpumask_t smp_commenced_mask;
80 /* Per CPU bogomips and other parameters */
81 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
83 u8 x86_cpu_to_apicid[NR_CPUS] =
84 { [0 ... NR_CPUS-1] = 0xff };
85 EXPORT_SYMBOL(x86_cpu_to_apicid);
87 /* Set when the idlers are all forked */
88 int smp_threads_ready;
90 #if 0
91 /*
92 * Trampoline 80x86 program as an array.
93 */
95 extern unsigned char trampoline_data [];
96 extern unsigned char trampoline_end [];
97 static unsigned char *trampoline_base;
98 static int trampoline_exec;
99 #endif
101 #ifdef CONFIG_HOTPLUG_CPU
102 /* State of each CPU. */
103 DEFINE_PER_CPU(int, cpu_state) = { 0 };
104 #endif
106 static DEFINE_PER_CPU(int, resched_irq);
107 static DEFINE_PER_CPU(int, callfunc_irq);
108 static char resched_name[NR_CPUS][15];
109 static char callfunc_name[NR_CPUS][15];
111 #if 0
112 /*
113 * Currently trivial. Write the real->protected mode
114 * bootstrap into the page concerned. The caller
115 * has made sure it's suitably aligned.
116 */
118 static unsigned long __init setup_trampoline(void)
119 {
120 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
121 return virt_to_phys(trampoline_base);
122 }
123 #endif
125 /*
126 * We are called very early to get the low memory for the
127 * SMP bootup trampoline page.
128 */
129 void __init smp_alloc_memory(void)
130 {
131 #if 1
132 int cpu;
134 for (cpu = 1; cpu < NR_CPUS; cpu++) {
135 cpu_gdt_descr[cpu].address = (unsigned long)
136 alloc_bootmem_low_pages(PAGE_SIZE);
137 /* XXX free unused pages later */
138 }
139 #else
140 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
141 /*
142 * Has to be in very low memory so we can execute
143 * real-mode AP code.
144 */
145 if (__pa(trampoline_base) >= 0x9F000)
146 BUG();
147 /*
148 * Make the SMP trampoline executable:
149 */
150 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
151 #endif
152 }
154 /*
155 * The bootstrap kernel entry code has set these up. Save them for
156 * a given CPU
157 */
159 static void __init smp_store_cpu_info(int id)
160 {
161 struct cpuinfo_x86 *c = cpu_data + id;
163 *c = boot_cpu_data;
164 if (id!=0)
165 identify_cpu(c);
166 /*
167 * Mask B, Pentium, but not Pentium MMX
168 */
169 if (c->x86_vendor == X86_VENDOR_INTEL &&
170 c->x86 == 5 &&
171 c->x86_mask >= 1 && c->x86_mask <= 4 &&
172 c->x86_model <= 3)
173 /*
174 * Remember we have B step Pentia with bugs
175 */
176 smp_b_stepping = 1;
178 /*
179 * Certain Athlons might work (for various values of 'work') in SMP
180 * but they are not certified as MP capable.
181 */
182 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
184 /* Athlon 660/661 is valid. */
185 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
186 goto valid_k7;
188 /* Duron 670 is valid */
189 if ((c->x86_model==7) && (c->x86_mask==0))
190 goto valid_k7;
192 /*
193 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
194 * It's worth noting that the A5 stepping (662) of some Athlon XP's
195 * have the MP bit set.
196 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
197 */
198 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
199 ((c->x86_model==7) && (c->x86_mask>=1)) ||
200 (c->x86_model> 7))
201 if (cpu_has_mp)
202 goto valid_k7;
204 /* If we get here, it's not a certified SMP capable AMD system. */
205 tainted |= TAINT_UNSAFE_SMP;
206 }
208 valid_k7:
209 ;
210 }
212 #if 0
213 /*
214 * TSC synchronization.
215 *
216 * We first check whether all CPUs have their TSC's synchronized,
217 * then we print a warning if not, and always resync.
218 */
220 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
221 static atomic_t tsc_count_start = ATOMIC_INIT(0);
222 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
223 static unsigned long long tsc_values[NR_CPUS];
225 #define NR_LOOPS 5
227 static void __init synchronize_tsc_bp (void)
228 {
229 int i;
230 unsigned long long t0;
231 unsigned long long sum, avg;
232 long long delta;
233 unsigned long one_usec;
234 int buggy = 0;
236 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
238 /* convert from kcyc/sec to cyc/usec */
239 one_usec = cpu_khz / 1000;
241 atomic_set(&tsc_start_flag, 1);
242 wmb();
244 /*
245 * We loop a few times to get a primed instruction cache,
246 * then the last pass is more or less synchronized and
247 * the BP and APs set their cycle counters to zero all at
248 * once. This reduces the chance of having random offsets
249 * between the processors, and guarantees that the maximum
250 * delay between the cycle counters is never bigger than
251 * the latency of information-passing (cachelines) between
252 * two CPUs.
253 */
254 for (i = 0; i < NR_LOOPS; i++) {
255 /*
256 * all APs synchronize but they loop on '== num_cpus'
257 */
258 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
259 mb();
260 atomic_set(&tsc_count_stop, 0);
261 wmb();
262 /*
263 * this lets the APs save their current TSC:
264 */
265 atomic_inc(&tsc_count_start);
267 rdtscll(tsc_values[smp_processor_id()]);
268 /*
269 * We clear the TSC in the last loop:
270 */
271 if (i == NR_LOOPS-1)
272 write_tsc(0, 0);
274 /*
275 * Wait for all APs to leave the synchronization point:
276 */
277 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
278 mb();
279 atomic_set(&tsc_count_start, 0);
280 wmb();
281 atomic_inc(&tsc_count_stop);
282 }
284 sum = 0;
285 for (i = 0; i < NR_CPUS; i++) {
286 if (cpu_isset(i, cpu_callout_map)) {
287 t0 = tsc_values[i];
288 sum += t0;
289 }
290 }
291 avg = sum;
292 do_div(avg, num_booting_cpus());
294 sum = 0;
295 for (i = 0; i < NR_CPUS; i++) {
296 if (!cpu_isset(i, cpu_callout_map))
297 continue;
298 delta = tsc_values[i] - avg;
299 if (delta < 0)
300 delta = -delta;
301 /*
302 * We report bigger than 2 microseconds clock differences.
303 */
304 if (delta > 2*one_usec) {
305 long realdelta;
306 if (!buggy) {
307 buggy = 1;
308 printk("\n");
309 }
310 realdelta = delta;
311 do_div(realdelta, one_usec);
312 if (tsc_values[i] < avg)
313 realdelta = -realdelta;
315 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
316 }
318 sum += delta;
319 }
320 if (!buggy)
321 printk("passed.\n");
322 }
324 static void __init synchronize_tsc_ap (void)
325 {
326 int i;
328 /*
329 * Not every cpu is online at the time
330 * this gets called, so we first wait for the BP to
331 * finish SMP initialization:
332 */
333 while (!atomic_read(&tsc_start_flag)) mb();
335 for (i = 0; i < NR_LOOPS; i++) {
336 atomic_inc(&tsc_count_start);
337 while (atomic_read(&tsc_count_start) != num_booting_cpus())
338 mb();
340 rdtscll(tsc_values[smp_processor_id()]);
341 if (i == NR_LOOPS-1)
342 write_tsc(0, 0);
344 atomic_inc(&tsc_count_stop);
345 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
346 }
347 }
348 #undef NR_LOOPS
349 #endif
351 extern void calibrate_delay(void);
353 static atomic_t init_deasserted;
355 void __init smp_callin(void)
356 {
357 int cpuid, phys_id;
358 unsigned long timeout;
360 #if 0
361 /*
362 * If waken up by an INIT in an 82489DX configuration
363 * we may get here before an INIT-deassert IPI reaches
364 * our local APIC. We have to wait for the IPI or we'll
365 * lock up on an APIC access.
366 */
367 wait_for_init_deassert(&init_deasserted);
368 #endif
370 /*
371 * (This works even if the APIC is not enabled.)
372 */
373 phys_id = smp_processor_id();
374 cpuid = smp_processor_id();
375 if (cpu_isset(cpuid, cpu_callin_map)) {
376 printk("huh, phys CPU#%d, CPU#%d already present??\n",
377 phys_id, cpuid);
378 BUG();
379 }
380 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
382 /*
383 * STARTUP IPIs are fragile beasts as they might sometimes
384 * trigger some glue motherboard logic. Complete APIC bus
385 * silence for 1 second, this overestimates the time the
386 * boot CPU is spending to send the up to 2 STARTUP IPIs
387 * by a factor of two. This should be enough.
388 */
390 /*
391 * Waiting 2s total for startup (udelay is not yet working)
392 */
393 timeout = jiffies + 2*HZ;
394 while (time_before(jiffies, timeout)) {
395 /*
396 * Has the boot CPU finished it's STARTUP sequence?
397 */
398 if (cpu_isset(cpuid, cpu_callout_map))
399 break;
400 rep_nop();
401 }
403 if (!time_before(jiffies, timeout)) {
404 printk("BUG: CPU%d started up but did not get a callout!\n",
405 cpuid);
406 BUG();
407 }
409 #if 0
410 /*
411 * the boot CPU has finished the init stage and is spinning
412 * on callin_map until we finish. We are free to set up this
413 * CPU, first the APIC. (this is probably redundant on most
414 * boards)
415 */
417 Dprintk("CALLIN, before setup_local_APIC().\n");
418 smp_callin_clear_local_apic();
419 setup_local_APIC();
420 #endif
421 map_cpu_to_logical_apicid();
423 /*
424 * Get our bogomips.
425 */
426 calibrate_delay();
427 Dprintk("Stack at about %p\n",&cpuid);
429 /*
430 * Save our processor parameters
431 */
432 smp_store_cpu_info(cpuid);
434 #if 0
435 disable_APIC_timer();
436 #endif
438 /*
439 * Allow the master to continue.
440 */
441 cpu_set(cpuid, cpu_callin_map);
443 #if 0
444 /*
445 * Synchronize the TSC with the BP
446 */
447 if (cpu_has_tsc && cpu_khz)
448 synchronize_tsc_ap();
449 #endif
450 }
452 int cpucount;
455 static irqreturn_t ldebug_interrupt(
456 int irq, void *dev_id, struct pt_regs *regs)
457 {
458 return IRQ_HANDLED;
459 }
461 static DEFINE_PER_CPU(int, ldebug_irq);
462 static char ldebug_name[NR_CPUS][15];
464 void ldebug_setup(void)
465 {
466 int cpu = smp_processor_id();
468 per_cpu(ldebug_irq, cpu) = bind_virq_to_irq(VIRQ_DEBUG);
469 sprintf(ldebug_name[cpu], "ldebug%d", cpu);
470 BUG_ON(request_irq(per_cpu(ldebug_irq, cpu), ldebug_interrupt,
471 SA_INTERRUPT, ldebug_name[cpu], NULL));
472 }
475 extern void local_setup_timer(void);
477 /*
478 * Activate a secondary processor.
479 */
480 static void __init start_secondary(void *unused)
481 {
482 /*
483 * Dont put anything before smp_callin(), SMP
484 * booting is too fragile that we want to limit the
485 * things done here to the most necessary things.
486 */
487 cpu_init();
488 smp_callin();
489 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
490 rep_nop();
491 local_setup_timer();
492 ldebug_setup();
493 smp_intr_init();
494 local_irq_enable();
495 /*
496 * low-memory mappings have been cleared, flush them from
497 * the local TLBs too.
498 */
499 local_flush_tlb();
500 cpu_set(smp_processor_id(), cpu_online_map);
502 /* We can take interrupts now: we're officially "up". */
503 local_irq_enable();
505 wmb();
506 cpu_idle();
507 }
509 /*
510 * Everything has been set up for the secondary
511 * CPUs - they just need to reload everything
512 * from the task structure
513 * This function must not return.
514 */
515 void __init initialize_secondary(void)
516 {
517 /*
518 * We don't actually need to load the full TSS,
519 * basically just the stack pointer and the eip.
520 */
522 asm volatile(
523 "movl %0,%%esp\n\t"
524 "jmp *%1"
525 :
526 :"r" (current->thread.esp),"r" (current->thread.eip));
527 }
529 extern struct {
530 void * esp;
531 unsigned short ss;
532 } stack_start;
534 #ifdef CONFIG_NUMA
536 /* which logical CPUs are on which nodes */
537 cpumask_t node_2_cpu_mask[MAX_NUMNODES] =
538 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
539 /* which node each logical CPU is on */
540 int cpu_2_node[NR_CPUS] = { [0 ... NR_CPUS-1] = 0 };
541 EXPORT_SYMBOL(cpu_2_node);
543 /* set up a mapping between cpu and node. */
544 static inline void map_cpu_to_node(int cpu, int node)
545 {
546 printk("Mapping cpu %d to node %d\n", cpu, node);
547 cpu_set(cpu, node_2_cpu_mask[node]);
548 cpu_2_node[cpu] = node;
549 }
551 /* undo a mapping between cpu and node. */
552 static inline void unmap_cpu_to_node(int cpu)
553 {
554 int node;
556 printk("Unmapping cpu %d from all nodes\n", cpu);
557 for (node = 0; node < MAX_NUMNODES; node ++)
558 cpu_clear(cpu, node_2_cpu_mask[node]);
559 cpu_2_node[cpu] = 0;
560 }
561 #else /* !CONFIG_NUMA */
563 #define map_cpu_to_node(cpu, node) ({})
564 #define unmap_cpu_to_node(cpu) ({})
566 #endif /* CONFIG_NUMA */
568 u8 cpu_2_logical_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
570 void map_cpu_to_logical_apicid(void)
571 {
572 int cpu = smp_processor_id();
573 int apicid = smp_processor_id();
575 cpu_2_logical_apicid[cpu] = apicid;
576 map_cpu_to_node(cpu, apicid_to_node(apicid));
577 }
579 void unmap_cpu_to_logical_apicid(int cpu)
580 {
581 cpu_2_logical_apicid[cpu] = BAD_APICID;
582 unmap_cpu_to_node(cpu);
583 }
585 #if APIC_DEBUG
586 static inline void __inquire_remote_apic(int apicid)
587 {
588 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
589 char *names[] = { "ID", "VERSION", "SPIV" };
590 int timeout, status;
592 printk("Inquiring remote APIC #%d...\n", apicid);
594 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
595 printk("... APIC #%d %s: ", apicid, names[i]);
597 /*
598 * Wait for idle.
599 */
600 apic_wait_icr_idle();
602 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
603 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
605 timeout = 0;
606 do {
607 udelay(100);
608 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
609 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
611 switch (status) {
612 case APIC_ICR_RR_VALID:
613 status = apic_read(APIC_RRR);
614 printk("%08x\n", status);
615 break;
616 default:
617 printk("failed\n");
618 }
619 }
620 }
621 #endif
623 #if 0
624 #ifdef WAKE_SECONDARY_VIA_NMI
625 /*
626 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
627 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
628 * won't ... remember to clear down the APIC, etc later.
629 */
630 static int __init
631 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
632 {
633 unsigned long send_status = 0, accept_status = 0;
634 int timeout, maxlvt;
636 /* Target chip */
637 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
639 /* Boot on the stack */
640 /* Kick the second */
641 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
643 Dprintk("Waiting for send to finish...\n");
644 timeout = 0;
645 do {
646 Dprintk("+");
647 udelay(100);
648 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
649 } while (send_status && (timeout++ < 1000));
651 /*
652 * Give the other CPU some time to accept the IPI.
653 */
654 udelay(200);
655 /*
656 * Due to the Pentium erratum 3AP.
657 */
658 maxlvt = get_maxlvt();
659 if (maxlvt > 3) {
660 apic_read_around(APIC_SPIV);
661 apic_write(APIC_ESR, 0);
662 }
663 accept_status = (apic_read(APIC_ESR) & 0xEF);
664 Dprintk("NMI sent.\n");
666 if (send_status)
667 printk("APIC never delivered???\n");
668 if (accept_status)
669 printk("APIC delivery error (%lx).\n", accept_status);
671 return (send_status | accept_status);
672 }
673 #endif /* WAKE_SECONDARY_VIA_NMI */
675 #ifdef WAKE_SECONDARY_VIA_INIT
676 static int __init
677 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
678 {
679 unsigned long send_status = 0, accept_status = 0;
680 int maxlvt, timeout, num_starts, j;
682 /*
683 * Be paranoid about clearing APIC errors.
684 */
685 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
686 apic_read_around(APIC_SPIV);
687 apic_write(APIC_ESR, 0);
688 apic_read(APIC_ESR);
689 }
691 Dprintk("Asserting INIT.\n");
693 /*
694 * Turn INIT on target chip
695 */
696 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
698 /*
699 * Send IPI
700 */
701 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
702 | APIC_DM_INIT);
704 Dprintk("Waiting for send to finish...\n");
705 timeout = 0;
706 do {
707 Dprintk("+");
708 udelay(100);
709 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
710 } while (send_status && (timeout++ < 1000));
712 mdelay(10);
714 Dprintk("Deasserting INIT.\n");
716 /* Target chip */
717 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
719 /* Send IPI */
720 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
722 Dprintk("Waiting for send to finish...\n");
723 timeout = 0;
724 do {
725 Dprintk("+");
726 udelay(100);
727 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
728 } while (send_status && (timeout++ < 1000));
730 atomic_set(&init_deasserted, 1);
732 /*
733 * Should we send STARTUP IPIs ?
734 *
735 * Determine this based on the APIC version.
736 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
737 */
738 if (APIC_INTEGRATED(apic_version[phys_apicid]))
739 num_starts = 2;
740 else
741 num_starts = 0;
743 /*
744 * Run STARTUP IPI loop.
745 */
746 Dprintk("#startup loops: %d.\n", num_starts);
748 maxlvt = get_maxlvt();
750 for (j = 1; j <= num_starts; j++) {
751 Dprintk("Sending STARTUP #%d.\n",j);
752 apic_read_around(APIC_SPIV);
753 apic_write(APIC_ESR, 0);
754 apic_read(APIC_ESR);
755 Dprintk("After apic_write.\n");
757 /*
758 * STARTUP IPI
759 */
761 /* Target chip */
762 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
764 /* Boot on the stack */
765 /* Kick the second */
766 apic_write_around(APIC_ICR, APIC_DM_STARTUP
767 | (start_eip >> 12));
769 /*
770 * Give the other CPU some time to accept the IPI.
771 */
772 udelay(300);
774 Dprintk("Startup point 1.\n");
776 Dprintk("Waiting for send to finish...\n");
777 timeout = 0;
778 do {
779 Dprintk("+");
780 udelay(100);
781 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
782 } while (send_status && (timeout++ < 1000));
784 /*
785 * Give the other CPU some time to accept the IPI.
786 */
787 udelay(200);
788 /*
789 * Due to the Pentium erratum 3AP.
790 */
791 if (maxlvt > 3) {
792 apic_read_around(APIC_SPIV);
793 apic_write(APIC_ESR, 0);
794 }
795 accept_status = (apic_read(APIC_ESR) & 0xEF);
796 if (send_status || accept_status)
797 break;
798 }
799 Dprintk("After Startup.\n");
801 if (send_status)
802 printk("APIC never delivered???\n");
803 if (accept_status)
804 printk("APIC delivery error (%lx).\n", accept_status);
806 return (send_status | accept_status);
807 }
808 #endif /* WAKE_SECONDARY_VIA_INIT */
809 #endif
811 extern cpumask_t cpu_initialized;
813 static int __init do_boot_cpu(int apicid)
814 /*
815 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
816 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
817 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
818 */
819 {
820 struct task_struct *idle;
821 unsigned long boot_error;
822 int timeout, cpu;
823 unsigned long start_eip;
824 #if 0
825 unsigned short nmi_high = 0, nmi_low = 0;
826 #endif
827 vcpu_guest_context_t ctxt;
828 extern void startup_32_smp(void);
829 extern void hypervisor_callback(void);
830 extern void failsafe_callback(void);
831 extern void smp_trap_init(trap_info_t *);
832 int i;
834 cpu = ++cpucount;
835 /*
836 * We can't use kernel_thread since we must avoid to
837 * reschedule the child.
838 */
839 idle = fork_idle(cpu);
840 if (IS_ERR(idle))
841 panic("failed fork for CPU %d", cpu);
842 idle->thread.eip = (unsigned long) start_secondary;
843 /* start_eip had better be page-aligned! */
844 start_eip = (unsigned long)startup_32_smp;
846 /* So we see what's up */
847 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
848 /* Stack for startup_32 can be just as for start_secondary onwards */
849 stack_start.esp = (void *) idle->thread.esp;
851 irq_ctx_init(cpu);
853 /*
854 * This grunge runs the startup process for
855 * the targeted processor.
856 */
858 atomic_set(&init_deasserted, 0);
860 #if 1
861 if (cpu_gdt_descr[0].size > PAGE_SIZE)
862 BUG();
863 cpu_gdt_descr[cpu].size = cpu_gdt_descr[0].size;
864 memcpy((void *)cpu_gdt_descr[cpu].address,
865 (void *)cpu_gdt_descr[0].address, cpu_gdt_descr[0].size);
867 memset(&ctxt, 0, sizeof(ctxt));
869 ctxt.user_regs.ds = __USER_DS;
870 ctxt.user_regs.es = __USER_DS;
871 ctxt.user_regs.fs = 0;
872 ctxt.user_regs.gs = 0;
873 ctxt.user_regs.ss = __KERNEL_DS;
874 ctxt.user_regs.cs = __KERNEL_CS;
875 ctxt.user_regs.eip = start_eip;
876 ctxt.user_regs.esp = idle->thread.esp;
877 ctxt.user_regs.eflags = (1<<9) | (1<<2) | (idle->thread.io_pl<<12);
879 /* FPU is set up to default initial state. */
880 memset(&ctxt.fpu_ctxt, 0, sizeof(ctxt.fpu_ctxt));
882 /* Virtual IDT is empty at start-of-day. */
883 for ( i = 0; i < 256; i++ )
884 {
885 ctxt.trap_ctxt[i].vector = i;
886 ctxt.trap_ctxt[i].cs = FLAT_KERNEL_CS;
887 }
888 smp_trap_init(ctxt.trap_ctxt);
890 /* No LDT. */
891 ctxt.ldt_ents = 0;
893 {
894 unsigned long va;
895 int f;
897 for (va = cpu_gdt_descr[cpu].address, f = 0;
898 va < cpu_gdt_descr[cpu].address + cpu_gdt_descr[cpu].size;
899 va += PAGE_SIZE, f++) {
900 ctxt.gdt_frames[f] = virt_to_machine(va) >> PAGE_SHIFT;
901 make_page_readonly((void *)va);
902 }
903 ctxt.gdt_ents = cpu_gdt_descr[cpu].size / 8;
904 }
906 /* Ring 1 stack is the initial stack. */
907 ctxt.kernel_ss = __KERNEL_DS;
908 ctxt.kernel_sp = idle->thread.esp;
910 /* Callback handlers. */
911 ctxt.event_callback_cs = __KERNEL_CS;
912 ctxt.event_callback_eip = (unsigned long)hypervisor_callback;
913 ctxt.failsafe_callback_cs = __KERNEL_CS;
914 ctxt.failsafe_callback_eip = (unsigned long)failsafe_callback;
916 ctxt.ctrlreg[3] = (unsigned long)virt_to_machine(swapper_pg_dir);
918 boot_error = HYPERVISOR_boot_vcpu(cpu, &ctxt);
920 if (!boot_error) {
921 /*
922 * allow APs to start initializing.
923 */
924 Dprintk("Before Callout %d.\n", cpu);
925 cpu_set(cpu, cpu_callout_map);
926 Dprintk("After Callout %d.\n", cpu);
928 /*
929 * Wait 5s total for a response
930 */
931 for (timeout = 0; timeout < 50000; timeout++) {
932 if (cpu_isset(cpu, cpu_callin_map))
933 break; /* It has booted */
934 udelay(100);
935 }
937 if (cpu_isset(cpu, cpu_callin_map)) {
938 /* number CPUs logically, starting from 1 (BSP is 0) */
939 Dprintk("OK.\n");
940 printk("CPU%d: ", cpu);
941 print_cpu_info(&cpu_data[cpu]);
942 Dprintk("CPU has booted.\n");
943 } else {
944 boot_error= 1;
945 }
946 }
947 x86_cpu_to_apicid[cpu] = apicid;
948 if (boot_error) {
949 /* Try to put things back the way they were before ... */
950 unmap_cpu_to_logical_apicid(cpu);
951 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
952 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
953 cpucount--;
954 }
956 #else
957 Dprintk("Setting warm reset code and vector.\n");
959 store_NMI_vector(&nmi_high, &nmi_low);
961 smpboot_setup_warm_reset_vector(start_eip);
963 /*
964 * Starting actual IPI sequence...
965 */
966 boot_error = wakeup_secondary_cpu(apicid, start_eip);
968 if (!boot_error) {
969 /*
970 * allow APs to start initializing.
971 */
972 Dprintk("Before Callout %d.\n", cpu);
973 cpu_set(cpu, cpu_callout_map);
974 Dprintk("After Callout %d.\n", cpu);
976 /*
977 * Wait 5s total for a response
978 */
979 for (timeout = 0; timeout < 50000; timeout++) {
980 if (cpu_isset(cpu, cpu_callin_map))
981 break; /* It has booted */
982 udelay(100);
983 }
985 if (cpu_isset(cpu, cpu_callin_map)) {
986 /* number CPUs logically, starting from 1 (BSP is 0) */
987 Dprintk("OK.\n");
988 printk("CPU%d: ", cpu);
989 print_cpu_info(&cpu_data[cpu]);
990 Dprintk("CPU has booted.\n");
991 } else {
992 boot_error= 1;
993 if (*((volatile unsigned char *)trampoline_base)
994 == 0xA5)
995 /* trampoline started but...? */
996 printk("Stuck ??\n");
997 else
998 /* trampoline code not run */
999 printk("Not responding.\n");
1000 inquire_remote_apic(apicid);
1003 x86_cpu_to_apicid[cpu] = apicid;
1004 if (boot_error) {
1005 /* Try to put things back the way they were before ... */
1006 unmap_cpu_to_logical_apicid(cpu);
1007 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
1008 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
1009 cpucount--;
1012 /* mark "stuck" area as not stuck */
1013 *((volatile unsigned long *)trampoline_base) = 0;
1014 #endif
1016 return boot_error;
1019 cycles_t cacheflush_time;
1020 unsigned long cache_decay_ticks;
1022 static void smp_tune_scheduling (void)
1024 unsigned long cachesize; /* kB */
1025 unsigned long bandwidth = 350; /* MB/s */
1026 /*
1027 * Rough estimation for SMP scheduling, this is the number of
1028 * cycles it takes for a fully memory-limited process to flush
1029 * the SMP-local cache.
1031 * (For a P5 this pretty much means we will choose another idle
1032 * CPU almost always at wakeup time (this is due to the small
1033 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1034 * the cache size)
1035 */
1037 if (!cpu_khz) {
1038 /*
1039 * this basically disables processor-affinity
1040 * scheduling on SMP without a TSC.
1041 */
1042 cacheflush_time = 0;
1043 return;
1044 } else {
1045 cachesize = boot_cpu_data.x86_cache_size;
1046 if (cachesize == -1) {
1047 cachesize = 16; /* Pentiums, 2x8kB cache */
1048 bandwidth = 100;
1051 cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth;
1054 cache_decay_ticks = (long)cacheflush_time/cpu_khz + 1;
1056 printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n",
1057 (long)cacheflush_time/(cpu_khz/1000),
1058 ((long)cacheflush_time*100/(cpu_khz/1000)) % 100);
1059 printk("task migration cache decay timeout: %ld msecs.\n",
1060 cache_decay_ticks);
1063 /*
1064 * Cycle through the processors sending APIC IPIs to boot each.
1065 */
1067 #if 0
1068 static int boot_cpu_logical_apicid;
1069 #endif
1070 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1071 void *xquad_portio;
1073 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
1075 static void __init smp_boot_cpus(unsigned int max_cpus)
1077 int cpu, kicked;
1078 unsigned long bogosum = 0;
1079 #if 0
1080 int apicid, bit;
1081 #endif
1083 /*
1084 * Setup boot CPU information
1085 */
1086 smp_store_cpu_info(0); /* Final full version of the data */
1087 printk("CPU%d: ", 0);
1088 print_cpu_info(&cpu_data[0]);
1090 #if 0
1091 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1092 boot_cpu_logical_apicid = logical_smp_processor_id();
1093 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1094 #else
1095 // boot_cpu_physical_apicid = 0;
1096 // boot_cpu_logical_apicid = 0;
1097 x86_cpu_to_apicid[0] = 0;
1098 #endif
1100 current_thread_info()->cpu = 0;
1101 smp_tune_scheduling();
1102 cpus_clear(cpu_sibling_map[0]);
1103 cpu_set(0, cpu_sibling_map[0]);
1105 #ifdef CONFIG_X86_IO_APIC
1106 /*
1107 * If we couldn't find an SMP configuration at boot time,
1108 * get out of here now!
1109 */
1110 if (!smp_found_config && !acpi_lapic) {
1111 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1112 smpboot_clear_io_apic_irqs();
1113 #if 0
1114 phys_cpu_present_map = physid_mask_of_physid(0);
1115 #endif
1116 #ifdef CONFIG_X86_LOCAL_APIC
1117 if (APIC_init_uniprocessor())
1118 printk(KERN_NOTICE "Local APIC not detected."
1119 " Using dummy APIC emulation.\n");
1120 #endif
1121 map_cpu_to_logical_apicid();
1122 return;
1124 #endif
1126 #if 0
1127 /*
1128 * Should not be necessary because the MP table should list the boot
1129 * CPU too, but we do it for the sake of robustness anyway.
1130 * Makes no sense to do this check in clustered apic mode, so skip it
1131 */
1132 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1133 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1134 boot_cpu_physical_apicid);
1135 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1138 /*
1139 * If we couldn't find a local APIC, then get out of here now!
1140 */
1141 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1142 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1143 boot_cpu_physical_apicid);
1144 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1145 smpboot_clear_io_apic_irqs();
1146 phys_cpu_present_map = physid_mask_of_physid(0);
1147 return;
1150 verify_local_APIC();
1151 #endif
1153 /*
1154 * If SMP should be disabled, then really disable it!
1155 */
1156 if (!max_cpus) {
1157 HYPERVISOR_shared_info->n_vcpu = 1;
1158 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1159 smpboot_clear_io_apic_irqs();
1160 #if 0
1161 phys_cpu_present_map = physid_mask_of_physid(0);
1162 #endif
1163 return;
1166 smp_intr_init();
1168 #if 0
1169 connect_bsp_APIC();
1170 setup_local_APIC();
1171 #endif
1172 map_cpu_to_logical_apicid();
1173 #if 0
1176 setup_portio_remap();
1178 /*
1179 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1181 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1182 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1183 * clustered apic ID.
1184 */
1185 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1186 #endif
1187 Dprintk("CPU present map: %lx\n",
1188 (1UL << HYPERVISOR_shared_info->n_vcpu) - 1);
1190 kicked = 1;
1191 for (cpu = 1; kicked < NR_CPUS &&
1192 cpu < HYPERVISOR_shared_info->n_vcpu; cpu++) {
1193 if (max_cpus <= cpucount+1)
1194 continue;
1196 #ifdef CONFIG_SMP_ALTERNATIVES
1197 if (kicked == 1)
1198 prepare_for_smp();
1199 #endif
1200 if (do_boot_cpu(cpu))
1201 printk("CPU #%d not responding - cannot use it.\n",
1202 cpu);
1203 else
1204 ++kicked;
1207 #if 0
1208 /*
1209 * Cleanup possible dangling ends...
1210 */
1211 smpboot_restore_warm_reset_vector();
1212 #endif
1214 /*
1215 * Allow the user to impress friends.
1216 */
1217 Dprintk("Before bogomips.\n");
1218 for (cpu = 0; cpu < NR_CPUS; cpu++)
1219 if (cpu_isset(cpu, cpu_callout_map))
1220 bogosum += cpu_data[cpu].loops_per_jiffy;
1221 printk(KERN_INFO
1222 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1223 cpucount+1,
1224 bogosum/(500000/HZ),
1225 (bogosum/(5000/HZ))%100);
1227 Dprintk("Before bogocount - setting activated=1.\n");
1229 if (smp_b_stepping)
1230 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1232 /*
1233 * Don't taint if we are running SMP kernel on a single non-MP
1234 * approved Athlon
1235 */
1236 if (tainted & TAINT_UNSAFE_SMP) {
1237 if (cpucount)
1238 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1239 else
1240 tainted &= ~TAINT_UNSAFE_SMP;
1243 Dprintk("Boot done.\n");
1245 /*
1246 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1247 * efficiently.
1248 */
1249 for (cpu = 0; cpu < NR_CPUS; cpu++)
1250 cpus_clear(cpu_sibling_map[cpu]);
1252 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1253 int siblings = 0;
1254 int i;
1255 if (!cpu_isset(cpu, cpu_callout_map))
1256 continue;
1258 if (smp_num_siblings > 1) {
1259 for (i = 0; i < NR_CPUS; i++) {
1260 if (!cpu_isset(i, cpu_callout_map))
1261 continue;
1262 if (phys_proc_id[cpu] == phys_proc_id[i]) {
1263 siblings++;
1264 cpu_set(i, cpu_sibling_map[cpu]);
1267 } else {
1268 siblings++;
1269 cpu_set(cpu, cpu_sibling_map[cpu]);
1272 if (siblings != smp_num_siblings)
1273 printk(KERN_WARNING "WARNING: %d siblings found for CPU%d, should be %d\n", siblings, cpu, smp_num_siblings);
1276 #if 0
1277 if (nmi_watchdog == NMI_LOCAL_APIC)
1278 check_nmi_watchdog();
1279 #endif
1281 smpboot_setup_io_apic();
1283 #if 0
1284 setup_boot_APIC_clock();
1286 /*
1287 * Synchronize the TSC with the AP
1288 */
1289 if (cpu_has_tsc && cpucount && cpu_khz)
1290 synchronize_tsc_bp();
1291 #endif
1294 /* These are wrappers to interface to the new boot process. Someone
1295 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1296 void __init smp_prepare_cpus(unsigned int max_cpus)
1298 smp_commenced_mask = cpumask_of_cpu(0);
1299 cpu_callin_map = cpumask_of_cpu(0);
1300 mb();
1301 smp_boot_cpus(max_cpus);
1304 void __devinit smp_prepare_boot_cpu(void)
1306 cpu_set(smp_processor_id(), cpu_online_map);
1307 cpu_set(smp_processor_id(), cpu_callout_map);
1310 #ifdef CONFIG_HOTPLUG_CPU
1311 #include <asm-xen/ctrl_if.h>
1313 /* hotplug down/up funtion pointer and target vcpu */
1314 struct vcpu_hotplug_handler_t {
1315 void (*fn)(int vcpu);
1316 u32 vcpu;
1317 };
1318 static struct vcpu_hotplug_handler_t vcpu_hotplug_handler;
1320 /* must be called with the cpucontrol mutex held */
1321 static int __devinit cpu_enable(unsigned int cpu)
1323 #ifdef CONFIG_SMP_ALTERNATIVES
1324 if (num_online_cpus() == 1)
1325 prepare_for_smp();
1326 #endif
1328 /* get the target out of its holding state */
1329 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1330 wmb();
1332 /* wait for the processor to ack it. timeout? */
1333 while (!cpu_online(cpu))
1334 cpu_relax();
1336 fixup_irqs(cpu_online_map);
1338 /* counter the disable in fixup_irqs() */
1339 local_irq_enable();
1340 return 0;
1343 int __cpu_disable(void)
1345 cpumask_t map = cpu_online_map;
1346 int cpu = smp_processor_id();
1348 /*
1349 * Perhaps use cpufreq to drop frequency, but that could go
1350 * into generic code.
1352 * We won't take down the boot processor on i386 due to some
1353 * interrupts only being able to be serviced by the BSP.
1354 * Especially so if we're not using an IOAPIC -zwane
1355 */
1356 if (cpu == 0)
1357 return -EBUSY;
1359 cpu_clear(cpu, map);
1360 fixup_irqs(map);
1362 /* It's now safe to remove this processor from the online map */
1363 cpu_clear(cpu, cpu_online_map);
1365 #ifdef CONFIG_SMP_ALTERNATIVES
1366 if (num_online_cpus() == 1)
1367 unprepare_for_smp();
1368 #endif
1370 return 0;
1373 void __cpu_die(unsigned int cpu)
1375 /* We don't do anything here: idle task is faking death itself. */
1376 unsigned int i;
1378 for (i = 0; i < 10; i++) {
1379 /* They ack this in play_dead by setting CPU_DEAD */
1380 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
1381 return;
1382 current->state = TASK_UNINTERRUPTIBLE;
1383 schedule_timeout(HZ/10);
1385 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1388 static int vcpu_hotplug_cpu_process(void *unused)
1390 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1392 if (handler->fn) {
1393 (*(handler->fn))(handler->vcpu);
1394 handler->fn = NULL;
1396 return 0;
1399 static void __vcpu_hotplug_handler(void *unused)
1401 int err;
1403 err = kernel_thread(vcpu_hotplug_cpu_process,
1404 NULL, CLONE_FS | CLONE_FILES);
1405 if (err < 0)
1406 printk(KERN_ALERT "Error creating hotplug_cpu process!\n");
1410 static void vcpu_hotplug_event_handler(ctrl_msg_t *msg, unsigned long id)
1412 static DECLARE_WORK(vcpu_hotplug_work, __vcpu_hotplug_handler, NULL);
1413 vcpu_hotplug_t *req = (vcpu_hotplug_t *)&msg->msg[0];
1414 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1415 ssize_t ret;
1417 if (msg->length != sizeof(vcpu_hotplug_t))
1418 goto parse_error;
1420 /* grab target vcpu from msg */
1421 handler->vcpu = req->vcpu;
1423 /* determine which function to call based on msg subtype */
1424 switch (msg->subtype) {
1425 case CMSG_VCPU_HOTPLUG_OFF:
1426 handler->fn = (void *)&cpu_down;
1427 ret = schedule_work(&vcpu_hotplug_work);
1428 req->status = (u32) ret;
1429 break;
1430 case CMSG_VCPU_HOTPLUG_ON:
1431 handler->fn = (void *)&cpu_up;
1432 ret = schedule_work(&vcpu_hotplug_work);
1433 req->status = (u32) ret;
1434 break;
1435 default:
1436 goto parse_error;
1439 ctrl_if_send_response(msg);
1440 return;
1441 parse_error:
1442 msg->length = 0;
1443 ctrl_if_send_response(msg);
1446 static int __init setup_vcpu_hotplug_event(void)
1448 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1450 handler->fn = NULL;
1451 ctrl_if_register_receiver(CMSG_VCPU_HOTPLUG,
1452 vcpu_hotplug_event_handler, 0);
1454 return 0;
1457 __initcall(setup_vcpu_hotplug_event);
1459 #else /* ... !CONFIG_HOTPLUG_CPU */
1460 int __cpu_disable(void)
1462 return -ENOSYS;
1465 void __cpu_die(unsigned int cpu)
1467 /* We said "no" in __cpu_disable */
1468 BUG();
1470 #endif /* CONFIG_HOTPLUG_CPU */
1472 int __devinit __cpu_up(unsigned int cpu)
1474 /* In case one didn't come up */
1475 if (!cpu_isset(cpu, cpu_callin_map)) {
1476 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1477 local_irq_enable();
1478 return -EIO;
1481 #ifdef CONFIG_HOTPLUG_CPU
1482 #ifdef CONFIG_XEN
1483 /* Tell hypervisor to bring vcpu up. */
1484 HYPERVISOR_vcpu_up(cpu);
1485 #endif
1486 /* Already up, and in cpu_quiescent now? */
1487 if (cpu_isset(cpu, smp_commenced_mask)) {
1488 cpu_enable(cpu);
1489 return 0;
1491 #endif
1493 local_irq_enable();
1494 /* Unleash the CPU! */
1495 cpu_set(cpu, smp_commenced_mask);
1496 while (!cpu_isset(cpu, cpu_online_map))
1497 mb();
1498 return 0;
1501 void __init smp_cpus_done(unsigned int max_cpus)
1503 #if 1
1504 #else
1505 #ifdef CONFIG_X86_IO_APIC
1506 setup_ioapic_dest();
1507 #endif
1508 zap_low_mappings();
1509 /*
1510 * Disable executability of the SMP trampoline:
1511 */
1512 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1513 #endif
1516 extern irqreturn_t smp_reschedule_interrupt(int, void *, struct pt_regs *);
1517 extern irqreturn_t smp_call_function_interrupt(int, void *, struct pt_regs *);
1519 void __init smp_intr_init(void)
1521 int cpu = smp_processor_id();
1523 per_cpu(resched_irq, cpu) =
1524 bind_ipi_on_cpu_to_irq(RESCHEDULE_VECTOR);
1525 sprintf(resched_name[cpu], "resched%d", cpu);
1526 BUG_ON(request_irq(per_cpu(resched_irq, cpu), smp_reschedule_interrupt,
1527 SA_INTERRUPT, resched_name[cpu], NULL));
1529 per_cpu(callfunc_irq, cpu) =
1530 bind_ipi_on_cpu_to_irq(CALL_FUNCTION_VECTOR);
1531 sprintf(callfunc_name[cpu], "callfunc%d", cpu);
1532 BUG_ON(request_irq(per_cpu(callfunc_irq, cpu),
1533 smp_call_function_interrupt,
1534 SA_INTERRUPT, callfunc_name[cpu], NULL));