ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmcs.h @ 17416:0553004fa328

x86, vmx: Enable VPID (Virtual Processor Identification)

Allows TLB entries to be retained across VM entry and VM exit, and Xen
can now identify distinct address spaces through a new
virtual-processor ID (VPID) field of the VMCS.

Signed-off-by: Xin Li <xin.b.li@intel.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Xiaohui Xin <Xiaohui.xin@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Apr 09 14:34:49 2008 +0100 (2008-04-09)
parents 9b635405ef90
children 3da148fb7d9b
line source
1 /*
2 * vmcs.h: VMCS related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMCS_H__
20 #define __ASM_X86_HVM_VMX_VMCS_H__
22 #include <asm/config.h>
23 #include <asm/hvm/io.h>
24 #include <asm/hvm/vmx/vpmu.h>
26 extern void start_vmx(void);
27 extern void vmcs_dump_vcpu(struct vcpu *v);
28 extern void setup_vmcs_dump(void);
29 extern int vmx_cpu_up(void);
30 extern void vmx_cpu_down(void);
32 struct vmcs_struct {
33 u32 vmcs_revision_id;
34 unsigned char data [0]; /* vmcs size is read from MSR */
35 };
37 struct vmx_msr_entry {
38 u32 index;
39 u32 mbz;
40 u64 data;
41 };
43 enum {
44 VMX_INDEX_MSR_LSTAR = 0,
45 VMX_INDEX_MSR_STAR,
46 VMX_INDEX_MSR_SYSCALL_MASK,
48 VMX_MSR_COUNT
49 };
51 struct vmx_msr_state {
52 unsigned long flags;
53 unsigned long msrs[VMX_MSR_COUNT];
54 };
56 #define EPT_DEFAULT_MT 6
57 #define EPT_DEFAULT_GAW 3
59 struct vmx_domain {
60 unsigned long apic_access_mfn;
61 unsigned long vpid_base;
62 union {
63 struct {
64 u64 etmt :3,
65 gaw :3,
66 rsvd :6,
67 asr :52;
68 };
69 u64 eptp;
70 } ept_control;
71 };
73 struct arch_vmx_struct {
74 /* Virtual address of VMCS. */
75 struct vmcs_struct *vmcs;
77 /* Protects remote usage of VMCS (VMPTRLD/VMCLEAR). */
78 spinlock_t vmcs_lock;
80 /*
81 * Activation and launch status of this VMCS.
82 * - Activated on a CPU by VMPTRLD. Deactivated by VMCLEAR.
83 * - Launched on active CPU by VMLAUNCH when current VMCS.
84 */
85 struct list_head active_list;
86 int active_cpu;
87 int launched;
89 /* Cache of cpu execution control. */
90 u32 exec_control;
91 u32 secondary_exec_control;
93 u16 vpid;
95 /* PMU */
96 struct vpmu_struct vpmu;
98 #ifdef __x86_64__
99 struct vmx_msr_state msr_state;
100 unsigned long shadow_gs;
101 unsigned long cstar;
102 #endif
104 unsigned long *msr_bitmap;
105 unsigned int msr_count;
106 struct vmx_msr_entry *msr_area;
107 unsigned int host_msr_count;
108 struct vmx_msr_entry *host_msr_area;
110 unsigned long host_cr0;
112 /* Are we emulating rather than VMENTERing? */
113 #define VMXEMUL_REALMODE 1 /* Yes, because CR0.PE == 0 */
114 #define VMXEMUL_BAD_CS 2 /* Yes, because CS.RPL != CPL */
115 #define VMXEMUL_BAD_SS 4 /* Yes, because SS.RPL != CPL */
116 uint8_t vmxemul;
117 };
119 int vmx_create_vmcs(struct vcpu *v);
120 void vmx_destroy_vmcs(struct vcpu *v);
121 void vmx_vmcs_enter(struct vcpu *v);
122 void vmx_vmcs_exit(struct vcpu *v);
124 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
125 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
126 #define CPU_BASED_HLT_EXITING 0x00000080
127 #define CPU_BASED_INVLPG_EXITING 0x00000200
128 #define CPU_BASED_MWAIT_EXITING 0x00000400
129 #define CPU_BASED_RDPMC_EXITING 0x00000800
130 #define CPU_BASED_RDTSC_EXITING 0x00001000
131 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000
132 #define CPU_BASED_CR3_STORE_EXITING 0x00010000
133 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
134 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
135 #define CPU_BASED_TPR_SHADOW 0x00200000
136 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
137 #define CPU_BASED_MOV_DR_EXITING 0x00800000
138 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
139 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
140 #define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000
141 #define CPU_BASED_MONITOR_EXITING 0x20000000
142 #define CPU_BASED_PAUSE_EXITING 0x40000000
143 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
144 extern u32 vmx_cpu_based_exec_control;
146 #define PIN_BASED_EXT_INTR_MASK 0x00000001
147 #define PIN_BASED_NMI_EXITING 0x00000008
148 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
149 extern u32 vmx_pin_based_exec_control;
151 #define VM_EXIT_IA32E_MODE 0x00000200
152 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
153 extern u32 vmx_vmexit_control;
155 #define VM_ENTRY_IA32E_MODE 0x00000200
156 #define VM_ENTRY_SMM 0x00000400
157 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
158 extern u32 vmx_vmentry_control;
160 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
161 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002
162 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020
163 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
164 extern u32 vmx_secondary_exec_control;
166 extern bool_t cpu_has_vmx_ins_outs_instr_info;
168 #define cpu_has_wbinvd_exiting \
169 (vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING)
170 #define cpu_has_vmx_virtualize_apic_accesses \
171 (vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
172 #define cpu_has_vmx_tpr_shadow \
173 (vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)
174 #define cpu_has_vmx_vnmi \
175 (vmx_pin_based_exec_control & PIN_BASED_VIRTUAL_NMIS)
176 #define cpu_has_vmx_msr_bitmap \
177 (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP)
178 #define cpu_has_vmx_secondary_exec_control \
179 (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
180 #define cpu_has_vmx_ept \
181 (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)
182 #define cpu_has_vmx_vpid \
183 (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
185 /* GUEST_INTERRUPTIBILITY_INFO flags. */
186 #define VMX_INTR_SHADOW_STI 0x00000001
187 #define VMX_INTR_SHADOW_MOV_SS 0x00000002
188 #define VMX_INTR_SHADOW_SMI 0x00000004
189 #define VMX_INTR_SHADOW_NMI 0x00000008
191 /* VMCS field encodings. */
192 enum vmcs_field {
193 VIRTUAL_PROCESSOR_ID = 0x00000000,
194 GUEST_ES_SELECTOR = 0x00000800,
195 GUEST_CS_SELECTOR = 0x00000802,
196 GUEST_SS_SELECTOR = 0x00000804,
197 GUEST_DS_SELECTOR = 0x00000806,
198 GUEST_FS_SELECTOR = 0x00000808,
199 GUEST_GS_SELECTOR = 0x0000080a,
200 GUEST_LDTR_SELECTOR = 0x0000080c,
201 GUEST_TR_SELECTOR = 0x0000080e,
202 HOST_ES_SELECTOR = 0x00000c00,
203 HOST_CS_SELECTOR = 0x00000c02,
204 HOST_SS_SELECTOR = 0x00000c04,
205 HOST_DS_SELECTOR = 0x00000c06,
206 HOST_FS_SELECTOR = 0x00000c08,
207 HOST_GS_SELECTOR = 0x00000c0a,
208 HOST_TR_SELECTOR = 0x00000c0c,
209 IO_BITMAP_A = 0x00002000,
210 IO_BITMAP_A_HIGH = 0x00002001,
211 IO_BITMAP_B = 0x00002002,
212 IO_BITMAP_B_HIGH = 0x00002003,
213 MSR_BITMAP = 0x00002004,
214 MSR_BITMAP_HIGH = 0x00002005,
215 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
216 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
217 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
218 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
219 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
220 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
221 TSC_OFFSET = 0x00002010,
222 TSC_OFFSET_HIGH = 0x00002011,
223 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
224 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
225 APIC_ACCESS_ADDR = 0x00002014,
226 APIC_ACCESS_ADDR_HIGH = 0x00002015,
227 EPT_POINTER = 0x0000201a,
228 EPT_POINTER_HIGH = 0x0000201b,
229 GUEST_PHYSICAL_ADDRESS = 0x00002400,
230 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
231 VMCS_LINK_POINTER = 0x00002800,
232 VMCS_LINK_POINTER_HIGH = 0x00002801,
233 GUEST_IA32_DEBUGCTL = 0x00002802,
234 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
235 GUEST_PDPTR0 = 0x0000280a,
236 GUEST_PDPTR0_HIGH = 0x0000280b,
237 GUEST_PDPTR1 = 0x0000280c,
238 GUEST_PDPTR1_HIGH = 0x0000280d,
239 GUEST_PDPTR2 = 0x0000280e,
240 GUEST_PDPTR2_HIGH = 0x0000280f,
241 GUEST_PDPTR3 = 0x00002810,
242 GUEST_PDPTR3_HIGH = 0x00002811,
243 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
244 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
245 EXCEPTION_BITMAP = 0x00004004,
246 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
247 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
248 CR3_TARGET_COUNT = 0x0000400a,
249 VM_EXIT_CONTROLS = 0x0000400c,
250 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
251 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
252 VM_ENTRY_CONTROLS = 0x00004012,
253 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
254 VM_ENTRY_INTR_INFO = 0x00004016,
255 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
256 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
257 TPR_THRESHOLD = 0x0000401c,
258 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
259 VM_INSTRUCTION_ERROR = 0x00004400,
260 VM_EXIT_REASON = 0x00004402,
261 VM_EXIT_INTR_INFO = 0x00004404,
262 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
263 IDT_VECTORING_INFO = 0x00004408,
264 IDT_VECTORING_ERROR_CODE = 0x0000440a,
265 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
266 VMX_INSTRUCTION_INFO = 0x0000440e,
267 GUEST_ES_LIMIT = 0x00004800,
268 GUEST_CS_LIMIT = 0x00004802,
269 GUEST_SS_LIMIT = 0x00004804,
270 GUEST_DS_LIMIT = 0x00004806,
271 GUEST_FS_LIMIT = 0x00004808,
272 GUEST_GS_LIMIT = 0x0000480a,
273 GUEST_LDTR_LIMIT = 0x0000480c,
274 GUEST_TR_LIMIT = 0x0000480e,
275 GUEST_GDTR_LIMIT = 0x00004810,
276 GUEST_IDTR_LIMIT = 0x00004812,
277 GUEST_ES_AR_BYTES = 0x00004814,
278 GUEST_CS_AR_BYTES = 0x00004816,
279 GUEST_SS_AR_BYTES = 0x00004818,
280 GUEST_DS_AR_BYTES = 0x0000481a,
281 GUEST_FS_AR_BYTES = 0x0000481c,
282 GUEST_GS_AR_BYTES = 0x0000481e,
283 GUEST_LDTR_AR_BYTES = 0x00004820,
284 GUEST_TR_AR_BYTES = 0x00004822,
285 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
286 GUEST_ACTIVITY_STATE = 0x00004826,
287 GUEST_SYSENTER_CS = 0x0000482A,
288 HOST_SYSENTER_CS = 0x00004c00,
289 CR0_GUEST_HOST_MASK = 0x00006000,
290 CR4_GUEST_HOST_MASK = 0x00006002,
291 CR0_READ_SHADOW = 0x00006004,
292 CR4_READ_SHADOW = 0x00006006,
293 CR3_TARGET_VALUE0 = 0x00006008,
294 CR3_TARGET_VALUE1 = 0x0000600a,
295 CR3_TARGET_VALUE2 = 0x0000600c,
296 CR3_TARGET_VALUE3 = 0x0000600e,
297 EXIT_QUALIFICATION = 0x00006400,
298 GUEST_LINEAR_ADDRESS = 0x0000640a,
299 GUEST_CR0 = 0x00006800,
300 GUEST_CR3 = 0x00006802,
301 GUEST_CR4 = 0x00006804,
302 GUEST_ES_BASE = 0x00006806,
303 GUEST_CS_BASE = 0x00006808,
304 GUEST_SS_BASE = 0x0000680a,
305 GUEST_DS_BASE = 0x0000680c,
306 GUEST_FS_BASE = 0x0000680e,
307 GUEST_GS_BASE = 0x00006810,
308 GUEST_LDTR_BASE = 0x00006812,
309 GUEST_TR_BASE = 0x00006814,
310 GUEST_GDTR_BASE = 0x00006816,
311 GUEST_IDTR_BASE = 0x00006818,
312 GUEST_DR7 = 0x0000681a,
313 GUEST_RSP = 0x0000681c,
314 GUEST_RIP = 0x0000681e,
315 GUEST_RFLAGS = 0x00006820,
316 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
317 GUEST_SYSENTER_ESP = 0x00006824,
318 GUEST_SYSENTER_EIP = 0x00006826,
319 HOST_CR0 = 0x00006c00,
320 HOST_CR3 = 0x00006c02,
321 HOST_CR4 = 0x00006c04,
322 HOST_FS_BASE = 0x00006c06,
323 HOST_GS_BASE = 0x00006c08,
324 HOST_TR_BASE = 0x00006c0a,
325 HOST_GDTR_BASE = 0x00006c0c,
326 HOST_IDTR_BASE = 0x00006c0e,
327 HOST_SYSENTER_ESP = 0x00006c10,
328 HOST_SYSENTER_EIP = 0x00006c12,
329 HOST_RSP = 0x00006c14,
330 HOST_RIP = 0x00006c16,
331 };
333 #define VMCS_VPID_WIDTH 16
335 void vmx_disable_intercept_for_msr(struct vcpu *v, u32 msr);
336 int vmx_read_guest_msr(struct vcpu *v, u32 msr, u64 *val);
337 int vmx_write_guest_msr(struct vcpu *v, u32 msr, u64 val);
338 int vmx_add_guest_msr(struct vcpu *v, u32 msr);
339 int vmx_add_host_load_msr(struct vcpu *v, u32 msr);
341 #endif /* ASM_X86_HVM_VMX_VMCS_H__ */
343 /*
344 * Local variables:
345 * mode: C
346 * c-set-style: "BSD"
347 * c-basic-offset: 4
348 * tab-width: 4
349 * indent-tabs-mode: nil
350 * End:
351 */