ia64/xen-unstable

view xen/arch/x86/hvm/vmx/vmx.c @ 8974:0349fb4de335

Clean up some vmx code.

Signed-off-by: Xin Li <xin.b.li@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Feb 23 11:34:11 2006 +0100 (2006-02-23)
parents b5bb9920bf48
children cf1c1bb9f6d2
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <asm/current.h>
29 #include <asm/io.h>
30 #include <asm/shadow.h>
31 #include <asm/regs.h>
32 #include <asm/cpufeature.h>
33 #include <asm/processor.h>
34 #include <asm/types.h>
35 #include <asm/msr.h>
36 #include <asm/spinlock.h>
37 #include <asm/hvm/hvm.h>
38 #include <asm/hvm/support.h>
39 #include <asm/hvm/vmx/vmx.h>
40 #include <asm/hvm/vmx/vmcs.h>
41 #include <asm/shadow.h>
42 #if CONFIG_PAGING_LEVELS >= 3
43 #include <asm/shadow_64.h>
44 #endif
45 #include <public/sched.h>
46 #include <public/hvm/ioreq.h>
47 #include <asm/hvm/vpic.h>
48 #include <asm/hvm/vlapic.h>
50 static unsigned long trace_values[NR_CPUS][4];
51 #define TRACE_VMEXIT(index,value) trace_values[smp_processor_id()][index]=value
53 void vmx_final_setup_guest(struct vcpu *v)
54 {
55 v->arch.schedule_tail = arch_vmx_do_launch;
57 if ( v->vcpu_id == 0 )
58 {
59 struct domain *d = v->domain;
60 struct vcpu *vc;
62 /* Initialize monitor page table */
63 for_each_vcpu(d, vc)
64 vc->arch.monitor_table = mk_pagetable(0);
66 /*
67 * Required to do this once per domain
68 * XXX todo: add a seperate function to do these.
69 */
70 memset(&d->shared_info->evtchn_mask[0], 0xff,
71 sizeof(d->shared_info->evtchn_mask));
73 /* Put the domain in shadow mode even though we're going to be using
74 * the shared 1:1 page table initially. It shouldn't hurt */
75 shadow_mode_enable(d,
76 SHM_enable|SHM_refcounts|
77 SHM_translate|SHM_external|SHM_wr_pt_pte);
78 }
79 }
81 void vmx_relinquish_resources(struct vcpu *v)
82 {
83 struct hvm_virpit *vpit;
85 if (v->vcpu_id == 0) {
86 /* unmap IO shared page */
87 struct domain *d = v->domain;
88 if ( d->arch.hvm_domain.shared_page_va )
89 unmap_domain_page_global(
90 (void *)d->arch.hvm_domain.shared_page_va);
91 shadow_direct_map_clean(d);
92 }
94 vmx_request_clear_vmcs(v);
95 destroy_vmcs(&v->arch.hvm_vmx);
96 free_monitor_pagetable(v);
97 vpit = &v->domain->arch.hvm_domain.vpit;
98 kill_timer(&vpit->pit_timer);
99 kill_timer(&v->arch.hvm_vmx.hlt_timer);
100 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
101 {
102 kill_timer(&VLAPIC(v)->vlapic_timer);
103 xfree(VLAPIC(v));
104 }
105 }
107 #ifdef __x86_64__
108 static struct vmx_msr_state percpu_msr[NR_CPUS];
110 static u32 msr_data_index[VMX_MSR_COUNT] =
111 {
112 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
113 MSR_SYSCALL_MASK, MSR_EFER,
114 };
116 void vmx_save_segments(struct vcpu *v)
117 {
118 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
119 }
121 /*
122 * To avoid MSR save/restore at every VM exit/entry time, we restore
123 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
124 * are not modified once set for generic domains, we don't save them,
125 * but simply reset them to the values set at percpu_traps_init().
126 */
127 void vmx_load_msrs(void)
128 {
129 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
130 int i;
132 while ( host_state->flags )
133 {
134 i = find_first_set_bit(host_state->flags);
135 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
136 clear_bit(i, &host_state->flags);
137 }
138 }
140 static void vmx_save_init_msrs(void)
141 {
142 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
143 int i;
145 for ( i = 0; i < VMX_MSR_COUNT; i++ )
146 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
147 }
149 #define CASE_READ_MSR(address) \
150 case MSR_ ## address: \
151 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
152 break
154 #define CASE_WRITE_MSR(address) \
155 case MSR_ ## address: \
156 { \
157 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
158 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
159 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
160 } \
161 wrmsrl(MSR_ ## address, msr_content); \
162 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
163 } \
164 break
166 #define IS_CANO_ADDRESS(add) 1
167 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
168 {
169 u64 msr_content = 0;
170 struct vcpu *vc = current;
171 struct vmx_msr_state * msr = &vc->arch.hvm_vmx.msr_content;
172 switch(regs->ecx){
173 case MSR_EFER:
174 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
175 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content %llx\n", (unsigned long long)msr_content);
176 if (test_bit(VMX_CPU_STATE_LME_ENABLED,
177 &vc->arch.hvm_vmx.cpu_state))
178 msr_content |= 1 << _EFER_LME;
180 if (VMX_LONG_GUEST(vc))
181 msr_content |= 1 << _EFER_LMA;
182 break;
183 case MSR_FS_BASE:
184 if (!(VMX_LONG_GUEST(vc)))
185 /* XXX should it be GP fault */
186 domain_crash_synchronous();
187 __vmread(GUEST_FS_BASE, &msr_content);
188 break;
189 case MSR_GS_BASE:
190 if (!(VMX_LONG_GUEST(vc)))
191 domain_crash_synchronous();
192 __vmread(GUEST_GS_BASE, &msr_content);
193 break;
194 case MSR_SHADOW_GS_BASE:
195 msr_content = msr->shadow_gs;
196 break;
198 CASE_READ_MSR(STAR);
199 CASE_READ_MSR(LSTAR);
200 CASE_READ_MSR(CSTAR);
201 CASE_READ_MSR(SYSCALL_MASK);
202 default:
203 return 0;
204 }
205 HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n", msr_content);
206 regs->eax = msr_content & 0xffffffff;
207 regs->edx = msr_content >> 32;
208 return 1;
209 }
211 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
212 {
213 u64 msr_content = regs->eax | ((u64)regs->edx << 32);
214 struct vcpu *vc = current;
215 struct vmx_msr_state * msr = &vc->arch.hvm_vmx.msr_content;
216 struct vmx_msr_state * host_state =
217 &percpu_msr[smp_processor_id()];
219 HVM_DBG_LOG(DBG_LEVEL_1, " mode_do_msr_write msr %lx msr_content %lx\n",
220 regs->ecx, msr_content);
222 switch (regs->ecx){
223 case MSR_EFER:
224 if ((msr_content & EFER_LME) ^
225 test_bit(VMX_CPU_STATE_LME_ENABLED,
226 &vc->arch.hvm_vmx.cpu_state)){
227 if (test_bit(VMX_CPU_STATE_PG_ENABLED,
228 &vc->arch.hvm_vmx.cpu_state) ||
229 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
230 &vc->arch.hvm_vmx.cpu_state)){
231 vmx_inject_exception(vc, TRAP_gp_fault, 0);
232 }
233 }
234 if (msr_content & EFER_LME)
235 set_bit(VMX_CPU_STATE_LME_ENABLED,
236 &vc->arch.hvm_vmx.cpu_state);
237 /* No update for LME/LMA since it have no effect */
238 msr->msr_items[VMX_INDEX_MSR_EFER] =
239 msr_content;
240 if (msr_content & ~(EFER_LME | EFER_LMA)){
241 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
242 if (!test_bit(VMX_INDEX_MSR_EFER, &msr->flags)){
243 rdmsrl(MSR_EFER,
244 host_state->msr_items[VMX_INDEX_MSR_EFER]);
245 set_bit(VMX_INDEX_MSR_EFER, &host_state->flags);
246 set_bit(VMX_INDEX_MSR_EFER, &msr->flags);
247 }
248 }
249 break;
251 case MSR_FS_BASE:
252 case MSR_GS_BASE:
253 if (!(VMX_LONG_GUEST(vc)))
254 domain_crash_synchronous();
255 if (!IS_CANO_ADDRESS(msr_content)){
256 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
257 vmx_inject_exception(vc, TRAP_gp_fault, 0);
258 }
259 if (regs->ecx == MSR_FS_BASE)
260 __vmwrite(GUEST_FS_BASE, msr_content);
261 else
262 __vmwrite(GUEST_GS_BASE, msr_content);
263 break;
265 case MSR_SHADOW_GS_BASE:
266 if (!(VMX_LONG_GUEST(vc)))
267 domain_crash_synchronous();
268 vc->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
269 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
270 break;
272 CASE_WRITE_MSR(STAR);
273 CASE_WRITE_MSR(LSTAR);
274 CASE_WRITE_MSR(CSTAR);
275 CASE_WRITE_MSR(SYSCALL_MASK);
276 default:
277 return 0;
278 }
279 return 1;
280 }
282 void
283 vmx_restore_msrs(struct vcpu *v)
284 {
285 int i = 0;
286 struct vmx_msr_state *guest_state;
287 struct vmx_msr_state *host_state;
288 unsigned long guest_flags ;
290 guest_state = &v->arch.hvm_vmx.msr_content;;
291 host_state = &percpu_msr[smp_processor_id()];
293 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
294 guest_flags = guest_state->flags;
295 if (!guest_flags)
296 return;
298 while (guest_flags){
299 i = find_first_set_bit(guest_flags);
301 HVM_DBG_LOG(DBG_LEVEL_2,
302 "restore guest's index %d msr %lx with %lx\n",
303 i, (unsigned long) msr_data_index[i], (unsigned long) guest_state->msr_items[i]);
304 set_bit(i, &host_state->flags);
305 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
306 clear_bit(i, &guest_flags);
307 }
308 }
309 #else /* __i386__ */
310 #define vmx_save_init_msrs() ((void)0)
312 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs){
313 return 0;
314 }
315 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs){
316 return 0;
317 }
318 #endif
320 void stop_vmx(void)
321 {
322 if (read_cr4() & X86_CR4_VMXE)
323 __vmxoff();
324 }
326 int vmx_initialize_guest_resources(struct vcpu *v)
327 {
328 vmx_final_setup_guest(v);
329 return 1;
330 }
332 int vmx_relinquish_guest_resources(struct vcpu *v)
333 {
334 vmx_relinquish_resources(v);
335 return 1;
336 }
338 void vmx_migrate_timers(struct vcpu *v)
339 {
340 struct hvm_virpit *vpit = &(v->domain->arch.hvm_domain.vpit);
342 migrate_timer(&vpit->pit_timer, v->processor);
343 migrate_timer(&v->arch.hvm_vmx.hlt_timer, v->processor);
344 if ( hvm_apic_support(v->domain) && VLAPIC(v))
345 migrate_timer(&(VLAPIC(v)->vlapic_timer), v->processor);
346 }
348 void vmx_store_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
349 {
350 #if defined (__x86_64__)
351 __vmread(GUEST_RFLAGS, &regs->rflags);
352 __vmread(GUEST_SS_SELECTOR, &regs->ss);
353 __vmread(GUEST_CS_SELECTOR, &regs->cs);
354 __vmread(GUEST_DS_SELECTOR, &regs->ds);
355 __vmread(GUEST_ES_SELECTOR, &regs->es);
356 __vmread(GUEST_GS_SELECTOR, &regs->gs);
357 __vmread(GUEST_FS_SELECTOR, &regs->fs);
358 __vmread(GUEST_RIP, &regs->rip);
359 __vmread(GUEST_RSP, &regs->rsp);
360 #elif defined (__i386__)
361 __vmread(GUEST_RFLAGS, &regs->eflags);
362 __vmread(GUEST_SS_SELECTOR, &regs->ss);
363 __vmread(GUEST_CS_SELECTOR, &regs->cs);
364 __vmread(GUEST_DS_SELECTOR, &regs->ds);
365 __vmread(GUEST_ES_SELECTOR, &regs->es);
366 __vmread(GUEST_GS_SELECTOR, &regs->gs);
367 __vmread(GUEST_FS_SELECTOR, &regs->fs);
368 __vmread(GUEST_RIP, &regs->eip);
369 __vmread(GUEST_RSP, &regs->esp);
370 #else
371 #error Unsupported architecture
372 #endif
373 }
375 void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
376 {
377 #if defined (__x86_64__)
378 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
379 __vmwrite(GUEST_RSP, regs->rsp);
381 __vmwrite(GUEST_RFLAGS, regs->rflags);
382 if (regs->rflags & EF_TF)
383 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
384 else
385 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
387 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
388 __vmwrite(GUEST_RIP, regs->rip);
389 #elif defined (__i386__)
390 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
391 __vmwrite(GUEST_RSP, regs->esp);
393 __vmwrite(GUEST_RFLAGS, regs->eflags);
394 if (regs->eflags & EF_TF)
395 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
396 else
397 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
399 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
400 __vmwrite(GUEST_RIP, regs->eip);
401 #else
402 #error Unsupported architecture
403 #endif
404 }
406 void vmx_store_cpu_guest_ctrl_regs(struct vcpu *v, unsigned long crs[8])
407 {
408 __vmread(CR0_READ_SHADOW, &crs[0]);
409 __vmread(GUEST_CR3, &crs[3]);
410 __vmread(CR4_READ_SHADOW, &crs[4]);
411 }
413 void vmx_modify_guest_state(struct vcpu *v)
414 {
415 modify_vmcs(&v->arch.hvm_vmx, &v->arch.guest_context.user_regs);
416 }
418 int vmx_realmode(struct vcpu *v)
419 {
420 unsigned long rflags;
422 __vmread(GUEST_RFLAGS, &rflags);
423 return rflags & X86_EFLAGS_VM;
424 }
426 int vmx_instruction_length(struct vcpu *v)
427 {
428 unsigned long inst_len;
430 if (__vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len))
431 return 0;
432 return inst_len;
433 }
435 unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
436 {
437 switch ( num )
438 {
439 case 0:
440 return v->arch.hvm_vmx.cpu_cr0;
441 case 2:
442 return v->arch.hvm_vmx.cpu_cr2;
443 case 3:
444 return v->arch.hvm_vmx.cpu_cr3;
445 default:
446 BUG();
447 }
448 return 0; /* dummy */
449 }
451 void do_nmi(struct cpu_user_regs *);
453 static int check_vmx_controls(ctrls, msr)
454 {
455 u32 vmx_msr_low, vmx_msr_high;
457 rdmsr(msr, vmx_msr_low, vmx_msr_high);
458 if (ctrls < vmx_msr_low || ctrls > vmx_msr_high) {
459 printk("Insufficient VMX capability 0x%x, "
460 "msr=0x%x,low=0x%8x,high=0x%x\n",
461 ctrls, msr, vmx_msr_low, vmx_msr_high);
462 return 0;
463 }
464 return 1;
465 }
467 int start_vmx(void)
468 {
469 struct vmcs_struct *vmcs;
470 u32 ecx;
471 u32 eax, edx;
472 u64 phys_vmcs; /* debugging */
474 /*
475 * Xen does not fill x86_capability words except 0.
476 */
477 ecx = cpuid_ecx(1);
478 boot_cpu_data.x86_capability[4] = ecx;
480 if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
481 return 0;
483 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
485 if (eax & IA32_FEATURE_CONTROL_MSR_LOCK) {
486 if ((eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0) {
487 printk("VMX disabled by Feature Control MSR.\n");
488 return 0;
489 }
490 }
491 else {
492 wrmsr(IA32_FEATURE_CONTROL_MSR,
493 IA32_FEATURE_CONTROL_MSR_LOCK |
494 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
495 }
497 if (!check_vmx_controls(MONITOR_PIN_BASED_EXEC_CONTROLS,
498 MSR_IA32_VMX_PINBASED_CTLS_MSR))
499 return 0;
500 if (!check_vmx_controls(MONITOR_CPU_BASED_EXEC_CONTROLS,
501 MSR_IA32_VMX_PROCBASED_CTLS_MSR))
502 return 0;
503 if (!check_vmx_controls(MONITOR_VM_EXIT_CONTROLS,
504 MSR_IA32_VMX_EXIT_CTLS_MSR))
505 return 0;
506 if (!check_vmx_controls(MONITOR_VM_ENTRY_CONTROLS,
507 MSR_IA32_VMX_ENTRY_CTLS_MSR))
508 return 0;
510 set_in_cr4(X86_CR4_VMXE); /* Enable VMXE */
512 if (!(vmcs = alloc_vmcs())) {
513 printk("Failed to allocate VMCS\n");
514 return 0;
515 }
517 phys_vmcs = (u64) virt_to_maddr(vmcs);
519 if (!(__vmxon(phys_vmcs))) {
520 printk("VMXON is done\n");
521 }
523 vmx_save_init_msrs();
525 /* Setup HVM interfaces */
526 hvm_funcs.disable = stop_vmx;
528 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
529 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
531 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
532 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
534 #ifdef __x86_64__
535 hvm_funcs.save_segments = vmx_save_segments;
536 hvm_funcs.load_msrs = vmx_load_msrs;
537 hvm_funcs.restore_msrs = vmx_restore_msrs;
538 #endif
540 hvm_funcs.store_cpu_guest_ctrl_regs = vmx_store_cpu_guest_ctrl_regs;
541 hvm_funcs.modify_guest_state = vmx_modify_guest_state;
543 hvm_funcs.realmode = vmx_realmode;
544 hvm_funcs.paging_enabled = vmx_paging_enabled;
545 hvm_funcs.instruction_length = vmx_instruction_length;
546 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
548 hvm_enabled = 1;
550 return 1;
551 }
553 /*
554 * Not all cases receive valid value in the VM-exit instruction length field.
555 */
556 #define __get_instruction_length(len) \
557 __vmread(VM_EXIT_INSTRUCTION_LEN, &(len)); \
558 if ((len) < 1 || (len) > 15) \
559 __hvm_bug(&regs);
561 static void inline __update_guest_eip(unsigned long inst_len)
562 {
563 unsigned long current_eip;
565 __vmread(GUEST_RIP, &current_eip);
566 __vmwrite(GUEST_RIP, current_eip + inst_len);
567 }
570 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
571 {
572 unsigned long gpa; /* FIXME: PAE */
573 int result;
575 #if 0 /* keep for debugging */
576 {
577 unsigned long eip;
579 __vmread(GUEST_RIP, &eip);
580 HVM_DBG_LOG(DBG_LEVEL_VMMU,
581 "vmx_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
582 va, eip, (unsigned long)regs->error_code);
583 }
584 #endif
586 if ( !vmx_paging_enabled(current) )
587 {
588 /* construct 1-to-1 direct mapping */
589 if ( shadow_direct_map_fault(va, regs) )
590 return 1;
592 handle_mmio(va, va);
593 TRACE_VMEXIT (2,2);
594 return 1;
595 }
596 gpa = gva_to_gpa(va);
598 /* Use 1:1 page table to identify MMIO address space */
599 if ( mmio_space(gpa) ){
600 struct vcpu *v = current;
601 /* No support for APIC */
602 if (!hvm_apic_support(v->domain) && gpa >= 0xFEC00000) {
603 u32 inst_len;
604 __vmread(VM_EXIT_INSTRUCTION_LEN, &(inst_len));
605 __update_guest_eip(inst_len);
606 return 1;
607 }
608 TRACE_VMEXIT (2,2);
609 handle_mmio(va, gpa);
610 return 1;
611 }
613 result = shadow_fault(va, regs);
614 TRACE_VMEXIT (2,result);
615 #if 0
616 if ( !result )
617 {
618 __vmread(GUEST_RIP, &eip);
619 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
620 }
621 #endif
623 return result;
624 }
626 static void vmx_do_no_device_fault(void)
627 {
628 unsigned long cr0;
629 struct vcpu *v = current;
631 setup_fpu(current);
632 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
634 /* Disable TS in guest CR0 unless the guest wants the exception too. */
635 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
636 if ( !(cr0 & X86_CR0_TS) )
637 {
638 __vmread_vcpu(v, GUEST_CR0, &cr0);
639 cr0 &= ~X86_CR0_TS;
640 __vmwrite(GUEST_CR0, cr0);
641 }
642 }
644 /* Reserved bits: [31:15], [12:11], [9], [6], [2:1] */
645 #define VMX_VCPU_CPUID_L1_RESERVED 0xffff9a46
647 static void vmx_vmexit_do_cpuid(unsigned long input, struct cpu_user_regs *regs)
648 {
649 unsigned int eax, ebx, ecx, edx;
650 unsigned long eip;
651 struct vcpu *v = current;
653 __vmread(GUEST_RIP, &eip);
655 HVM_DBG_LOG(DBG_LEVEL_1,
656 "do_cpuid: (eax) %lx, (ebx) %lx, (ecx) %lx, (edx) %lx,"
657 " (esi) %lx, (edi) %lx",
658 (unsigned long)regs->eax, (unsigned long)regs->ebx,
659 (unsigned long)regs->ecx, (unsigned long)regs->edx,
660 (unsigned long)regs->esi, (unsigned long)regs->edi);
662 cpuid(input, &eax, &ebx, &ecx, &edx);
664 if ( input == 1 )
665 {
666 if ( hvm_apic_support(v->domain) &&
667 !vlapic_global_enabled((VLAPIC(v))) )
668 clear_bit(X86_FEATURE_APIC, &edx);
670 #if CONFIG_PAGING_LEVELS < 3
671 clear_bit(X86_FEATURE_PAE, &edx);
672 clear_bit(X86_FEATURE_PSE, &edx);
673 clear_bit(X86_FEATURE_PSE36, &edx);
674 #else
675 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L2 )
676 {
677 if ( !v->domain->arch.hvm_domain.pae_enabled )
678 clear_bit(X86_FEATURE_PAE, &edx);
679 clear_bit(X86_FEATURE_PSE, &edx);
680 clear_bit(X86_FEATURE_PSE36, &edx);
681 }
682 #endif
684 /* Unsupportable for virtualised CPUs. */
685 ecx &= ~VMX_VCPU_CPUID_L1_RESERVED; /* mask off reserved bits */
686 clear_bit(X86_FEATURE_VMXE & 31, &ecx);
687 clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
688 }
689 #ifdef __i386__
690 else if ( input == 0x80000001 )
691 {
692 /* Mask feature for Intel ia32e or AMD long mode. */
693 clear_bit(X86_FEATURE_LM & 31, &edx);
694 }
695 #endif
697 regs->eax = (unsigned long) eax;
698 regs->ebx = (unsigned long) ebx;
699 regs->ecx = (unsigned long) ecx;
700 regs->edx = (unsigned long) edx;
702 HVM_DBG_LOG(DBG_LEVEL_1,
703 "vmx_vmexit_do_cpuid: eip: %lx, input: %lx, out:eax=%x, ebx=%x, ecx=%x, edx=%x",
704 eip, input, eax, ebx, ecx, edx);
706 }
708 #define CASE_GET_REG_P(REG, reg) \
709 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
711 static void vmx_dr_access (unsigned long exit_qualification, struct cpu_user_regs *regs)
712 {
713 unsigned int reg;
714 unsigned long *reg_p = 0;
715 struct vcpu *v = current;
716 unsigned long eip;
718 __vmread(GUEST_RIP, &eip);
720 reg = exit_qualification & DEBUG_REG_ACCESS_NUM;
722 HVM_DBG_LOG(DBG_LEVEL_1,
723 "vmx_dr_access : eip=%lx, reg=%d, exit_qualification = %lx",
724 eip, reg, exit_qualification);
726 switch(exit_qualification & DEBUG_REG_ACCESS_REG) {
727 CASE_GET_REG_P(EAX, eax);
728 CASE_GET_REG_P(ECX, ecx);
729 CASE_GET_REG_P(EDX, edx);
730 CASE_GET_REG_P(EBX, ebx);
731 CASE_GET_REG_P(EBP, ebp);
732 CASE_GET_REG_P(ESI, esi);
733 CASE_GET_REG_P(EDI, edi);
734 case REG_ESP:
735 break;
736 default:
737 __hvm_bug(regs);
738 }
740 switch (exit_qualification & DEBUG_REG_ACCESS_TYPE) {
741 case TYPE_MOV_TO_DR:
742 /* don't need to check the range */
743 if (reg != REG_ESP)
744 v->arch.guest_context.debugreg[reg] = *reg_p;
745 else {
746 unsigned long value;
747 __vmread(GUEST_RSP, &value);
748 v->arch.guest_context.debugreg[reg] = value;
749 }
750 break;
751 case TYPE_MOV_FROM_DR:
752 if (reg != REG_ESP)
753 *reg_p = v->arch.guest_context.debugreg[reg];
754 else {
755 __vmwrite(GUEST_RSP, v->arch.guest_context.debugreg[reg]);
756 }
757 break;
758 }
759 }
761 /*
762 * Invalidate the TLB for va. Invalidate the shadow page corresponding
763 * the address va.
764 */
765 static void vmx_vmexit_do_invlpg(unsigned long va)
766 {
767 unsigned long eip;
768 struct vcpu *v = current;
770 __vmread(GUEST_RIP, &eip);
772 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
773 eip, va);
775 /*
776 * We do the safest things first, then try to update the shadow
777 * copying from guest
778 */
779 shadow_invlpg(v, va);
780 }
782 static int check_for_null_selector(unsigned long eip)
783 {
784 unsigned char inst[MAX_INST_LEN];
785 unsigned long sel;
786 int i, inst_len;
787 int inst_copy_from_guest(unsigned char *, unsigned long, int);
789 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
790 memset(inst, 0, MAX_INST_LEN);
791 if (inst_copy_from_guest(inst, eip, inst_len) != inst_len) {
792 printf("check_for_null_selector: get guest instruction failed\n");
793 domain_crash_synchronous();
794 }
796 for (i = 0; i < inst_len; i++) {
797 switch (inst[i]) {
798 case 0xf3: /* REPZ */
799 case 0xf2: /* REPNZ */
800 case 0xf0: /* LOCK */
801 case 0x66: /* data32 */
802 case 0x67: /* addr32 */
803 continue;
804 case 0x2e: /* CS */
805 __vmread(GUEST_CS_SELECTOR, &sel);
806 break;
807 case 0x36: /* SS */
808 __vmread(GUEST_SS_SELECTOR, &sel);
809 break;
810 case 0x26: /* ES */
811 __vmread(GUEST_ES_SELECTOR, &sel);
812 break;
813 case 0x64: /* FS */
814 __vmread(GUEST_FS_SELECTOR, &sel);
815 break;
816 case 0x65: /* GS */
817 __vmread(GUEST_GS_SELECTOR, &sel);
818 break;
819 case 0x3e: /* DS */
820 /* FALLTHROUGH */
821 default:
822 /* DS is the default */
823 __vmread(GUEST_DS_SELECTOR, &sel);
824 }
825 return sel == 0 ? 1 : 0;
826 }
828 return 0;
829 }
831 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
832 unsigned long count, int size, long value,
833 int dir, int pvalid);
835 static void vmx_io_instruction(struct cpu_user_regs *regs,
836 unsigned long exit_qualification, unsigned long inst_len)
837 {
838 struct mmio_op *mmio_opp;
839 unsigned long eip, cs, eflags;
840 unsigned long port, size, dir;
841 int vm86;
843 mmio_opp = &current->arch.hvm_vcpu.mmio_op;
844 mmio_opp->instr = INSTR_PIO;
845 mmio_opp->flags = 0;
847 __vmread(GUEST_RIP, &eip);
848 __vmread(GUEST_CS_SELECTOR, &cs);
849 __vmread(GUEST_RFLAGS, &eflags);
850 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
852 HVM_DBG_LOG(DBG_LEVEL_1,
853 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
854 "exit_qualification = %lx",
855 vm86, cs, eip, exit_qualification);
857 if (test_bit(6, &exit_qualification))
858 port = (exit_qualification >> 16) & 0xFFFF;
859 else
860 port = regs->edx & 0xffff;
861 TRACE_VMEXIT(2, port);
862 size = (exit_qualification & 7) + 1;
863 dir = test_bit(3, &exit_qualification); /* direction */
865 if (test_bit(4, &exit_qualification)) { /* string instruction */
866 unsigned long addr, count = 1;
867 int sign = regs->eflags & EF_DF ? -1 : 1;
869 __vmread(GUEST_LINEAR_ADDRESS, &addr);
871 /*
872 * In protected mode, guest linear address is invalid if the
873 * selector is null.
874 */
875 if (!vm86 && check_for_null_selector(eip))
876 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
878 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
879 mmio_opp->flags |= REPZ;
880 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
881 }
883 /*
884 * Handle string pio instructions that cross pages or that
885 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
886 */
887 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
888 unsigned long value = 0;
890 mmio_opp->flags |= OVERLAP;
891 if (dir == IOREQ_WRITE)
892 hvm_copy(&value, addr, size, HVM_COPY_IN);
893 send_pio_req(regs, port, 1, size, value, dir, 0);
894 } else {
895 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
896 if (sign > 0)
897 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
898 else
899 count = (addr & ~PAGE_MASK) / size;
900 } else
901 __update_guest_eip(inst_len);
903 send_pio_req(regs, port, count, size, addr, dir, 1);
904 }
905 } else {
906 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
907 hvm_print_line(current, regs->eax); /* guest debug output */
909 __update_guest_eip(inst_len);
910 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
911 }
912 }
914 int
915 vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
916 {
917 unsigned long inst_len;
918 int error = 0;
920 error |= __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
921 error |= __vmread(GUEST_RIP, &c->eip);
922 c->eip += inst_len; /* skip transition instruction */
923 error |= __vmread(GUEST_RSP, &c->esp);
924 error |= __vmread(GUEST_RFLAGS, &c->eflags);
926 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
927 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
928 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
930 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
931 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
933 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
934 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
936 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
937 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
938 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
939 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
941 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
942 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
943 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
944 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
946 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
947 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
948 error |= __vmread(GUEST_ES_BASE, &c->es_base);
949 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
951 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
952 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
953 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
954 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
956 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
957 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
958 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
959 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
961 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
962 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
963 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
964 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
966 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
967 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
968 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
969 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
971 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
972 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
973 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
974 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
976 return !error;
977 }
979 int
980 vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
981 {
982 unsigned long mfn, old_cr4, old_base_mfn;
983 int error = 0;
985 error |= __vmwrite(GUEST_RIP, c->eip);
986 error |= __vmwrite(GUEST_RSP, c->esp);
987 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
989 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
991 if (!vmx_paging_enabled(v)) {
992 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
993 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
994 goto skip_cr3;
995 }
997 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
998 /*
999 * This is simple TLB flush, implying the guest has
1000 * removed some translation or changed page attributes.
1001 * We simply invalidate the shadow.
1002 */
1003 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1004 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1005 printk("Invalid CR3 value=%x", c->cr3);
1006 domain_crash_synchronous();
1007 return 0;
1009 shadow_sync_all(v->domain);
1010 } else {
1011 /*
1012 * If different, make a shadow. Check if the PDBR is valid
1013 * first.
1014 */
1015 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1016 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1017 printk("Invalid CR3 value=%x", c->cr3);
1018 domain_crash_synchronous();
1019 return 0;
1021 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1022 if(!get_page(mfn_to_page(mfn), v->domain))
1023 return 0;
1024 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1025 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1026 if (old_base_mfn)
1027 put_page(mfn_to_page(old_base_mfn));
1028 /*
1029 * arch.shadow_table should now hold the next CR3 for shadow
1030 */
1031 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1032 update_pagetables(v);
1033 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1034 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1037 skip_cr3:
1039 error |= __vmread(CR4_READ_SHADOW, &old_cr4);
1040 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1041 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1043 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1044 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1046 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1047 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1049 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1050 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1051 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1052 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1054 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1055 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1056 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1057 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1059 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1060 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1061 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1062 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1064 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1065 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1066 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1067 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1069 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1070 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1071 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1072 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1074 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1075 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1076 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1077 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1079 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1080 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1081 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1082 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1084 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1085 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1086 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1087 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1089 return !error;
1092 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1094 int
1095 vmx_assist(struct vcpu *v, int mode)
1097 struct vmx_assist_context c;
1098 u32 magic;
1099 u32 cp;
1101 /* make sure vmxassist exists (this is not an error) */
1102 if (!hvm_copy(&magic, VMXASSIST_MAGIC_OFFSET, sizeof(magic), HVM_COPY_IN))
1103 return 0;
1104 if (magic != VMXASSIST_MAGIC)
1105 return 0;
1107 switch (mode) {
1108 /*
1109 * Transfer control to vmxassist.
1110 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1111 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1112 * by vmxassist and will transfer control to it.
1113 */
1114 case VMX_ASSIST_INVOKE:
1115 /* save the old context */
1116 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1117 goto error;
1118 if (cp != 0) {
1119 if (!vmx_world_save(v, &c))
1120 goto error;
1121 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_OUT))
1122 goto error;
1125 /* restore the new context, this should activate vmxassist */
1126 if (!hvm_copy(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp), HVM_COPY_IN))
1127 goto error;
1128 if (cp != 0) {
1129 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1130 goto error;
1131 if (!vmx_world_restore(v, &c))
1132 goto error;
1133 return 1;
1135 break;
1137 /*
1138 * Restore the VMXASSIST_OLD_CONTEXT that was saved by VMX_ASSIST_INVOKE
1139 * above.
1140 */
1141 case VMX_ASSIST_RESTORE:
1142 /* save the old context */
1143 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1144 goto error;
1145 if (cp != 0) {
1146 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1147 goto error;
1148 if (!vmx_world_restore(v, &c))
1149 goto error;
1150 return 1;
1152 break;
1155 error:
1156 printf("Failed to transfer to vmxassist\n");
1157 domain_crash_synchronous();
1158 return 0;
1161 static int vmx_set_cr0(unsigned long value)
1163 struct vcpu *v = current;
1164 unsigned long mfn;
1165 unsigned long eip;
1166 int paging_enabled;
1167 unsigned long vm_entry_value;
1168 unsigned long old_cr0;
1170 /*
1171 * CR0: We don't want to lose PE and PG.
1172 */
1173 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1174 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1176 /* TS cleared? Then initialise FPU now. */
1177 if ( !(value & X86_CR0_TS) )
1179 setup_fpu(v);
1180 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1183 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1184 __vmwrite(CR0_READ_SHADOW, value);
1186 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1188 if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
1190 unsigned long cr4;
1192 /*
1193 * Trying to enable guest paging.
1194 * The guest CR3 must be pointing to the guest physical.
1195 */
1196 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1197 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1198 !get_page(mfn_to_page(mfn), v->domain) )
1200 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1201 domain_crash_synchronous(); /* need to take a clean path */
1204 #if defined(__x86_64__)
1205 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1206 &v->arch.hvm_vmx.cpu_state) &&
1207 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
1208 &v->arch.hvm_vmx.cpu_state) )
1210 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enabled\n");
1211 vmx_inject_exception(v, TRAP_gp_fault, 0);
1214 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1215 &v->arch.hvm_vmx.cpu_state) )
1217 /* Here the PAE is should be opened */
1218 HVM_DBG_LOG(DBG_LEVEL_1, "Enable long mode\n");
1219 set_bit(VMX_CPU_STATE_LMA_ENABLED,
1220 &v->arch.hvm_vmx.cpu_state);
1222 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1223 vm_entry_value |= VM_ENTRY_CONTROLS_IA32E_MODE;
1224 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1226 if ( !shadow_set_guest_paging_levels(v->domain, 4) ) {
1227 printk("Unsupported guest paging levels\n");
1228 domain_crash_synchronous(); /* need to take a clean path */
1231 else
1232 #endif /* __x86_64__ */
1234 #if CONFIG_PAGING_LEVELS >= 3
1235 if ( !shadow_set_guest_paging_levels(v->domain, 2) ) {
1236 printk("Unsupported guest paging levels\n");
1237 domain_crash_synchronous(); /* need to take a clean path */
1239 #endif
1242 /* update CR4's PAE if needed */
1243 __vmread(GUEST_CR4, &cr4);
1244 if ( (!(cr4 & X86_CR4_PAE)) &&
1245 test_bit(VMX_CPU_STATE_PAE_ENABLED,
1246 &v->arch.hvm_vmx.cpu_state) )
1248 HVM_DBG_LOG(DBG_LEVEL_1, "enable PAE in cr4\n");
1249 __vmwrite(GUEST_CR4, cr4 | X86_CR4_PAE);
1252 /*
1253 * Now arch.guest_table points to machine physical.
1254 */
1255 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1256 update_pagetables(v);
1258 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1259 (unsigned long) (mfn << PAGE_SHIFT));
1261 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1262 /*
1263 * arch->shadow_table should hold the next CR3 for shadow
1264 */
1265 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1266 v->arch.hvm_vmx.cpu_cr3, mfn);
1269 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1270 if ( v->arch.hvm_vmx.cpu_cr3 ) {
1271 put_page(mfn_to_page(get_mfn_from_gpfn(
1272 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1273 v->arch.guest_table = mk_pagetable(0);
1276 /*
1277 * VMX does not implement real-mode virtualization. We emulate
1278 * real-mode by performing a world switch to VMXAssist whenever
1279 * a partition disables the CR0.PE bit.
1280 */
1281 if ( (value & X86_CR0_PE) == 0 )
1283 if ( value & X86_CR0_PG ) {
1284 /* inject GP here */
1285 vmx_inject_exception(v, TRAP_gp_fault, 0);
1286 return 0;
1287 } else {
1288 /*
1289 * Disable paging here.
1290 * Same to PE == 1 && PG == 0
1291 */
1292 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED,
1293 &v->arch.hvm_vmx.cpu_state) )
1295 clear_bit(VMX_CPU_STATE_LMA_ENABLED,
1296 &v->arch.hvm_vmx.cpu_state);
1297 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1298 vm_entry_value &= ~VM_ENTRY_CONTROLS_IA32E_MODE;
1299 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1303 clear_all_shadow_status(v->domain);
1304 if ( vmx_assist(v, VMX_ASSIST_INVOKE) ) {
1305 set_bit(VMX_CPU_STATE_ASSIST_ENABLED, &v->arch.hvm_vmx.cpu_state);
1306 __vmread(GUEST_RIP, &eip);
1307 HVM_DBG_LOG(DBG_LEVEL_1,
1308 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1309 return 0; /* do not update eip! */
1311 } else if ( test_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1312 &v->arch.hvm_vmx.cpu_state) )
1314 __vmread(GUEST_RIP, &eip);
1315 HVM_DBG_LOG(DBG_LEVEL_1,
1316 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1317 if ( vmx_assist(v, VMX_ASSIST_RESTORE) )
1319 clear_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1320 &v->arch.hvm_vmx.cpu_state);
1321 __vmread(GUEST_RIP, &eip);
1322 HVM_DBG_LOG(DBG_LEVEL_1,
1323 "Restoring to %%eip 0x%lx\n", eip);
1324 return 0; /* do not update eip! */
1328 return 1;
1331 #define CASE_GET_REG(REG, reg) \
1332 case REG_ ## REG: value = regs->reg; break
1334 #define CASE_EXTEND_SET_REG \
1335 CASE_EXTEND_REG(S)
1336 #define CASE_EXTEND_GET_REG \
1337 CASE_EXTEND_REG(G)
1339 #ifdef __i386__
1340 #define CASE_EXTEND_REG(T)
1341 #else
1342 #define CASE_EXTEND_REG(T) \
1343 CASE_ ## T ## ET_REG(R8, r8); \
1344 CASE_ ## T ## ET_REG(R9, r9); \
1345 CASE_ ## T ## ET_REG(R10, r10); \
1346 CASE_ ## T ## ET_REG(R11, r11); \
1347 CASE_ ## T ## ET_REG(R12, r12); \
1348 CASE_ ## T ## ET_REG(R13, r13); \
1349 CASE_ ## T ## ET_REG(R14, r14); \
1350 CASE_ ## T ## ET_REG(R15, r15);
1351 #endif
1354 /*
1355 * Write to control registers
1356 */
1357 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1359 unsigned long value;
1360 unsigned long old_cr;
1361 struct vcpu *v = current;
1363 switch (gp) {
1364 CASE_GET_REG(EAX, eax);
1365 CASE_GET_REG(ECX, ecx);
1366 CASE_GET_REG(EDX, edx);
1367 CASE_GET_REG(EBX, ebx);
1368 CASE_GET_REG(EBP, ebp);
1369 CASE_GET_REG(ESI, esi);
1370 CASE_GET_REG(EDI, edi);
1371 CASE_EXTEND_GET_REG
1372 case REG_ESP:
1373 __vmread(GUEST_RSP, &value);
1374 break;
1375 default:
1376 printk("invalid gp: %d\n", gp);
1377 __hvm_bug(regs);
1380 HVM_DBG_LOG(DBG_LEVEL_1, "mov_to_cr: CR%d, value = %lx,", cr, value);
1381 HVM_DBG_LOG(DBG_LEVEL_1, "current = %lx,", (unsigned long) current);
1383 switch(cr) {
1384 case 0:
1386 return vmx_set_cr0(value);
1388 case 3:
1390 unsigned long old_base_mfn, mfn;
1392 /*
1393 * If paging is not enabled yet, simply copy the value to CR3.
1394 */
1395 if (!vmx_paging_enabled(v)) {
1396 v->arch.hvm_vmx.cpu_cr3 = value;
1397 break;
1400 /*
1401 * We make a new one if the shadow does not exist.
1402 */
1403 if (value == v->arch.hvm_vmx.cpu_cr3) {
1404 /*
1405 * This is simple TLB flush, implying the guest has
1406 * removed some translation or changed page attributes.
1407 * We simply invalidate the shadow.
1408 */
1409 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1410 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1411 __hvm_bug(regs);
1412 shadow_sync_all(v->domain);
1413 } else {
1414 /*
1415 * If different, make a shadow. Check if the PDBR is valid
1416 * first.
1417 */
1418 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1419 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1420 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1421 !get_page(mfn_to_page(mfn), v->domain) )
1423 printk("Invalid CR3 value=%lx", value);
1424 domain_crash_synchronous(); /* need to take a clean path */
1426 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1427 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1428 if (old_base_mfn)
1429 put_page(mfn_to_page(old_base_mfn));
1430 /*
1431 * arch.shadow_table should now hold the next CR3 for shadow
1432 */
1433 #if CONFIG_PAGING_LEVELS >= 3
1434 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L3 )
1435 shadow_sync_all(v->domain);
1436 #endif
1438 v->arch.hvm_vmx.cpu_cr3 = value;
1439 update_pagetables(v);
1440 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1441 value);
1442 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1444 break;
1446 case 4: /* CR4 */
1448 __vmread(CR4_READ_SHADOW, &old_cr);
1450 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1452 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1454 if ( vmx_pgbit_test(v) )
1456 /* The guest is 32 bit. */
1457 #if CONFIG_PAGING_LEVELS >= 4
1458 unsigned long mfn, old_base_mfn;
1460 if( !shadow_set_guest_paging_levels(v->domain, 3) )
1462 printk("Unsupported guest paging levels\n");
1463 domain_crash_synchronous(); /* need to take a clean path */
1466 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1467 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1468 !get_page(mfn_to_page(mfn), v->domain) )
1470 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1471 domain_crash_synchronous(); /* need to take a clean path */
1474 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1475 if ( old_base_mfn )
1476 put_page(mfn_to_page(old_base_mfn));
1478 /*
1479 * Now arch.guest_table points to machine physical.
1480 */
1482 v->arch.guest_table = mk_pagetable((u64)mfn << PAGE_SHIFT);
1483 update_pagetables(v);
1485 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1486 (unsigned long) (mfn << PAGE_SHIFT));
1488 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1490 /*
1491 * arch->shadow_table should hold the next CR3 for shadow
1492 */
1494 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1495 v->arch.hvm_vmx.cpu_cr3, mfn);
1496 #endif
1498 else
1500 /* The guest is 64 bit. */
1501 #if CONFIG_PAGING_LEVELS >= 4
1502 if ( !shadow_set_guest_paging_levels(v->domain, 4) )
1504 printk("Unsupported guest paging levels\n");
1505 domain_crash_synchronous(); /* need to take a clean path */
1507 #endif
1510 else if ( value & X86_CR4_PAE )
1511 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1512 else
1514 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED, &v->arch.hvm_vmx.cpu_state) )
1515 vmx_inject_exception(v, TRAP_gp_fault, 0);
1517 clear_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1520 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1521 __vmwrite(CR4_READ_SHADOW, value);
1523 /*
1524 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1525 * all TLB entries except global entries.
1526 */
1527 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1528 shadow_sync_all(v->domain);
1530 break;
1532 default:
1533 printk("invalid cr: %d\n", gp);
1534 __hvm_bug(regs);
1537 return 1;
1540 #define CASE_SET_REG(REG, reg) \
1541 case REG_ ## REG: \
1542 regs->reg = value; \
1543 break
1545 /*
1546 * Read from control registers. CR0 and CR4 are read from the shadow.
1547 */
1548 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1550 unsigned long value;
1551 struct vcpu *v = current;
1553 if (cr != 3)
1554 __hvm_bug(regs);
1556 value = (unsigned long) v->arch.hvm_vmx.cpu_cr3;
1558 switch (gp) {
1559 CASE_SET_REG(EAX, eax);
1560 CASE_SET_REG(ECX, ecx);
1561 CASE_SET_REG(EDX, edx);
1562 CASE_SET_REG(EBX, ebx);
1563 CASE_SET_REG(EBP, ebp);
1564 CASE_SET_REG(ESI, esi);
1565 CASE_SET_REG(EDI, edi);
1566 CASE_EXTEND_SET_REG
1567 case REG_ESP:
1568 __vmwrite(GUEST_RSP, value);
1569 regs->esp = value;
1570 break;
1571 default:
1572 printk("invalid gp: %d\n", gp);
1573 __hvm_bug(regs);
1576 HVM_DBG_LOG(DBG_LEVEL_VMMU, "mov_from_cr: CR%d, value = %lx,", cr, value);
1579 static int vmx_cr_access(unsigned long exit_qualification, struct cpu_user_regs *regs)
1581 unsigned int gp, cr;
1582 unsigned long value;
1583 struct vcpu *v = current;
1585 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1586 case TYPE_MOV_TO_CR:
1587 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1588 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1589 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1590 TRACE_VMEXIT(2,cr);
1591 TRACE_VMEXIT(3,gp);
1592 return mov_to_cr(gp, cr, regs);
1593 case TYPE_MOV_FROM_CR:
1594 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1595 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1596 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1597 TRACE_VMEXIT(2,cr);
1598 TRACE_VMEXIT(3,gp);
1599 mov_from_cr(cr, gp, regs);
1600 break;
1601 case TYPE_CLTS:
1602 TRACE_VMEXIT(1,TYPE_CLTS);
1604 /* We initialise the FPU now, to avoid needing another vmexit. */
1605 setup_fpu(v);
1606 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1608 __vmread_vcpu(v, GUEST_CR0, &value);
1609 value &= ~X86_CR0_TS; /* clear TS */
1610 __vmwrite(GUEST_CR0, value);
1612 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1613 value &= ~X86_CR0_TS; /* clear TS */
1614 __vmwrite(CR0_READ_SHADOW, value);
1615 break;
1616 case TYPE_LMSW:
1617 TRACE_VMEXIT(1,TYPE_LMSW);
1618 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1619 value = (value & ~0xF) |
1620 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1621 return vmx_set_cr0(value);
1622 break;
1623 default:
1624 __hvm_bug(regs);
1625 break;
1627 return 1;
1630 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1632 u64 msr_content = 0;
1633 struct vcpu *v = current;
1635 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1636 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1637 (unsigned long)regs->edx);
1638 switch (regs->ecx) {
1639 case MSR_IA32_TIME_STAMP_COUNTER:
1641 struct hvm_virpit *vpit;
1643 rdtscll(msr_content);
1644 vpit = &(v->domain->arch.hvm_domain.vpit);
1645 msr_content += vpit->shift;
1646 break;
1648 case MSR_IA32_SYSENTER_CS:
1649 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1650 break;
1651 case MSR_IA32_SYSENTER_ESP:
1652 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1653 break;
1654 case MSR_IA32_SYSENTER_EIP:
1655 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1656 break;
1657 case MSR_IA32_APICBASE:
1658 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1659 break;
1660 default:
1661 if(long_mode_do_msr_read(regs))
1662 return;
1663 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1664 break;
1667 regs->eax = msr_content & 0xFFFFFFFF;
1668 regs->edx = msr_content >> 32;
1670 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1671 "ecx=%lx, eax=%lx, edx=%lx",
1672 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1673 (unsigned long)regs->edx);
1676 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1678 u64 msr_content;
1679 struct vcpu *v = current;
1681 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1682 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1683 (unsigned long)regs->edx);
1685 msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
1687 switch (regs->ecx) {
1688 case MSR_IA32_TIME_STAMP_COUNTER:
1690 struct hvm_virpit *vpit;
1691 u64 host_tsc, drift;
1693 rdtscll(host_tsc);
1694 vpit = &(v->domain->arch.hvm_domain.vpit);
1695 drift = v->arch.hvm_vmx.tsc_offset - vpit->shift;
1696 vpit->shift = msr_content - host_tsc;
1697 v->arch.hvm_vmx.tsc_offset = vpit->shift + drift;
1698 __vmwrite(TSC_OFFSET, vpit->shift);
1700 #if defined (__i386__)
1701 __vmwrite(TSC_OFFSET_HIGH, ((vpit->shift)>>32));
1702 #endif
1703 break;
1705 case MSR_IA32_SYSENTER_CS:
1706 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1707 break;
1708 case MSR_IA32_SYSENTER_ESP:
1709 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1710 break;
1711 case MSR_IA32_SYSENTER_EIP:
1712 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1713 break;
1714 case MSR_IA32_APICBASE:
1715 vlapic_msr_set(VLAPIC(v), msr_content);
1716 break;
1717 default:
1718 long_mode_do_msr_write(regs);
1719 break;
1722 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1723 "ecx=%lx, eax=%lx, edx=%lx",
1724 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1725 (unsigned long)regs->edx);
1728 /*
1729 * Need to use this exit to reschedule
1730 */
1731 void vmx_vmexit_do_hlt(void)
1733 struct vcpu *v=current;
1734 struct hvm_virpit *vpit = &(v->domain->arch.hvm_domain.vpit);
1735 s_time_t next_pit=-1,next_wakeup;
1737 if ( !v->vcpu_id )
1738 next_pit = get_pit_scheduled(v,vpit);
1739 next_wakeup = get_apictime_scheduled(v);
1740 if ( (next_pit != -1 && next_pit < next_wakeup) || next_wakeup == -1 )
1741 next_wakeup = next_pit;
1742 if ( next_wakeup != - 1 )
1743 set_timer(&current->arch.hvm_vmx.hlt_timer, next_wakeup);
1744 hvm_safe_block();
1747 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
1749 unsigned int vector;
1750 int error;
1752 asmlinkage void do_IRQ(struct cpu_user_regs *);
1753 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
1754 fastcall void smp_event_check_interrupt(void);
1755 fastcall void smp_invalidate_interrupt(void);
1756 fastcall void smp_call_function_interrupt(void);
1757 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
1758 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
1759 #ifdef CONFIG_X86_MCE_P4THERMAL
1760 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
1761 #endif
1763 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1764 && !(vector & INTR_INFO_VALID_MASK))
1765 __hvm_bug(regs);
1767 vector &= 0xff;
1768 local_irq_disable();
1770 switch(vector) {
1771 case LOCAL_TIMER_VECTOR:
1772 smp_apic_timer_interrupt(regs);
1773 break;
1774 case EVENT_CHECK_VECTOR:
1775 smp_event_check_interrupt();
1776 break;
1777 case INVALIDATE_TLB_VECTOR:
1778 smp_invalidate_interrupt();
1779 break;
1780 case CALL_FUNCTION_VECTOR:
1781 smp_call_function_interrupt();
1782 break;
1783 case SPURIOUS_APIC_VECTOR:
1784 smp_spurious_interrupt(regs);
1785 break;
1786 case ERROR_APIC_VECTOR:
1787 smp_error_interrupt(regs);
1788 break;
1789 #ifdef CONFIG_X86_MCE_P4THERMAL
1790 case THERMAL_APIC_VECTOR:
1791 smp_thermal_interrupt(regs);
1792 break;
1793 #endif
1794 default:
1795 regs->entry_vector = vector;
1796 do_IRQ(regs);
1797 break;
1801 #if defined (__x86_64__)
1802 void store_cpu_user_regs(struct cpu_user_regs *regs)
1804 __vmread(GUEST_SS_SELECTOR, &regs->ss);
1805 __vmread(GUEST_RSP, &regs->rsp);
1806 __vmread(GUEST_RFLAGS, &regs->rflags);
1807 __vmread(GUEST_CS_SELECTOR, &regs->cs);
1808 __vmread(GUEST_DS_SELECTOR, &regs->ds);
1809 __vmread(GUEST_ES_SELECTOR, &regs->es);
1810 __vmread(GUEST_RIP, &regs->rip);
1812 #elif defined (__i386__)
1813 void store_cpu_user_regs(struct cpu_user_regs *regs)
1815 __vmread(GUEST_SS_SELECTOR, &regs->ss);
1816 __vmread(GUEST_RSP, &regs->esp);
1817 __vmread(GUEST_RFLAGS, &regs->eflags);
1818 __vmread(GUEST_CS_SELECTOR, &regs->cs);
1819 __vmread(GUEST_DS_SELECTOR, &regs->ds);
1820 __vmread(GUEST_ES_SELECTOR, &regs->es);
1821 __vmread(GUEST_RIP, &regs->eip);
1823 #endif
1825 #ifdef XEN_DEBUGGER
1826 void save_cpu_user_regs(struct cpu_user_regs *regs)
1828 __vmread(GUEST_SS_SELECTOR, &regs->xss);
1829 __vmread(GUEST_RSP, &regs->esp);
1830 __vmread(GUEST_RFLAGS, &regs->eflags);
1831 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
1832 __vmread(GUEST_RIP, &regs->eip);
1834 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
1835 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
1836 __vmread(GUEST_ES_SELECTOR, &regs->xes);
1837 __vmread(GUEST_DS_SELECTOR, &regs->xds);
1840 void restore_cpu_user_regs(struct cpu_user_regs *regs)
1842 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
1843 __vmwrite(GUEST_RSP, regs->esp);
1844 __vmwrite(GUEST_RFLAGS, regs->eflags);
1845 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
1846 __vmwrite(GUEST_RIP, regs->eip);
1848 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
1849 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
1850 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
1851 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
1853 #endif
1855 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs regs)
1857 unsigned int exit_reason, idtv_info_field;
1858 unsigned long exit_qualification, eip, inst_len = 0;
1859 struct vcpu *v = current;
1860 int error;
1862 if ((error = __vmread(VM_EXIT_REASON, &exit_reason)))
1863 __hvm_bug(&regs);
1865 perfc_incra(vmexits, exit_reason);
1867 __vmread(IDT_VECTORING_INFO_FIELD, &idtv_info_field);
1868 if (idtv_info_field & INTR_INFO_VALID_MASK) {
1869 __vmwrite(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
1871 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1872 if (inst_len >= 1 && inst_len <= 15)
1873 __vmwrite(VM_ENTRY_INSTRUCTION_LEN, inst_len);
1875 if (idtv_info_field & 0x800) { /* valid error code */
1876 unsigned long error_code;
1877 __vmread(IDT_VECTORING_ERROR_CODE, &error_code);
1878 __vmwrite(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1881 HVM_DBG_LOG(DBG_LEVEL_1, "idtv_info_field=%x", idtv_info_field);
1884 /* don't bother H/W interrutps */
1885 if (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT &&
1886 exit_reason != EXIT_REASON_VMCALL &&
1887 exit_reason != EXIT_REASON_IO_INSTRUCTION)
1888 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
1890 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
1891 printk("Failed vm entry\n");
1892 domain_crash_synchronous();
1893 return;
1897 __vmread(GUEST_RIP, &eip);
1898 TRACE_3D(TRC_VMX_VMEXIT, v->domain->domain_id, eip, exit_reason);
1899 TRACE_VMEXIT(0,exit_reason);
1902 switch (exit_reason) {
1903 case EXIT_REASON_EXCEPTION_NMI:
1905 /*
1906 * We don't set the software-interrupt exiting (INT n).
1907 * (1) We can get an exception (e.g. #PG) in the guest, or
1908 * (2) NMI
1909 */
1910 int error;
1911 unsigned int vector;
1912 unsigned long va;
1914 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1915 || !(vector & INTR_INFO_VALID_MASK))
1916 __hvm_bug(&regs);
1917 vector &= 0xff;
1919 TRACE_VMEXIT(1,vector);
1920 perfc_incra(cause_vector, vector);
1922 TRACE_3D(TRC_VMX_VECTOR, v->domain->domain_id, eip, vector);
1923 switch (vector) {
1924 #ifdef XEN_DEBUGGER
1925 case TRAP_debug:
1927 save_cpu_user_regs(&regs);
1928 pdb_handle_exception(1, &regs, 1);
1929 restore_cpu_user_regs(&regs);
1930 break;
1932 case TRAP_int3:
1934 save_cpu_user_regs(&regs);
1935 pdb_handle_exception(3, &regs, 1);
1936 restore_cpu_user_regs(&regs);
1937 break;
1939 #else
1940 case TRAP_debug:
1942 void store_cpu_user_regs(struct cpu_user_regs *regs);
1944 store_cpu_user_regs(&regs);
1945 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS, PENDING_DEBUG_EXC_BS);
1947 domain_pause_for_debugger();
1949 break;
1951 #endif
1952 case TRAP_no_device:
1954 vmx_do_no_device_fault();
1955 break;
1957 case TRAP_page_fault:
1959 __vmread(EXIT_QUALIFICATION, &va);
1960 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs.error_code);
1962 TRACE_VMEXIT(3,regs.error_code);
1963 TRACE_VMEXIT(4,va);
1965 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1966 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
1967 (unsigned long)regs.eax, (unsigned long)regs.ebx,
1968 (unsigned long)regs.ecx, (unsigned long)regs.edx,
1969 (unsigned long)regs.esi, (unsigned long)regs.edi);
1970 v->arch.hvm_vcpu.mmio_op.inst_decoder_regs = &regs;
1972 if (!(error = vmx_do_page_fault(va, &regs))) {
1973 /*
1974 * Inject #PG using Interruption-Information Fields
1975 */
1976 vmx_inject_exception(v, TRAP_page_fault, regs.error_code);
1977 v->arch.hvm_vmx.cpu_cr2 = va;
1978 TRACE_3D(TRC_VMX_INT, v->domain->domain_id, TRAP_page_fault, va);
1980 break;
1982 case TRAP_nmi:
1983 do_nmi(&regs);
1984 break;
1985 default:
1986 vmx_reflect_exception(v);
1987 break;
1989 break;
1991 case EXIT_REASON_EXTERNAL_INTERRUPT:
1992 vmx_vmexit_do_extint(&regs);
1993 break;
1994 case EXIT_REASON_PENDING_INTERRUPT:
1995 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
1996 MONITOR_CPU_BASED_EXEC_CONTROLS);
1997 break;
1998 case EXIT_REASON_TASK_SWITCH:
1999 __hvm_bug(&regs);
2000 break;
2001 case EXIT_REASON_CPUID:
2002 __get_instruction_length(inst_len);
2003 vmx_vmexit_do_cpuid(regs.eax, &regs);
2004 __update_guest_eip(inst_len);
2005 break;
2006 case EXIT_REASON_HLT:
2007 __get_instruction_length(inst_len);
2008 __update_guest_eip(inst_len);
2009 vmx_vmexit_do_hlt();
2010 break;
2011 case EXIT_REASON_INVLPG:
2013 unsigned long va;
2015 __vmread(EXIT_QUALIFICATION, &va);
2016 vmx_vmexit_do_invlpg(va);
2017 __get_instruction_length(inst_len);
2018 __update_guest_eip(inst_len);
2019 break;
2021 case EXIT_REASON_VMCALL:
2022 __get_instruction_length(inst_len);
2023 __vmread(GUEST_RIP, &eip);
2024 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2026 hvm_print_line(v, regs.eax); /* provides the current domain */
2027 __update_guest_eip(inst_len);
2028 break;
2029 case EXIT_REASON_CR_ACCESS:
2031 __vmread(GUEST_RIP, &eip);
2032 __get_instruction_length(inst_len);
2033 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2035 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx, inst_len =%lx, exit_qualification = %lx",
2036 eip, inst_len, exit_qualification);
2037 if (vmx_cr_access(exit_qualification, &regs))
2038 __update_guest_eip(inst_len);
2039 TRACE_VMEXIT(3,regs.error_code);
2040 TRACE_VMEXIT(4,exit_qualification);
2041 break;
2043 case EXIT_REASON_DR_ACCESS:
2044 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2045 vmx_dr_access(exit_qualification, &regs);
2046 __get_instruction_length(inst_len);
2047 __update_guest_eip(inst_len);
2048 break;
2049 case EXIT_REASON_IO_INSTRUCTION:
2050 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2051 __get_instruction_length(inst_len);
2052 vmx_io_instruction(&regs, exit_qualification, inst_len);
2053 TRACE_VMEXIT(4,exit_qualification);
2054 break;
2055 case EXIT_REASON_MSR_READ:
2056 __get_instruction_length(inst_len);
2057 vmx_do_msr_read(&regs);
2058 __update_guest_eip(inst_len);
2059 break;
2060 case EXIT_REASON_MSR_WRITE:
2061 __vmread(GUEST_RIP, &eip);
2062 vmx_do_msr_write(&regs);
2063 __get_instruction_length(inst_len);
2064 __update_guest_eip(inst_len);
2065 break;
2066 case EXIT_REASON_MWAIT_INSTRUCTION:
2067 __hvm_bug(&regs);
2068 break;
2069 default:
2070 __hvm_bug(&regs); /* should not happen */
2074 asmlinkage void vmx_load_cr2(void)
2076 struct vcpu *v = current;
2078 local_irq_disable();
2079 #ifdef __i386__
2080 asm volatile("movl %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2081 #else
2082 asm volatile("movq %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2083 #endif
2086 asmlinkage void vmx_trace_vmentry (void)
2088 TRACE_5D(TRC_VMENTRY,
2089 trace_values[smp_processor_id()][0],
2090 trace_values[smp_processor_id()][1],
2091 trace_values[smp_processor_id()][2],
2092 trace_values[smp_processor_id()][3],
2093 trace_values[smp_processor_id()][4]);
2094 TRACE_VMEXIT(0,9);
2095 TRACE_VMEXIT(1,9);
2096 TRACE_VMEXIT(2,9);
2097 TRACE_VMEXIT(3,9);
2098 TRACE_VMEXIT(4,9);
2099 return;
2102 asmlinkage void vmx_trace_vmexit (void)
2104 TRACE_3D(TRC_VMEXIT,0,0,0);
2105 return;
2108 /*
2109 * Local variables:
2110 * mode: C
2111 * c-set-style: "BSD"
2112 * c-basic-offset: 4
2113 * tab-width: 4
2114 * indent-tabs-mode: nil
2115 * End:
2116 */