ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmcs.h @ 10902:022f29d4d2b8

[HVM][VMX] Clean up vmx hvm interface functions:
1) define vmx hvm interface functions static.
2) setup hvm interface functions only once.

Signed-off-by: Xin Li <xin.b.li@intel.com>
author kfraser@localhost.localdomain
date Wed Aug 02 09:38:08 2006 +0100 (2006-08-02)
parents 82f481bda1c7
children d20e1835c24b
line source
1 /*
2 * vmcs.h: VMCS related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMCS_H__
20 #define __ASM_X86_HVM_VMX_VMCS_H__
22 #include <asm/config.h>
23 #include <asm/hvm/io.h>
24 #include <asm/hvm/vmx/cpu.h>
25 #include <public/hvm/vmx_assist.h>
27 extern int start_vmx(void);
28 extern void vmcs_dump_vcpu(void);
29 extern void vmx_init_vmcs_config(void);
31 enum {
32 VMX_CPU_STATE_PAE_ENABLED=0,
33 VMX_CPU_STATE_LME_ENABLED,
34 VMX_CPU_STATE_LMA_ENABLED,
35 VMX_CPU_STATE_ASSIST_ENABLED,
36 };
38 #define VMX_LONG_GUEST(ed) \
39 (test_bit(VMX_CPU_STATE_LMA_ENABLED, &ed->arch.hvm_vmx.cpu_state))
41 struct vmcs_struct {
42 u32 vmcs_revision_id;
43 unsigned char data [0]; /* vmcs size is read from MSR */
44 };
46 enum {
47 VMX_INDEX_MSR_LSTAR = 0,
48 VMX_INDEX_MSR_STAR,
49 VMX_INDEX_MSR_CSTAR,
50 VMX_INDEX_MSR_SYSCALL_MASK,
51 VMX_INDEX_MSR_EFER,
53 VMX_MSR_COUNT,
54 };
56 struct vmx_msr_state {
57 unsigned long flags;
58 unsigned long msr_items[VMX_MSR_COUNT];
59 unsigned long shadow_gs;
60 };
62 /* io bitmap is 4KBytes in size */
63 #define IO_BITMAP_SIZE 0x1000
64 #define IO_BITMAP_ORDER (get_order_from_bytes(IO_BITMAP_SIZE))
66 struct arch_vmx_struct {
67 /* Virtual address of VMCS. */
68 struct vmcs_struct *vmcs;
70 /* Protects remote usage of VMCS (VMPTRLD/VMCLEAR). */
71 spinlock_t vmcs_lock;
73 /*
74 * Activation and launch status of this VMCS.
75 * - Activated on a CPU by VMPTRLD. Deactivated by VMCLEAR.
76 * - Launched on active CPU by VMLAUNCH when current VMCS.
77 */
78 int active_cpu;
79 int launched;
81 /* Cache of cpu execution control. */
82 u32 exec_control;
84 /* If there is vector installed in the INTR_INFO_FIELD. */
85 u32 vector_injected;
87 unsigned long cpu_cr0; /* copy of guest CR0 */
88 unsigned long cpu_shadow_cr0; /* copy of guest read shadow CR0 */
89 unsigned long cpu_cr2; /* save CR2 */
90 unsigned long cpu_cr3;
91 unsigned long cpu_state;
92 unsigned long cpu_based_exec_control;
93 struct vmx_msr_state msr_content;
94 void *io_bitmap_a, *io_bitmap_b;
95 struct timer hlt_timer; /* hlt ins emulation wakeup timer */
96 };
98 #define vmx_schedule_tail(next) \
99 (next)->thread.arch_vmx.arch_vmx_schedule_tail((next))
101 void vmx_do_resume(struct vcpu *);
103 struct vmcs_struct *vmx_alloc_host_vmcs(void);
104 void vmx_free_host_vmcs(struct vmcs_struct *vmcs);
106 int vmx_create_vmcs(struct vcpu *v);
107 void vmx_destroy_vmcs(struct vcpu *v);
108 void vmx_vmcs_enter(struct vcpu *v);
109 void vmx_vmcs_exit(struct vcpu *v);
111 #define VMCS_USE_HOST_ENV 1
112 #define VMCS_USE_SEPARATE_ENV 0
114 extern int vmcs_version;
116 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
117 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
118 #define CPU_BASED_HLT_EXITING 0x00000080
119 #define CPU_BASED_INVDPG_EXITING 0x00000200
120 #define CPU_BASED_MWAIT_EXITING 0x00000400
121 #define CPU_BASED_RDPMC_EXITING 0x00000800
122 #define CPU_BASED_RDTSC_EXITING 0x00001000
123 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
124 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
125 #define CPU_BASED_TPR_SHADOW 0x00200000
126 #define CPU_BASED_MOV_DR_EXITING 0x00800000
127 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
128 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
129 #define CPU_BASED_MONITOR_EXITING 0x20000000
130 #define CPU_BASED_PAUSE_EXITING 0x40000000
131 #define PIN_BASED_EXT_INTR_MASK 0x1
132 #define PIN_BASED_NMI_EXITING 0x8
134 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
135 #define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200
138 /* VMCS Encordings */
139 enum vmcs_field {
140 GUEST_ES_SELECTOR = 0x00000800,
141 GUEST_CS_SELECTOR = 0x00000802,
142 GUEST_SS_SELECTOR = 0x00000804,
143 GUEST_DS_SELECTOR = 0x00000806,
144 GUEST_FS_SELECTOR = 0x00000808,
145 GUEST_GS_SELECTOR = 0x0000080a,
146 GUEST_LDTR_SELECTOR = 0x0000080c,
147 GUEST_TR_SELECTOR = 0x0000080e,
148 HOST_ES_SELECTOR = 0x00000c00,
149 HOST_CS_SELECTOR = 0x00000c02,
150 HOST_SS_SELECTOR = 0x00000c04,
151 HOST_DS_SELECTOR = 0x00000c06,
152 HOST_FS_SELECTOR = 0x00000c08,
153 HOST_GS_SELECTOR = 0x00000c0a,
154 HOST_TR_SELECTOR = 0x00000c0c,
155 IO_BITMAP_A = 0x00002000,
156 IO_BITMAP_A_HIGH = 0x00002001,
157 IO_BITMAP_B = 0x00002002,
158 IO_BITMAP_B_HIGH = 0x00002003,
159 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
160 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
161 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
162 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
163 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
164 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
165 TSC_OFFSET = 0x00002010,
166 TSC_OFFSET_HIGH = 0x00002011,
167 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
168 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
169 VMCS_LINK_POINTER = 0x00002800,
170 VMCS_LINK_POINTER_HIGH = 0x00002801,
171 GUEST_IA32_DEBUGCTL = 0x00002802,
172 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
173 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
174 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
175 EXCEPTION_BITMAP = 0x00004004,
176 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
177 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
178 CR3_TARGET_COUNT = 0x0000400a,
179 VM_EXIT_CONTROLS = 0x0000400c,
180 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
181 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
182 VM_ENTRY_CONTROLS = 0x00004012,
183 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
184 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
185 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
186 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
187 TPR_THRESHOLD = 0x0000401c,
188 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
189 VM_INSTRUCTION_ERROR = 0x00004400,
190 VM_EXIT_REASON = 0x00004402,
191 VM_EXIT_INTR_INFO = 0x00004404,
192 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
193 IDT_VECTORING_INFO_FIELD = 0x00004408,
194 IDT_VECTORING_ERROR_CODE = 0x0000440a,
195 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
196 VMX_INSTRUCTION_INFO = 0x0000440e,
197 GUEST_ES_LIMIT = 0x00004800,
198 GUEST_CS_LIMIT = 0x00004802,
199 GUEST_SS_LIMIT = 0x00004804,
200 GUEST_DS_LIMIT = 0x00004806,
201 GUEST_FS_LIMIT = 0x00004808,
202 GUEST_GS_LIMIT = 0x0000480a,
203 GUEST_LDTR_LIMIT = 0x0000480c,
204 GUEST_TR_LIMIT = 0x0000480e,
205 GUEST_GDTR_LIMIT = 0x00004810,
206 GUEST_IDTR_LIMIT = 0x00004812,
207 GUEST_ES_AR_BYTES = 0x00004814,
208 GUEST_CS_AR_BYTES = 0x00004816,
209 GUEST_SS_AR_BYTES = 0x00004818,
210 GUEST_DS_AR_BYTES = 0x0000481a,
211 GUEST_FS_AR_BYTES = 0x0000481c,
212 GUEST_GS_AR_BYTES = 0x0000481e,
213 GUEST_LDTR_AR_BYTES = 0x00004820,
214 GUEST_TR_AR_BYTES = 0x00004822,
215 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
216 GUEST_SYSENTER_CS = 0x0000482A,
217 HOST_IA32_SYSENTER_CS = 0x00004c00,
218 CR0_GUEST_HOST_MASK = 0x00006000,
219 CR4_GUEST_HOST_MASK = 0x00006002,
220 CR0_READ_SHADOW = 0x00006004,
221 CR4_READ_SHADOW = 0x00006006,
222 CR3_TARGET_VALUE0 = 0x00006008,
223 CR3_TARGET_VALUE1 = 0x0000600a,
224 CR3_TARGET_VALUE2 = 0x0000600c,
225 CR3_TARGET_VALUE3 = 0x0000600e,
226 EXIT_QUALIFICATION = 0x00006400,
227 GUEST_LINEAR_ADDRESS = 0x0000640a,
228 GUEST_CR0 = 0x00006800,
229 GUEST_CR3 = 0x00006802,
230 GUEST_CR4 = 0x00006804,
231 GUEST_ES_BASE = 0x00006806,
232 GUEST_CS_BASE = 0x00006808,
233 GUEST_SS_BASE = 0x0000680a,
234 GUEST_DS_BASE = 0x0000680c,
235 GUEST_FS_BASE = 0x0000680e,
236 GUEST_GS_BASE = 0x00006810,
237 GUEST_LDTR_BASE = 0x00006812,
238 GUEST_TR_BASE = 0x00006814,
239 GUEST_GDTR_BASE = 0x00006816,
240 GUEST_IDTR_BASE = 0x00006818,
241 GUEST_DR7 = 0x0000681a,
242 GUEST_RSP = 0x0000681c,
243 GUEST_RIP = 0x0000681e,
244 GUEST_RFLAGS = 0x00006820,
245 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
246 GUEST_SYSENTER_ESP = 0x00006824,
247 GUEST_SYSENTER_EIP = 0x00006826,
248 HOST_CR0 = 0x00006c00,
249 HOST_CR3 = 0x00006c02,
250 HOST_CR4 = 0x00006c04,
251 HOST_FS_BASE = 0x00006c06,
252 HOST_GS_BASE = 0x00006c08,
253 HOST_TR_BASE = 0x00006c0a,
254 HOST_GDTR_BASE = 0x00006c0c,
255 HOST_IDTR_BASE = 0x00006c0e,
256 HOST_IA32_SYSENTER_ESP = 0x00006c10,
257 HOST_IA32_SYSENTER_EIP = 0x00006c12,
258 HOST_RSP = 0x00006c14,
259 HOST_RIP = 0x00006c16,
260 };
262 #endif /* ASM_X86_HVM_VMX_VMCS_H__ */
264 /*
265 * Local variables:
266 * mode: C
267 * c-set-style: "BSD"
268 * c-basic-offset: 4
269 * tab-width: 4
270 * indent-tabs-mode: nil
271 * End:
272 */