ia64/xen-unstable

view xen/arch/x86/hvm/vmx/vmx.c @ 10902:022f29d4d2b8

[HVM][VMX] Clean up vmx hvm interface functions:
1) define vmx hvm interface functions static.
2) setup hvm interface functions only once.

Signed-off-by: Xin Li <xin.b.li@intel.com>
author kfraser@localhost.localdomain
date Wed Aug 02 09:38:08 2006 +0100 (2006-08-02)
parents 0d2ba35c0cf2
children 822c39808e62
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <asm/current.h>
29 #include <asm/io.h>
30 #include <asm/shadow.h>
31 #include <asm/regs.h>
32 #include <asm/cpufeature.h>
33 #include <asm/processor.h>
34 #include <asm/types.h>
35 #include <asm/msr.h>
36 #include <asm/spinlock.h>
37 #include <asm/hvm/hvm.h>
38 #include <asm/hvm/support.h>
39 #include <asm/hvm/vmx/vmx.h>
40 #include <asm/hvm/vmx/vmcs.h>
41 #include <asm/hvm/vmx/cpu.h>
42 #include <asm/shadow.h>
43 #if CONFIG_PAGING_LEVELS >= 3
44 #include <asm/shadow_64.h>
45 #endif
46 #include <public/sched.h>
47 #include <public/hvm/ioreq.h>
48 #include <asm/hvm/vpic.h>
49 #include <asm/hvm/vlapic.h>
51 static unsigned long trace_values[NR_CPUS][5];
52 #define TRACE_VMEXIT(index,value) trace_values[smp_processor_id()][index]=value
54 static void vmx_ctxt_switch_from(struct vcpu *v);
55 static void vmx_ctxt_switch_to(struct vcpu *v);
57 static int vmx_initialize_guest_resources(struct vcpu *v)
58 {
59 struct domain *d = v->domain;
60 struct vcpu *vc;
61 void *io_bitmap_a, *io_bitmap_b;
62 int rc;
64 v->arch.schedule_tail = arch_vmx_do_launch;
65 v->arch.ctxt_switch_from = vmx_ctxt_switch_from;
66 v->arch.ctxt_switch_to = vmx_ctxt_switch_to;
68 if ( v->vcpu_id != 0 )
69 return 1;
71 for_each_vcpu ( d, vc )
72 {
73 /* Initialize monitor page table */
74 vc->arch.monitor_table = pagetable_null();
76 memset(&vc->arch.hvm_vmx, 0, sizeof(struct arch_vmx_struct));
78 if ( (rc = vmx_create_vmcs(vc)) != 0 )
79 {
80 DPRINTK("Failed to create VMCS for vcpu %d: err=%d.\n",
81 vc->vcpu_id, rc);
82 return 0;
83 }
85 spin_lock_init(&vc->arch.hvm_vmx.vmcs_lock);
87 if ( (io_bitmap_a = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
88 {
89 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
90 vc->vcpu_id);
91 return 0;
92 }
94 if ( (io_bitmap_b = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
95 {
96 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
97 vc->vcpu_id);
98 return 0;
99 }
101 memset(io_bitmap_a, 0xff, 0x1000);
102 memset(io_bitmap_b, 0xff, 0x1000);
104 /* don't bother debug port access */
105 clear_bit(PC_DEBUG_PORT, io_bitmap_a);
107 vc->arch.hvm_vmx.io_bitmap_a = io_bitmap_a;
108 vc->arch.hvm_vmx.io_bitmap_b = io_bitmap_b;
109 }
111 /*
112 * Required to do this once per domain XXX todo: add a seperate function
113 * to do these.
114 */
115 memset(&d->shared_info->evtchn_mask[0], 0xff,
116 sizeof(d->shared_info->evtchn_mask));
118 /* Put the domain in shadow mode even though we're going to be using
119 * the shared 1:1 page table initially. It shouldn't hurt */
120 shadow_mode_enable(
121 d, SHM_enable|SHM_refcounts|SHM_translate|SHM_external|SHM_wr_pt_pte);
123 return 1;
124 }
126 static void vmx_relinquish_guest_resources(struct domain *d)
127 {
128 struct vcpu *v;
130 for_each_vcpu ( d, v )
131 {
132 vmx_destroy_vmcs(v);
133 if ( !test_bit(_VCPUF_initialised, &v->vcpu_flags) )
134 continue;
135 free_monitor_pagetable(v);
136 kill_timer(&v->arch.hvm_vmx.hlt_timer);
137 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
138 {
139 kill_timer(&VLAPIC(v)->vlapic_timer);
140 xfree(VLAPIC(v));
141 }
142 }
144 kill_timer(&d->arch.hvm_domain.pl_time.periodic_tm.timer);
146 if ( d->arch.hvm_domain.shared_page_va )
147 unmap_domain_page_global(
148 (void *)d->arch.hvm_domain.shared_page_va);
150 shadow_direct_map_clean(d);
151 }
153 #ifdef __x86_64__
155 static struct vmx_msr_state percpu_msr[NR_CPUS];
157 static u32 msr_data_index[VMX_MSR_COUNT] =
158 {
159 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
160 MSR_SYSCALL_MASK, MSR_EFER,
161 };
163 static void vmx_save_segments(struct vcpu *v)
164 {
165 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
166 }
168 /*
169 * To avoid MSR save/restore at every VM exit/entry time, we restore
170 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
171 * are not modified once set for generic domains, we don't save them,
172 * but simply reset them to the values set at percpu_traps_init().
173 */
174 static void vmx_load_msrs(void)
175 {
176 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
177 int i;
179 while ( host_state->flags )
180 {
181 i = find_first_set_bit(host_state->flags);
182 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
183 clear_bit(i, &host_state->flags);
184 }
185 }
187 static void vmx_save_init_msrs(void)
188 {
189 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
190 int i;
192 for ( i = 0; i < VMX_MSR_COUNT; i++ )
193 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
194 }
196 #define CASE_READ_MSR(address) \
197 case MSR_ ## address: \
198 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
199 break
201 #define CASE_WRITE_MSR(address) \
202 case MSR_ ## address: \
203 { \
204 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
205 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
206 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
207 } \
208 wrmsrl(MSR_ ## address, msr_content); \
209 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
210 } \
211 break
213 #define IS_CANO_ADDRESS(add) 1
214 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
215 {
216 u64 msr_content = 0;
217 struct vcpu *v = current;
218 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
220 switch ( regs->ecx ) {
221 case MSR_EFER:
222 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content 0x%"PRIx64, msr_content);
223 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
225 /* the following code may be not needed */
226 if ( test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
227 msr_content |= EFER_LME;
228 else
229 msr_content &= ~EFER_LME;
231 if ( VMX_LONG_GUEST(v) )
232 msr_content |= EFER_LMA;
233 else
234 msr_content &= ~EFER_LMA;
235 break;
237 case MSR_FS_BASE:
238 if ( !(VMX_LONG_GUEST(v)) )
239 /* XXX should it be GP fault */
240 domain_crash_synchronous();
242 __vmread(GUEST_FS_BASE, &msr_content);
243 break;
245 case MSR_GS_BASE:
246 if ( !(VMX_LONG_GUEST(v)) )
247 domain_crash_synchronous();
249 __vmread(GUEST_GS_BASE, &msr_content);
250 break;
252 case MSR_SHADOW_GS_BASE:
253 msr_content = msr->shadow_gs;
254 break;
256 CASE_READ_MSR(STAR);
257 CASE_READ_MSR(LSTAR);
258 CASE_READ_MSR(CSTAR);
259 CASE_READ_MSR(SYSCALL_MASK);
261 default:
262 return 0;
263 }
265 HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
267 regs->eax = msr_content & 0xffffffff;
268 regs->edx = msr_content >> 32;
270 return 1;
271 }
273 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
274 {
275 u64 msr_content = regs->eax | ((u64)regs->edx << 32);
276 struct vcpu *v = current;
277 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
278 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
280 HVM_DBG_LOG(DBG_LEVEL_1, "msr 0x%lx msr_content 0x%"PRIx64"\n",
281 (unsigned long)regs->ecx, msr_content);
283 switch ( regs->ecx ) {
284 case MSR_EFER:
285 /* offending reserved bit will cause #GP */
286 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
287 {
288 printk("trying to set reserved bit in EFER\n");
289 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
290 return 0;
291 }
293 /* LME: 0 -> 1 */
294 if ( msr_content & EFER_LME &&
295 !test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
296 {
297 if ( vmx_paging_enabled(v) ||
298 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
299 &v->arch.hvm_vmx.cpu_state) )
300 {
301 printk("trying to set LME bit when "
302 "in paging mode or PAE bit is not set\n");
303 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
304 return 0;
305 }
307 set_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state);
308 }
310 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
311 break;
313 case MSR_FS_BASE:
314 case MSR_GS_BASE:
315 if ( !(VMX_LONG_GUEST(v)) )
316 domain_crash_synchronous();
318 if ( !IS_CANO_ADDRESS(msr_content) )
319 {
320 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
321 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
322 return 0;
323 }
325 if ( regs->ecx == MSR_FS_BASE )
326 __vmwrite(GUEST_FS_BASE, msr_content);
327 else
328 __vmwrite(GUEST_GS_BASE, msr_content);
330 break;
332 case MSR_SHADOW_GS_BASE:
333 if ( !(VMX_LONG_GUEST(v)) )
334 domain_crash_synchronous();
336 v->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
337 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
338 break;
340 CASE_WRITE_MSR(STAR);
341 CASE_WRITE_MSR(LSTAR);
342 CASE_WRITE_MSR(CSTAR);
343 CASE_WRITE_MSR(SYSCALL_MASK);
345 default:
346 return 0;
347 }
349 return 1;
350 }
352 static void vmx_restore_msrs(struct vcpu *v)
353 {
354 int i = 0;
355 struct vmx_msr_state *guest_state;
356 struct vmx_msr_state *host_state;
357 unsigned long guest_flags ;
359 guest_state = &v->arch.hvm_vmx.msr_content;;
360 host_state = &percpu_msr[smp_processor_id()];
362 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
363 guest_flags = guest_state->flags;
364 if (!guest_flags)
365 return;
367 while (guest_flags){
368 i = find_first_set_bit(guest_flags);
370 HVM_DBG_LOG(DBG_LEVEL_2,
371 "restore guest's index %d msr %lx with %lx\n",
372 i, (unsigned long)msr_data_index[i],
373 (unsigned long)guest_state->msr_items[i]);
374 set_bit(i, &host_state->flags);
375 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
376 clear_bit(i, &guest_flags);
377 }
378 }
380 #else /* __i386__ */
382 #define vmx_save_segments(v) ((void)0)
383 #define vmx_load_msrs() ((void)0)
384 #define vmx_restore_msrs(v) ((void)0)
385 #define vmx_save_init_msrs() ((void)0)
387 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
388 {
389 return 0;
390 }
392 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
393 {
394 return 0;
395 }
397 #endif /* __i386__ */
399 #define loaddebug(_v,_reg) \
400 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
401 #define savedebug(_v,_reg) \
402 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
404 static inline void vmx_save_dr(struct vcpu *v)
405 {
406 if ( v->arch.hvm_vcpu.flag_dr_dirty )
407 {
408 savedebug(&v->arch.guest_context, 0);
409 savedebug(&v->arch.guest_context, 1);
410 savedebug(&v->arch.guest_context, 2);
411 savedebug(&v->arch.guest_context, 3);
412 savedebug(&v->arch.guest_context, 6);
414 v->arch.hvm_vcpu.flag_dr_dirty = 0;
416 v->arch.hvm_vcpu.u.vmx.exec_control |= CPU_BASED_MOV_DR_EXITING;
417 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
418 v->arch.hvm_vcpu.u.vmx.exec_control);
419 }
420 }
422 static inline void __restore_debug_registers(struct vcpu *v)
423 {
424 loaddebug(&v->arch.guest_context, 0);
425 loaddebug(&v->arch.guest_context, 1);
426 loaddebug(&v->arch.guest_context, 2);
427 loaddebug(&v->arch.guest_context, 3);
428 /* No 4 and 5 */
429 loaddebug(&v->arch.guest_context, 6);
430 /* DR7 is loaded from the vmcs. */
431 }
433 /*
434 * DR7 is saved and restored on every vmexit. Other debug registers only
435 * need to be restored if their value is going to affect execution -- i.e.,
436 * if one of the breakpoints is enabled. So mask out all bits that don't
437 * enable some breakpoint functionality.
438 *
439 * This is in part necessary because bit 10 of DR7 is hardwired to 1, so a
440 * simple if( guest_dr7 ) will always return true. As long as we're masking,
441 * we might as well do it right.
442 */
443 #define DR7_ACTIVE_MASK 0xff
445 static inline void vmx_restore_dr(struct vcpu *v)
446 {
447 unsigned long guest_dr7;
449 __vmread(GUEST_DR7, &guest_dr7);
451 /* Assumes guest does not have DR access at time of context switch. */
452 if ( unlikely(guest_dr7 & DR7_ACTIVE_MASK) )
453 __restore_debug_registers(v);
454 }
456 static void vmx_freeze_time(struct vcpu *v)
457 {
458 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
460 if ( pt->enabled && pt->first_injected && !v->arch.hvm_vcpu.guest_time ) {
461 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
462 stop_timer(&(pt->timer));
463 }
464 }
466 static void vmx_ctxt_switch_from(struct vcpu *v)
467 {
468 vmx_freeze_time(v);
469 vmx_save_segments(v);
470 vmx_load_msrs();
471 vmx_save_dr(v);
472 }
474 static void vmx_ctxt_switch_to(struct vcpu *v)
475 {
476 vmx_restore_msrs(v);
477 vmx_restore_dr(v);
478 }
480 static void stop_vmx(void)
481 {
482 if (read_cr4() & X86_CR4_VMXE)
483 __vmxoff();
484 }
486 void vmx_migrate_timers(struct vcpu *v)
487 {
488 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
490 if ( pt->enabled ) {
491 migrate_timer(&pt->timer, v->processor);
492 migrate_timer(&v->arch.hvm_vmx.hlt_timer, v->processor);
493 }
494 if ( hvm_apic_support(v->domain) && VLAPIC(v))
495 migrate_timer(&(VLAPIC(v)->vlapic_timer), v->processor);
496 }
498 static void vmx_store_cpu_guest_regs(
499 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
500 {
501 vmx_vmcs_enter(v);
503 if ( regs != NULL )
504 {
505 __vmread(GUEST_RFLAGS, &regs->eflags);
506 __vmread(GUEST_SS_SELECTOR, &regs->ss);
507 __vmread(GUEST_CS_SELECTOR, &regs->cs);
508 __vmread(GUEST_DS_SELECTOR, &regs->ds);
509 __vmread(GUEST_ES_SELECTOR, &regs->es);
510 __vmread(GUEST_GS_SELECTOR, &regs->gs);
511 __vmread(GUEST_FS_SELECTOR, &regs->fs);
512 __vmread(GUEST_RIP, &regs->eip);
513 __vmread(GUEST_RSP, &regs->esp);
514 }
516 if ( crs != NULL )
517 {
518 __vmread(CR0_READ_SHADOW, &crs[0]);
519 __vmread(GUEST_CR3, &crs[3]);
520 __vmread(CR4_READ_SHADOW, &crs[4]);
521 }
523 vmx_vmcs_exit(v);
524 }
526 /*
527 * The VMX spec (section 4.3.1.2, Checks on Guest Segment
528 * Registers) says that virtual-8086 mode guests' segment
529 * base-address fields in the VMCS must be equal to their
530 * corresponding segment selector field shifted right by
531 * four bits upon vmentry.
532 *
533 * This function (called only for VM86-mode guests) fixes
534 * the bases to be consistent with the selectors in regs
535 * if they're not already. Without this, we can fail the
536 * vmentry check mentioned above.
537 */
538 static void fixup_vm86_seg_bases(struct cpu_user_regs *regs)
539 {
540 int err = 0;
541 unsigned long base;
543 err |= __vmread(GUEST_ES_BASE, &base);
544 if (regs->es << 4 != base)
545 err |= __vmwrite(GUEST_ES_BASE, regs->es << 4);
546 err |= __vmread(GUEST_CS_BASE, &base);
547 if (regs->cs << 4 != base)
548 err |= __vmwrite(GUEST_CS_BASE, regs->cs << 4);
549 err |= __vmread(GUEST_SS_BASE, &base);
550 if (regs->ss << 4 != base)
551 err |= __vmwrite(GUEST_SS_BASE, regs->ss << 4);
552 err |= __vmread(GUEST_DS_BASE, &base);
553 if (regs->ds << 4 != base)
554 err |= __vmwrite(GUEST_DS_BASE, regs->ds << 4);
555 err |= __vmread(GUEST_FS_BASE, &base);
556 if (regs->fs << 4 != base)
557 err |= __vmwrite(GUEST_FS_BASE, regs->fs << 4);
558 err |= __vmread(GUEST_GS_BASE, &base);
559 if (regs->gs << 4 != base)
560 err |= __vmwrite(GUEST_GS_BASE, regs->gs << 4);
562 BUG_ON(err);
563 }
565 static void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
566 {
567 vmx_vmcs_enter(v);
569 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
570 __vmwrite(GUEST_DS_SELECTOR, regs->ds);
571 __vmwrite(GUEST_ES_SELECTOR, regs->es);
572 __vmwrite(GUEST_GS_SELECTOR, regs->gs);
573 __vmwrite(GUEST_FS_SELECTOR, regs->fs);
575 __vmwrite(GUEST_RSP, regs->esp);
577 __vmwrite(GUEST_RFLAGS, regs->eflags);
578 if (regs->eflags & EF_TF)
579 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
580 else
581 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
582 if (regs->eflags & EF_VM)
583 fixup_vm86_seg_bases(regs);
585 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
586 __vmwrite(GUEST_RIP, regs->eip);
588 vmx_vmcs_exit(v);
589 }
591 static int vmx_realmode(struct vcpu *v)
592 {
593 unsigned long rflags;
595 __vmread(GUEST_RFLAGS, &rflags);
596 return rflags & X86_EFLAGS_VM;
597 }
599 static int vmx_instruction_length(struct vcpu *v)
600 {
601 unsigned long inst_len;
603 if (__vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len))
604 return 0;
605 return inst_len;
606 }
608 static unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
609 {
610 switch ( num )
611 {
612 case 0:
613 return v->arch.hvm_vmx.cpu_cr0;
614 case 2:
615 return v->arch.hvm_vmx.cpu_cr2;
616 case 3:
617 return v->arch.hvm_vmx.cpu_cr3;
618 default:
619 BUG();
620 }
621 return 0; /* dummy */
622 }
624 /* SMP VMX guest support */
625 static void vmx_init_ap_context(struct vcpu_guest_context *ctxt,
626 int vcpuid, int trampoline_vector)
627 {
628 int i;
630 memset(ctxt, 0, sizeof(*ctxt));
632 /*
633 * Initial register values:
634 */
635 ctxt->user_regs.eip = VMXASSIST_BASE;
636 ctxt->user_regs.edx = vcpuid;
637 ctxt->user_regs.ebx = trampoline_vector;
639 ctxt->flags = VGCF_HVM_GUEST;
641 /* Virtual IDT is empty at start-of-day. */
642 for ( i = 0; i < 256; i++ )
643 {
644 ctxt->trap_ctxt[i].vector = i;
645 ctxt->trap_ctxt[i].cs = FLAT_KERNEL_CS;
646 }
648 /* No callback handlers. */
649 #if defined(__i386__)
650 ctxt->event_callback_cs = FLAT_KERNEL_CS;
651 ctxt->failsafe_callback_cs = FLAT_KERNEL_CS;
652 #endif
653 }
655 void do_nmi(struct cpu_user_regs *);
657 static int check_vmx_controls(u32 ctrls, u32 msr)
658 {
659 u32 vmx_msr_low, vmx_msr_high;
661 rdmsr(msr, vmx_msr_low, vmx_msr_high);
662 if ( (ctrls < vmx_msr_low) || (ctrls > vmx_msr_high) )
663 {
664 printk("Insufficient VMX capability 0x%x, "
665 "msr=0x%x,low=0x%8x,high=0x%x\n",
666 ctrls, msr, vmx_msr_low, vmx_msr_high);
667 return 0;
668 }
669 return 1;
670 }
672 /* Setup HVM interfaces */
673 static void vmx_setup_hvm_funcs(void)
674 {
675 if ( hvm_enabled )
676 return;
678 hvm_funcs.disable = stop_vmx;
680 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
681 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
683 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
684 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
686 hvm_funcs.realmode = vmx_realmode;
687 hvm_funcs.paging_enabled = vmx_paging_enabled;
688 hvm_funcs.instruction_length = vmx_instruction_length;
689 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
691 hvm_funcs.init_ap_context = vmx_init_ap_context;
692 }
694 static void vmx_init_hypercall_page(struct domain *d, void *hypercall_page)
695 {
696 char *p;
697 int i;
699 memset(hypercall_page, 0, PAGE_SIZE);
701 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
702 {
703 p = (char *)(hypercall_page + (i * 32));
704 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
705 *(u32 *)(p + 1) = i;
706 *(u8 *)(p + 5) = 0x0f; /* vmcall */
707 *(u8 *)(p + 6) = 0x01;
708 *(u8 *)(p + 7) = 0xc1;
709 *(u8 *)(p + 8) = 0xc3; /* ret */
710 }
712 /* Don't support HYPERVISOR_iret at the moment */
713 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
714 }
716 int start_vmx(void)
717 {
718 u32 eax, edx;
719 struct vmcs_struct *vmcs;
721 /*
722 * Xen does not fill x86_capability words except 0.
723 */
724 boot_cpu_data.x86_capability[4] = cpuid_ecx(1);
726 if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
727 return 0;
729 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
731 if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
732 {
733 if ( (eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0 )
734 {
735 printk("VMX disabled by Feature Control MSR.\n");
736 return 0;
737 }
738 }
739 else
740 {
741 wrmsr(IA32_FEATURE_CONTROL_MSR,
742 IA32_FEATURE_CONTROL_MSR_LOCK |
743 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
744 }
746 if ( !check_vmx_controls(MONITOR_PIN_BASED_EXEC_CONTROLS,
747 MSR_IA32_VMX_PINBASED_CTLS_MSR) )
748 return 0;
749 if ( !check_vmx_controls(MONITOR_CPU_BASED_EXEC_CONTROLS,
750 MSR_IA32_VMX_PROCBASED_CTLS_MSR) )
751 return 0;
752 if ( !check_vmx_controls(MONITOR_VM_EXIT_CONTROLS,
753 MSR_IA32_VMX_EXIT_CTLS_MSR) )
754 return 0;
755 if ( !check_vmx_controls(MONITOR_VM_ENTRY_CONTROLS,
756 MSR_IA32_VMX_ENTRY_CTLS_MSR) )
757 return 0;
759 set_in_cr4(X86_CR4_VMXE);
761 vmx_init_vmcs_config();
763 if ( (vmcs = vmx_alloc_host_vmcs()) == NULL )
764 {
765 printk("Failed to allocate host VMCS\n");
766 return 0;
767 }
769 if ( __vmxon(virt_to_maddr(vmcs)) )
770 {
771 printk("VMXON failed\n");
772 vmx_free_host_vmcs(vmcs);
773 return 0;
774 }
776 printk("VMXON is done\n");
778 vmx_save_init_msrs();
780 vmx_setup_hvm_funcs();
782 hvm_funcs.init_hypercall_page = vmx_init_hypercall_page;
784 hvm_enabled = 1;
786 return 1;
787 }
789 /*
790 * Not all cases receive valid value in the VM-exit instruction length field.
791 */
792 #define __get_instruction_length(len) \
793 __vmread(VM_EXIT_INSTRUCTION_LEN, &(len)); \
794 if ((len) < 1 || (len) > 15) \
795 __hvm_bug(&regs);
797 static void inline __update_guest_eip(unsigned long inst_len)
798 {
799 unsigned long current_eip;
801 __vmread(GUEST_RIP, &current_eip);
802 __vmwrite(GUEST_RIP, current_eip + inst_len);
803 __vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
804 }
807 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
808 {
809 unsigned long gpa; /* FIXME: PAE */
810 int result;
812 #if 0 /* keep for debugging */
813 {
814 unsigned long eip;
816 __vmread(GUEST_RIP, &eip);
817 HVM_DBG_LOG(DBG_LEVEL_VMMU,
818 "vmx_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
819 va, eip, (unsigned long)regs->error_code);
820 }
821 #endif
823 if ( !vmx_paging_enabled(current) )
824 {
825 /* construct 1-to-1 direct mapping */
826 if ( shadow_direct_map_fault(va, regs) )
827 return 1;
829 handle_mmio(va, va);
830 TRACE_VMEXIT (2,2);
831 return 1;
832 }
833 gpa = gva_to_gpa(va);
835 /* Use 1:1 page table to identify MMIO address space */
836 if ( mmio_space(gpa) ){
837 struct vcpu *v = current;
838 /* No support for APIC */
839 if (!hvm_apic_support(v->domain) && gpa >= 0xFEC00000) {
840 u32 inst_len;
841 __vmread(VM_EXIT_INSTRUCTION_LEN, &(inst_len));
842 __update_guest_eip(inst_len);
843 return 1;
844 }
845 TRACE_VMEXIT (2,2);
846 /* in the case of MMIO, we are more interested in gpa than in va */
847 TRACE_VMEXIT (4,gpa);
848 handle_mmio(va, gpa);
849 return 1;
850 }
852 result = shadow_fault(va, regs);
853 TRACE_VMEXIT (2,result);
854 #if 0
855 if ( !result )
856 {
857 __vmread(GUEST_RIP, &eip);
858 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
859 }
860 #endif
862 return result;
863 }
865 static void vmx_do_no_device_fault(void)
866 {
867 unsigned long cr0;
868 struct vcpu *v = current;
870 setup_fpu(current);
871 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
873 /* Disable TS in guest CR0 unless the guest wants the exception too. */
874 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
875 if ( !(cr0 & X86_CR0_TS) )
876 {
877 __vmread_vcpu(v, GUEST_CR0, &cr0);
878 cr0 &= ~X86_CR0_TS;
879 __vmwrite(GUEST_CR0, cr0);
880 }
881 }
883 #define bitmaskof(idx) (1U << ((idx)&31))
884 static void vmx_vmexit_do_cpuid(struct cpu_user_regs *regs)
885 {
886 unsigned int input = (unsigned int)regs->eax;
887 unsigned int count = (unsigned int)regs->ecx;
888 unsigned int eax, ebx, ecx, edx;
889 unsigned long eip;
890 struct vcpu *v = current;
892 __vmread(GUEST_RIP, &eip);
894 HVM_DBG_LOG(DBG_LEVEL_3, "(eax) 0x%08lx, (ebx) 0x%08lx, "
895 "(ecx) 0x%08lx, (edx) 0x%08lx, (esi) 0x%08lx, (edi) 0x%08lx",
896 (unsigned long)regs->eax, (unsigned long)regs->ebx,
897 (unsigned long)regs->ecx, (unsigned long)regs->edx,
898 (unsigned long)regs->esi, (unsigned long)regs->edi);
900 if ( input == CPUID_LEAF_0x4 )
901 {
902 cpuid_count(input, count, &eax, &ebx, &ecx, &edx);
903 eax &= NUM_CORES_RESET_MASK;
904 }
905 else if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
906 {
907 cpuid(input, &eax, &ebx, &ecx, &edx);
909 if ( input == CPUID_LEAF_0x1 )
910 {
911 /* mask off reserved bits */
912 ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
914 if ( !hvm_apic_support(v->domain) ||
915 !vlapic_global_enabled((VLAPIC(v))) )
916 {
917 /* Since the apic is disabled, avoid any
918 confusion about SMP cpus being available */
920 clear_bit(X86_FEATURE_APIC, &edx);
921 }
923 #if CONFIG_PAGING_LEVELS < 3
924 edx &= ~(bitmaskof(X86_FEATURE_PAE) |
925 bitmaskof(X86_FEATURE_PSE) |
926 bitmaskof(X86_FEATURE_PSE36));
927 #else
928 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L2 )
929 {
930 if ( v->domain->arch.hvm_domain.pae_enabled )
931 clear_bit(X86_FEATURE_PSE36, &edx);
932 else
933 {
934 clear_bit(X86_FEATURE_PAE, &edx);
935 clear_bit(X86_FEATURE_PSE, &edx);
936 clear_bit(X86_FEATURE_PSE36, &edx);
937 }
938 }
939 #endif
941 ebx &= NUM_THREADS_RESET_MASK;
943 /* Unsupportable for virtualised CPUs. */
944 ecx &= ~(bitmaskof(X86_FEATURE_VMXE) |
945 bitmaskof(X86_FEATURE_EST) |
946 bitmaskof(X86_FEATURE_TM2) |
947 bitmaskof(X86_FEATURE_CID) |
948 bitmaskof(X86_FEATURE_MWAIT) );
950 edx &= ~( bitmaskof(X86_FEATURE_HT) |
951 bitmaskof(X86_FEATURE_MCA) |
952 bitmaskof(X86_FEATURE_MCE) |
953 bitmaskof(X86_FEATURE_ACPI) |
954 bitmaskof(X86_FEATURE_ACC) );
955 }
956 else if ( ( input == CPUID_LEAF_0x6 )
957 || ( input == CPUID_LEAF_0x9 )
958 || ( input == CPUID_LEAF_0xA ))
959 {
960 eax = ebx = ecx = edx = 0x0;
961 }
962 #ifdef __i386__
963 else if ( input == CPUID_LEAF_0x80000001 )
964 {
965 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
967 clear_bit(X86_FEATURE_LM & 31, &edx);
968 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
969 }
970 #endif
971 }
973 regs->eax = (unsigned long) eax;
974 regs->ebx = (unsigned long) ebx;
975 regs->ecx = (unsigned long) ecx;
976 regs->edx = (unsigned long) edx;
978 HVM_DBG_LOG(DBG_LEVEL_3, "eip@%lx, input: 0x%lx, "
979 "output: eax = 0x%08lx, ebx = 0x%08lx, "
980 "ecx = 0x%08lx, edx = 0x%08lx",
981 (unsigned long)eip, (unsigned long)input,
982 (unsigned long)eax, (unsigned long)ebx,
983 (unsigned long)ecx, (unsigned long)edx);
984 }
986 #define CASE_GET_REG_P(REG, reg) \
987 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
989 #ifdef __i386__
990 #define CASE_EXTEND_GET_REG_P
991 #else
992 #define CASE_EXTEND_GET_REG_P \
993 CASE_GET_REG_P(R8, r8); \
994 CASE_GET_REG_P(R9, r9); \
995 CASE_GET_REG_P(R10, r10); \
996 CASE_GET_REG_P(R11, r11); \
997 CASE_GET_REG_P(R12, r12); \
998 CASE_GET_REG_P(R13, r13); \
999 CASE_GET_REG_P(R14, r14); \
1000 CASE_GET_REG_P(R15, r15)
1001 #endif
1003 static void vmx_dr_access(unsigned long exit_qualification,
1004 struct cpu_user_regs *regs)
1006 struct vcpu *v = current;
1008 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1010 /* We could probably be smarter about this */
1011 __restore_debug_registers(v);
1013 /* Allow guest direct access to DR registers */
1014 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_MOV_DR_EXITING;
1015 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
1016 v->arch.hvm_vcpu.u.vmx.exec_control);
1019 /*
1020 * Invalidate the TLB for va. Invalidate the shadow page corresponding
1021 * the address va.
1022 */
1023 static void vmx_vmexit_do_invlpg(unsigned long va)
1025 unsigned long eip;
1026 struct vcpu *v = current;
1028 __vmread(GUEST_RIP, &eip);
1030 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
1031 eip, va);
1033 /*
1034 * We do the safest things first, then try to update the shadow
1035 * copying from guest
1036 */
1037 shadow_invlpg(v, va);
1040 static int check_for_null_selector(unsigned long eip)
1042 unsigned char inst[MAX_INST_LEN];
1043 unsigned long sel;
1044 int i, inst_len;
1045 int inst_copy_from_guest(unsigned char *, unsigned long, int);
1047 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1048 memset(inst, 0, MAX_INST_LEN);
1049 if (inst_copy_from_guest(inst, eip, inst_len) != inst_len) {
1050 printf("check_for_null_selector: get guest instruction failed\n");
1051 domain_crash_synchronous();
1054 for (i = 0; i < inst_len; i++) {
1055 switch (inst[i]) {
1056 case 0xf3: /* REPZ */
1057 case 0xf2: /* REPNZ */
1058 case 0xf0: /* LOCK */
1059 case 0x66: /* data32 */
1060 case 0x67: /* addr32 */
1061 continue;
1062 case 0x2e: /* CS */
1063 __vmread(GUEST_CS_SELECTOR, &sel);
1064 break;
1065 case 0x36: /* SS */
1066 __vmread(GUEST_SS_SELECTOR, &sel);
1067 break;
1068 case 0x26: /* ES */
1069 __vmread(GUEST_ES_SELECTOR, &sel);
1070 break;
1071 case 0x64: /* FS */
1072 __vmread(GUEST_FS_SELECTOR, &sel);
1073 break;
1074 case 0x65: /* GS */
1075 __vmread(GUEST_GS_SELECTOR, &sel);
1076 break;
1077 case 0x3e: /* DS */
1078 /* FALLTHROUGH */
1079 default:
1080 /* DS is the default */
1081 __vmread(GUEST_DS_SELECTOR, &sel);
1083 return sel == 0 ? 1 : 0;
1086 return 0;
1089 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
1090 unsigned long count, int size, long value,
1091 int dir, int pvalid);
1093 static void vmx_io_instruction(unsigned long exit_qualification,
1094 unsigned long inst_len)
1096 struct cpu_user_regs *regs;
1097 struct hvm_io_op *pio_opp;
1098 unsigned long eip, cs, eflags;
1099 unsigned long port, size, dir;
1100 int vm86;
1102 pio_opp = &current->arch.hvm_vcpu.io_op;
1103 pio_opp->instr = INSTR_PIO;
1104 pio_opp->flags = 0;
1106 regs = &pio_opp->io_context;
1108 /* Copy current guest state into io instruction state structure. */
1109 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1111 __vmread(GUEST_RIP, &eip);
1112 __vmread(GUEST_CS_SELECTOR, &cs);
1113 __vmread(GUEST_RFLAGS, &eflags);
1114 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
1116 HVM_DBG_LOG(DBG_LEVEL_IO,
1117 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
1118 "exit_qualification = %lx",
1119 vm86, cs, eip, exit_qualification);
1121 if (test_bit(6, &exit_qualification))
1122 port = (exit_qualification >> 16) & 0xFFFF;
1123 else
1124 port = regs->edx & 0xffff;
1125 TRACE_VMEXIT(1, port);
1126 size = (exit_qualification & 7) + 1;
1127 dir = test_bit(3, &exit_qualification); /* direction */
1129 if (test_bit(4, &exit_qualification)) { /* string instruction */
1130 unsigned long addr, count = 1;
1131 int sign = regs->eflags & EF_DF ? -1 : 1;
1133 __vmread(GUEST_LINEAR_ADDRESS, &addr);
1135 /*
1136 * In protected mode, guest linear address is invalid if the
1137 * selector is null.
1138 */
1139 if (!vm86 && check_for_null_selector(eip))
1140 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
1142 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
1143 pio_opp->flags |= REPZ;
1144 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
1147 /*
1148 * Handle string pio instructions that cross pages or that
1149 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
1150 */
1151 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
1152 unsigned long value = 0;
1154 pio_opp->flags |= OVERLAP;
1155 if (dir == IOREQ_WRITE)
1156 hvm_copy(&value, addr, size, HVM_COPY_IN);
1157 send_pio_req(regs, port, 1, size, value, dir, 0);
1158 } else {
1159 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
1160 if (sign > 0)
1161 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1162 else
1163 count = (addr & ~PAGE_MASK) / size;
1164 } else
1165 __update_guest_eip(inst_len);
1167 send_pio_req(regs, port, count, size, addr, dir, 1);
1169 } else {
1170 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1171 hvm_print_line(current, regs->eax); /* guest debug output */
1173 __update_guest_eip(inst_len);
1174 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
1178 int
1179 vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
1181 unsigned long inst_len;
1182 int error = 0;
1184 error |= __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1185 error |= __vmread(GUEST_RIP, &c->eip);
1186 c->eip += inst_len; /* skip transition instruction */
1187 error |= __vmread(GUEST_RSP, &c->esp);
1188 error |= __vmread(GUEST_RFLAGS, &c->eflags);
1190 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
1191 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
1192 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
1194 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
1195 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
1197 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
1198 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
1200 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
1201 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
1202 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
1203 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
1205 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
1206 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
1207 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
1208 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
1210 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
1211 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
1212 error |= __vmread(GUEST_ES_BASE, &c->es_base);
1213 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
1215 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
1216 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
1217 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
1218 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
1220 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
1221 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
1222 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
1223 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
1225 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
1226 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
1227 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
1228 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
1230 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
1231 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
1232 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
1233 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
1235 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
1236 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
1237 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
1238 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
1240 return !error;
1243 int
1244 vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
1246 unsigned long mfn, old_cr4, old_base_mfn;
1247 int error = 0;
1249 error |= __vmwrite(GUEST_RIP, c->eip);
1250 error |= __vmwrite(GUEST_RSP, c->esp);
1251 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
1253 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
1255 if (!vmx_paging_enabled(v)) {
1256 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
1257 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
1258 goto skip_cr3;
1261 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
1262 /*
1263 * This is simple TLB flush, implying the guest has
1264 * removed some translation or changed page attributes.
1265 * We simply invalidate the shadow.
1266 */
1267 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1268 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1269 printk("Invalid CR3 value=%x", c->cr3);
1270 domain_crash_synchronous();
1271 return 0;
1273 shadow_sync_all(v->domain);
1274 } else {
1275 /*
1276 * If different, make a shadow. Check if the PDBR is valid
1277 * first.
1278 */
1279 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1280 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1281 printk("Invalid CR3 value=%x", c->cr3);
1282 domain_crash_synchronous();
1283 return 0;
1285 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1286 if(!get_page(mfn_to_page(mfn), v->domain))
1287 return 0;
1288 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1289 v->arch.guest_table = pagetable_from_pfn(mfn);
1290 if (old_base_mfn)
1291 put_page(mfn_to_page(old_base_mfn));
1292 /*
1293 * arch.shadow_table should now hold the next CR3 for shadow
1294 */
1295 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1296 update_pagetables(v);
1297 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1298 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1301 skip_cr3:
1303 error |= __vmread(CR4_READ_SHADOW, &old_cr4);
1304 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1305 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1307 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1308 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1310 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1311 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1313 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1314 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1315 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1316 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1318 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1319 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1320 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1321 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1323 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1324 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1325 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1326 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1328 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1329 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1330 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1331 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1333 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1334 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1335 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1336 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1338 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1339 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1340 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1341 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1343 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1344 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1345 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1346 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1348 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1349 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1350 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1351 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1353 return !error;
1356 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1358 int
1359 vmx_assist(struct vcpu *v, int mode)
1361 struct vmx_assist_context c;
1362 u32 magic;
1363 u32 cp;
1365 /* make sure vmxassist exists (this is not an error) */
1366 if (!hvm_copy(&magic, VMXASSIST_MAGIC_OFFSET, sizeof(magic), HVM_COPY_IN))
1367 return 0;
1368 if (magic != VMXASSIST_MAGIC)
1369 return 0;
1371 switch (mode) {
1372 /*
1373 * Transfer control to vmxassist.
1374 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1375 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1376 * by vmxassist and will transfer control to it.
1377 */
1378 case VMX_ASSIST_INVOKE:
1379 /* save the old context */
1380 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1381 goto error;
1382 if (cp != 0) {
1383 if (!vmx_world_save(v, &c))
1384 goto error;
1385 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_OUT))
1386 goto error;
1389 /* restore the new context, this should activate vmxassist */
1390 if (!hvm_copy(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp), HVM_COPY_IN))
1391 goto error;
1392 if (cp != 0) {
1393 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1394 goto error;
1395 if (!vmx_world_restore(v, &c))
1396 goto error;
1397 return 1;
1399 break;
1401 /*
1402 * Restore the VMXASSIST_OLD_CONTEXT that was saved by VMX_ASSIST_INVOKE
1403 * above.
1404 */
1405 case VMX_ASSIST_RESTORE:
1406 /* save the old context */
1407 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1408 goto error;
1409 if (cp != 0) {
1410 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1411 goto error;
1412 if (!vmx_world_restore(v, &c))
1413 goto error;
1414 return 1;
1416 break;
1419 error:
1420 printf("Failed to transfer to vmxassist\n");
1421 domain_crash_synchronous();
1422 return 0;
1425 static int vmx_set_cr0(unsigned long value)
1427 struct vcpu *v = current;
1428 unsigned long mfn;
1429 unsigned long eip;
1430 int paging_enabled;
1431 unsigned long vm_entry_value;
1432 unsigned long old_cr0;
1434 /*
1435 * CR0: We don't want to lose PE and PG.
1436 */
1437 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1438 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1440 /* TS cleared? Then initialise FPU now. */
1441 if ( !(value & X86_CR0_TS) )
1443 setup_fpu(v);
1444 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1447 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1448 __vmwrite(CR0_READ_SHADOW, value);
1450 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1452 if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
1454 /*
1455 * Trying to enable guest paging.
1456 * The guest CR3 must be pointing to the guest physical.
1457 */
1458 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1459 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1460 !get_page(mfn_to_page(mfn), v->domain) )
1462 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1463 domain_crash_synchronous(); /* need to take a clean path */
1466 #if defined(__x86_64__)
1467 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1468 &v->arch.hvm_vmx.cpu_state) &&
1469 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
1470 &v->arch.hvm_vmx.cpu_state) )
1472 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enabled\n");
1473 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1476 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1477 &v->arch.hvm_vmx.cpu_state) )
1479 /* Here the PAE is should be opened */
1480 HVM_DBG_LOG(DBG_LEVEL_1, "Enable long mode\n");
1481 set_bit(VMX_CPU_STATE_LMA_ENABLED,
1482 &v->arch.hvm_vmx.cpu_state);
1484 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1485 vm_entry_value |= VM_ENTRY_CONTROLS_IA32E_MODE;
1486 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1488 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L4) )
1490 printk("Unsupported guest paging levels\n");
1491 domain_crash_synchronous(); /* need to take a clean path */
1494 else
1495 #endif /* __x86_64__ */
1497 #if CONFIG_PAGING_LEVELS >= 3
1498 /* seems it's a 32-bit or 32-bit PAE guest */
1500 if ( test_bit(VMX_CPU_STATE_PAE_ENABLED,
1501 &v->arch.hvm_vmx.cpu_state) )
1503 /* The guest enables PAE first and then it enables PG, it is
1504 * really a PAE guest */
1505 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
1507 printk("Unsupported guest paging levels\n");
1508 domain_crash_synchronous();
1511 else
1513 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L2) )
1515 printk("Unsupported guest paging levels\n");
1516 domain_crash_synchronous(); /* need to take a clean path */
1519 #endif
1522 /*
1523 * Now arch.guest_table points to machine physical.
1524 */
1525 v->arch.guest_table = pagetable_from_pfn(mfn);
1526 update_pagetables(v);
1528 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1529 (unsigned long) (mfn << PAGE_SHIFT));
1531 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1532 /*
1533 * arch->shadow_table should hold the next CR3 for shadow
1534 */
1535 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1536 v->arch.hvm_vmx.cpu_cr3, mfn);
1539 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1540 if ( v->arch.hvm_vmx.cpu_cr3 ) {
1541 put_page(mfn_to_page(get_mfn_from_gpfn(
1542 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1543 v->arch.guest_table = pagetable_null();
1546 /*
1547 * VMX does not implement real-mode virtualization. We emulate
1548 * real-mode by performing a world switch to VMXAssist whenever
1549 * a partition disables the CR0.PE bit.
1550 */
1551 if ( (value & X86_CR0_PE) == 0 )
1553 if ( value & X86_CR0_PG ) {
1554 /* inject GP here */
1555 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1556 return 0;
1557 } else {
1558 /*
1559 * Disable paging here.
1560 * Same to PE == 1 && PG == 0
1561 */
1562 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED,
1563 &v->arch.hvm_vmx.cpu_state) )
1565 clear_bit(VMX_CPU_STATE_LMA_ENABLED,
1566 &v->arch.hvm_vmx.cpu_state);
1567 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1568 vm_entry_value &= ~VM_ENTRY_CONTROLS_IA32E_MODE;
1569 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1573 clear_all_shadow_status(v->domain);
1574 if ( vmx_assist(v, VMX_ASSIST_INVOKE) ) {
1575 set_bit(VMX_CPU_STATE_ASSIST_ENABLED, &v->arch.hvm_vmx.cpu_state);
1576 __vmread(GUEST_RIP, &eip);
1577 HVM_DBG_LOG(DBG_LEVEL_1,
1578 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1579 return 0; /* do not update eip! */
1581 } else if ( test_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1582 &v->arch.hvm_vmx.cpu_state) )
1584 __vmread(GUEST_RIP, &eip);
1585 HVM_DBG_LOG(DBG_LEVEL_1,
1586 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1587 if ( vmx_assist(v, VMX_ASSIST_RESTORE) )
1589 clear_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1590 &v->arch.hvm_vmx.cpu_state);
1591 __vmread(GUEST_RIP, &eip);
1592 HVM_DBG_LOG(DBG_LEVEL_1,
1593 "Restoring to %%eip 0x%lx\n", eip);
1594 return 0; /* do not update eip! */
1597 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1599 /* we should take care of this kind of situation */
1600 clear_all_shadow_status(v->domain);
1601 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
1604 return 1;
1607 #define CASE_SET_REG(REG, reg) \
1608 case REG_ ## REG: regs->reg = value; break
1609 #define CASE_GET_REG(REG, reg) \
1610 case REG_ ## REG: value = regs->reg; break
1612 #define CASE_EXTEND_SET_REG \
1613 CASE_EXTEND_REG(S)
1614 #define CASE_EXTEND_GET_REG \
1615 CASE_EXTEND_REG(G)
1617 #ifdef __i386__
1618 #define CASE_EXTEND_REG(T)
1619 #else
1620 #define CASE_EXTEND_REG(T) \
1621 CASE_ ## T ## ET_REG(R8, r8); \
1622 CASE_ ## T ## ET_REG(R9, r9); \
1623 CASE_ ## T ## ET_REG(R10, r10); \
1624 CASE_ ## T ## ET_REG(R11, r11); \
1625 CASE_ ## T ## ET_REG(R12, r12); \
1626 CASE_ ## T ## ET_REG(R13, r13); \
1627 CASE_ ## T ## ET_REG(R14, r14); \
1628 CASE_ ## T ## ET_REG(R15, r15)
1629 #endif
1631 /*
1632 * Write to control registers
1633 */
1634 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1636 unsigned long value;
1637 unsigned long old_cr;
1638 struct vcpu *v = current;
1640 switch ( gp ) {
1641 CASE_GET_REG(EAX, eax);
1642 CASE_GET_REG(ECX, ecx);
1643 CASE_GET_REG(EDX, edx);
1644 CASE_GET_REG(EBX, ebx);
1645 CASE_GET_REG(EBP, ebp);
1646 CASE_GET_REG(ESI, esi);
1647 CASE_GET_REG(EDI, edi);
1648 CASE_EXTEND_GET_REG;
1649 case REG_ESP:
1650 __vmread(GUEST_RSP, &value);
1651 break;
1652 default:
1653 printk("invalid gp: %d\n", gp);
1654 __hvm_bug(regs);
1657 HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
1659 switch ( cr ) {
1660 case 0:
1661 return vmx_set_cr0(value);
1662 case 3:
1664 unsigned long old_base_mfn, mfn;
1666 /*
1667 * If paging is not enabled yet, simply copy the value to CR3.
1668 */
1669 if (!vmx_paging_enabled(v)) {
1670 v->arch.hvm_vmx.cpu_cr3 = value;
1671 break;
1674 /*
1675 * We make a new one if the shadow does not exist.
1676 */
1677 if (value == v->arch.hvm_vmx.cpu_cr3) {
1678 /*
1679 * This is simple TLB flush, implying the guest has
1680 * removed some translation or changed page attributes.
1681 * We simply invalidate the shadow.
1682 */
1683 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1684 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1685 __hvm_bug(regs);
1686 shadow_sync_all(v->domain);
1687 } else {
1688 /*
1689 * If different, make a shadow. Check if the PDBR is valid
1690 * first.
1691 */
1692 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1693 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1694 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1695 !get_page(mfn_to_page(mfn), v->domain) )
1697 printk("Invalid CR3 value=%lx", value);
1698 domain_crash_synchronous(); /* need to take a clean path */
1700 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1701 v->arch.guest_table = pagetable_from_pfn(mfn);
1702 if (old_base_mfn)
1703 put_page(mfn_to_page(old_base_mfn));
1704 /*
1705 * arch.shadow_table should now hold the next CR3 for shadow
1706 */
1707 #if CONFIG_PAGING_LEVELS >= 3
1708 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L3 )
1709 shadow_sync_all(v->domain);
1710 #endif
1712 v->arch.hvm_vmx.cpu_cr3 = value;
1713 update_pagetables(v);
1714 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1715 value);
1716 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1718 break;
1720 case 4: /* CR4 */
1722 __vmread(CR4_READ_SHADOW, &old_cr);
1724 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1726 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1728 if ( vmx_pgbit_test(v) )
1730 /* The guest is a 32-bit PAE guest. */
1731 #if CONFIG_PAGING_LEVELS >= 3
1732 unsigned long mfn, old_base_mfn;
1734 if( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
1736 printk("Unsupported guest paging levels\n");
1737 domain_crash_synchronous(); /* need to take a clean path */
1740 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1741 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1742 !get_page(mfn_to_page(mfn), v->domain) )
1744 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1745 domain_crash_synchronous(); /* need to take a clean path */
1748 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1749 if ( old_base_mfn )
1750 put_page(mfn_to_page(old_base_mfn));
1752 /*
1753 * Now arch.guest_table points to machine physical.
1754 */
1756 v->arch.guest_table = pagetable_from_pfn(mfn);
1757 update_pagetables(v);
1759 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1760 (unsigned long) (mfn << PAGE_SHIFT));
1762 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1764 /*
1765 * arch->shadow_table should hold the next CR3 for shadow
1766 */
1768 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1769 v->arch.hvm_vmx.cpu_cr3, mfn);
1770 #endif
1772 else
1774 /* The guest is a 64 bit or 32-bit PAE guest. */
1775 #if CONFIG_PAGING_LEVELS >= 3
1776 if ( (v->domain->arch.ops != NULL) &&
1777 v->domain->arch.ops->guest_paging_levels == PAGING_L2)
1779 /* Seems the guest first enables PAE without enabling PG,
1780 * it must enable PG after that, and it is a 32-bit PAE
1781 * guest */
1783 if ( !shadow_set_guest_paging_levels(v->domain,
1784 PAGING_L3) )
1786 printk("Unsupported guest paging levels\n");
1787 /* need to take a clean path */
1788 domain_crash_synchronous();
1791 #endif
1794 else if ( value & X86_CR4_PAE )
1795 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1796 else
1798 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED, &v->arch.hvm_vmx.cpu_state) )
1799 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1801 clear_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1804 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1805 __vmwrite(CR4_READ_SHADOW, value);
1807 /*
1808 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1809 * all TLB entries except global entries.
1810 */
1811 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1812 shadow_sync_all(v->domain);
1814 break;
1816 default:
1817 printk("invalid cr: %d\n", gp);
1818 __hvm_bug(regs);
1821 return 1;
1824 /*
1825 * Read from control registers. CR0 and CR4 are read from the shadow.
1826 */
1827 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1829 unsigned long value;
1830 struct vcpu *v = current;
1832 if ( cr != 3 )
1833 __hvm_bug(regs);
1835 value = (unsigned long) v->arch.hvm_vmx.cpu_cr3;
1837 switch ( gp ) {
1838 CASE_SET_REG(EAX, eax);
1839 CASE_SET_REG(ECX, ecx);
1840 CASE_SET_REG(EDX, edx);
1841 CASE_SET_REG(EBX, ebx);
1842 CASE_SET_REG(EBP, ebp);
1843 CASE_SET_REG(ESI, esi);
1844 CASE_SET_REG(EDI, edi);
1845 CASE_EXTEND_SET_REG;
1846 case REG_ESP:
1847 __vmwrite(GUEST_RSP, value);
1848 regs->esp = value;
1849 break;
1850 default:
1851 printk("invalid gp: %d\n", gp);
1852 __hvm_bug(regs);
1855 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
1858 static int vmx_cr_access(unsigned long exit_qualification, struct cpu_user_regs *regs)
1860 unsigned int gp, cr;
1861 unsigned long value;
1862 struct vcpu *v = current;
1864 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1865 case TYPE_MOV_TO_CR:
1866 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1867 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1868 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1869 TRACE_VMEXIT(2,cr);
1870 TRACE_VMEXIT(3,gp);
1871 return mov_to_cr(gp, cr, regs);
1872 case TYPE_MOV_FROM_CR:
1873 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1874 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1875 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1876 TRACE_VMEXIT(2,cr);
1877 TRACE_VMEXIT(3,gp);
1878 mov_from_cr(cr, gp, regs);
1879 break;
1880 case TYPE_CLTS:
1881 TRACE_VMEXIT(1,TYPE_CLTS);
1883 /* We initialise the FPU now, to avoid needing another vmexit. */
1884 setup_fpu(v);
1885 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1887 __vmread_vcpu(v, GUEST_CR0, &value);
1888 value &= ~X86_CR0_TS; /* clear TS */
1889 __vmwrite(GUEST_CR0, value);
1891 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1892 value &= ~X86_CR0_TS; /* clear TS */
1893 __vmwrite(CR0_READ_SHADOW, value);
1894 break;
1895 case TYPE_LMSW:
1896 TRACE_VMEXIT(1,TYPE_LMSW);
1897 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1898 value = (value & ~0xF) |
1899 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1900 return vmx_set_cr0(value);
1901 break;
1902 default:
1903 __hvm_bug(regs);
1904 break;
1906 return 1;
1909 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1911 u64 msr_content = 0;
1912 u32 eax, edx;
1913 struct vcpu *v = current;
1915 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1916 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1917 (unsigned long)regs->edx);
1918 switch (regs->ecx) {
1919 case MSR_IA32_TIME_STAMP_COUNTER:
1920 msr_content = hvm_get_guest_time(v);
1921 break;
1922 case MSR_IA32_SYSENTER_CS:
1923 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1924 break;
1925 case MSR_IA32_SYSENTER_ESP:
1926 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1927 break;
1928 case MSR_IA32_SYSENTER_EIP:
1929 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1930 break;
1931 case MSR_IA32_APICBASE:
1932 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1933 break;
1934 default:
1935 if (long_mode_do_msr_read(regs))
1936 return;
1938 if ( rdmsr_hypervisor_regs(regs->ecx, &eax, &edx) )
1940 regs->eax = eax;
1941 regs->edx = edx;
1942 return;
1945 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1946 break;
1949 regs->eax = msr_content & 0xFFFFFFFF;
1950 regs->edx = msr_content >> 32;
1952 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1953 "ecx=%lx, eax=%lx, edx=%lx",
1954 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1955 (unsigned long)regs->edx);
1958 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1960 u64 msr_content;
1961 struct vcpu *v = current;
1963 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1964 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1965 (unsigned long)regs->edx);
1967 msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
1969 switch (regs->ecx) {
1970 case MSR_IA32_TIME_STAMP_COUNTER:
1971 set_guest_time(v, msr_content);
1972 break;
1973 case MSR_IA32_SYSENTER_CS:
1974 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1975 break;
1976 case MSR_IA32_SYSENTER_ESP:
1977 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1978 break;
1979 case MSR_IA32_SYSENTER_EIP:
1980 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1981 break;
1982 case MSR_IA32_APICBASE:
1983 vlapic_msr_set(VLAPIC(v), msr_content);
1984 break;
1985 default:
1986 if ( !long_mode_do_msr_write(regs) )
1987 wrmsr_hypervisor_regs(regs->ecx, regs->eax, regs->edx);
1988 break;
1991 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1992 "ecx=%lx, eax=%lx, edx=%lx",
1993 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1994 (unsigned long)regs->edx);
1997 /*
1998 * Need to use this exit to reschedule
1999 */
2000 void vmx_vmexit_do_hlt(void)
2002 struct vcpu *v=current;
2003 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
2004 s_time_t next_pit=-1,next_wakeup;
2006 if ( !v->vcpu_id )
2007 next_pit = get_scheduled(v, pt->irq, pt);
2008 next_wakeup = get_apictime_scheduled(v);
2009 if ( (next_pit != -1 && next_pit < next_wakeup) || next_wakeup == -1 )
2010 next_wakeup = next_pit;
2011 if ( next_wakeup != - 1 )
2012 set_timer(&current->arch.hvm_vmx.hlt_timer, next_wakeup);
2013 hvm_safe_block();
2016 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
2018 unsigned int vector;
2019 int error;
2021 asmlinkage void do_IRQ(struct cpu_user_regs *);
2022 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
2023 fastcall void smp_event_check_interrupt(void);
2024 fastcall void smp_invalidate_interrupt(void);
2025 fastcall void smp_call_function_interrupt(void);
2026 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
2027 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
2028 #ifdef CONFIG_X86_MCE_P4THERMAL
2029 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
2030 #endif
2032 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
2033 && !(vector & INTR_INFO_VALID_MASK))
2034 __hvm_bug(regs);
2036 vector &= INTR_INFO_VECTOR_MASK;
2037 TRACE_VMEXIT(1,vector);
2039 switch(vector) {
2040 case LOCAL_TIMER_VECTOR:
2041 smp_apic_timer_interrupt(regs);
2042 break;
2043 case EVENT_CHECK_VECTOR:
2044 smp_event_check_interrupt();
2045 break;
2046 case INVALIDATE_TLB_VECTOR:
2047 smp_invalidate_interrupt();
2048 break;
2049 case CALL_FUNCTION_VECTOR:
2050 smp_call_function_interrupt();
2051 break;
2052 case SPURIOUS_APIC_VECTOR:
2053 smp_spurious_interrupt(regs);
2054 break;
2055 case ERROR_APIC_VECTOR:
2056 smp_error_interrupt(regs);
2057 break;
2058 #ifdef CONFIG_X86_MCE_P4THERMAL
2059 case THERMAL_APIC_VECTOR:
2060 smp_thermal_interrupt(regs);
2061 break;
2062 #endif
2063 default:
2064 regs->entry_vector = vector;
2065 do_IRQ(regs);
2066 break;
2070 #if defined (__x86_64__)
2071 void store_cpu_user_regs(struct cpu_user_regs *regs)
2073 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2074 __vmread(GUEST_RSP, &regs->rsp);
2075 __vmread(GUEST_RFLAGS, &regs->rflags);
2076 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2077 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2078 __vmread(GUEST_ES_SELECTOR, &regs->es);
2079 __vmread(GUEST_RIP, &regs->rip);
2081 #elif defined (__i386__)
2082 void store_cpu_user_regs(struct cpu_user_regs *regs)
2084 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2085 __vmread(GUEST_RSP, &regs->esp);
2086 __vmread(GUEST_RFLAGS, &regs->eflags);
2087 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2088 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2089 __vmread(GUEST_ES_SELECTOR, &regs->es);
2090 __vmread(GUEST_RIP, &regs->eip);
2092 #endif
2094 #ifdef XEN_DEBUGGER
2095 void save_cpu_user_regs(struct cpu_user_regs *regs)
2097 __vmread(GUEST_SS_SELECTOR, &regs->xss);
2098 __vmread(GUEST_RSP, &regs->esp);
2099 __vmread(GUEST_RFLAGS, &regs->eflags);
2100 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
2101 __vmread(GUEST_RIP, &regs->eip);
2103 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
2104 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
2105 __vmread(GUEST_ES_SELECTOR, &regs->xes);
2106 __vmread(GUEST_DS_SELECTOR, &regs->xds);
2109 void restore_cpu_user_regs(struct cpu_user_regs *regs)
2111 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
2112 __vmwrite(GUEST_RSP, regs->esp);
2113 __vmwrite(GUEST_RFLAGS, regs->eflags);
2114 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
2115 __vmwrite(GUEST_RIP, regs->eip);
2117 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
2118 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
2119 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
2120 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
2122 #endif
2124 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs regs)
2126 unsigned int exit_reason;
2127 unsigned long exit_qualification, eip, inst_len = 0;
2128 struct vcpu *v = current;
2129 int error;
2131 error = __vmread(VM_EXIT_REASON, &exit_reason);
2132 BUG_ON(error);
2134 perfc_incra(vmexits, exit_reason);
2136 if ( (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT) &&
2137 (exit_reason != EXIT_REASON_VMCALL) &&
2138 (exit_reason != EXIT_REASON_IO_INSTRUCTION) )
2139 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
2141 if ( exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT )
2142 local_irq_enable();
2144 if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
2146 unsigned int failed_vmentry_reason = exit_reason & 0xFFFF;
2148 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2149 printk("Failed vm entry (exit reason 0x%x) ", exit_reason);
2150 switch ( failed_vmentry_reason ) {
2151 case EXIT_REASON_INVALID_GUEST_STATE:
2152 printk("caused by invalid guest state (%ld).\n", exit_qualification);
2153 break;
2154 case EXIT_REASON_MSR_LOADING:
2155 printk("caused by MSR entry %ld loading.\n", exit_qualification);
2156 break;
2157 case EXIT_REASON_MACHINE_CHECK:
2158 printk("caused by machine check.\n");
2159 break;
2160 default:
2161 printk("reason not known yet!");
2162 break;
2165 printk("************* VMCS Area **************\n");
2166 vmcs_dump_vcpu();
2167 printk("**************************************\n");
2168 domain_crash_synchronous();
2171 __vmread(GUEST_RIP, &eip);
2172 TRACE_VMEXIT(0,exit_reason);
2174 switch ( exit_reason )
2176 case EXIT_REASON_EXCEPTION_NMI:
2178 /*
2179 * We don't set the software-interrupt exiting (INT n).
2180 * (1) We can get an exception (e.g. #PG) in the guest, or
2181 * (2) NMI
2182 */
2183 int error;
2184 unsigned int vector;
2185 unsigned long va;
2187 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
2188 || !(vector & INTR_INFO_VALID_MASK))
2189 __hvm_bug(&regs);
2190 vector &= INTR_INFO_VECTOR_MASK;
2192 TRACE_VMEXIT(1,vector);
2193 perfc_incra(cause_vector, vector);
2195 switch (vector) {
2196 #ifdef XEN_DEBUGGER
2197 case TRAP_debug:
2199 save_cpu_user_regs(&regs);
2200 pdb_handle_exception(1, &regs, 1);
2201 restore_cpu_user_regs(&regs);
2202 break;
2204 case TRAP_int3:
2206 save_cpu_user_regs(&regs);
2207 pdb_handle_exception(3, &regs, 1);
2208 restore_cpu_user_regs(&regs);
2209 break;
2211 #else
2212 case TRAP_debug:
2214 void store_cpu_user_regs(struct cpu_user_regs *regs);
2216 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2218 store_cpu_user_regs(&regs);
2219 domain_pause_for_debugger();
2220 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2221 PENDING_DEBUG_EXC_BS);
2223 else
2225 vmx_reflect_exception(v);
2226 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2227 PENDING_DEBUG_EXC_BS);
2230 break;
2232 case TRAP_int3:
2234 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2235 domain_pause_for_debugger();
2236 else
2237 vmx_reflect_exception(v);
2238 break;
2240 #endif
2241 case TRAP_no_device:
2243 vmx_do_no_device_fault();
2244 break;
2246 case TRAP_page_fault:
2248 __vmread(EXIT_QUALIFICATION, &va);
2249 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs.error_code);
2251 TRACE_VMEXIT(3,regs.error_code);
2252 TRACE_VMEXIT(4,va);
2254 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2255 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2256 (unsigned long)regs.eax, (unsigned long)regs.ebx,
2257 (unsigned long)regs.ecx, (unsigned long)regs.edx,
2258 (unsigned long)regs.esi, (unsigned long)regs.edi);
2260 if (!(error = vmx_do_page_fault(va, &regs))) {
2261 /*
2262 * Inject #PG using Interruption-Information Fields
2263 */
2264 vmx_inject_hw_exception(v, TRAP_page_fault, regs.error_code);
2265 v->arch.hvm_vmx.cpu_cr2 = va;
2266 TRACE_3D(TRC_VMX_INT, v->domain->domain_id, TRAP_page_fault, va);
2268 break;
2270 case TRAP_nmi:
2271 do_nmi(&regs);
2272 break;
2273 default:
2274 vmx_reflect_exception(v);
2275 break;
2277 break;
2279 case EXIT_REASON_EXTERNAL_INTERRUPT:
2280 vmx_vmexit_do_extint(&regs);
2281 break;
2282 case EXIT_REASON_PENDING_INTERRUPT:
2283 /*
2284 * Not sure exactly what the purpose of this is. The only bits set
2285 * and cleared at this point are CPU_BASED_VIRTUAL_INTR_PENDING.
2286 * (in io.c:{enable,disable}_irq_window(). So presumably we want to
2287 * set it to the original value...
2288 */
2289 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2290 v->arch.hvm_vcpu.u.vmx.exec_control |=
2291 (MONITOR_CPU_BASED_EXEC_CONTROLS & CPU_BASED_VIRTUAL_INTR_PENDING);
2292 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
2293 v->arch.hvm_vcpu.u.vmx.exec_control);
2294 break;
2295 case EXIT_REASON_TASK_SWITCH:
2296 __hvm_bug(&regs);
2297 break;
2298 case EXIT_REASON_CPUID:
2299 vmx_vmexit_do_cpuid(&regs);
2300 __get_instruction_length(inst_len);
2301 __update_guest_eip(inst_len);
2302 break;
2303 case EXIT_REASON_HLT:
2304 __get_instruction_length(inst_len);
2305 __update_guest_eip(inst_len);
2306 vmx_vmexit_do_hlt();
2307 break;
2308 case EXIT_REASON_INVLPG:
2310 unsigned long va;
2312 __vmread(EXIT_QUALIFICATION, &va);
2313 vmx_vmexit_do_invlpg(va);
2314 __get_instruction_length(inst_len);
2315 __update_guest_eip(inst_len);
2316 break;
2318 case EXIT_REASON_VMCALL:
2320 __get_instruction_length(inst_len);
2321 __vmread(GUEST_RIP, &eip);
2322 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2324 hvm_do_hypercall(&regs);
2325 __update_guest_eip(inst_len);
2326 break;
2328 case EXIT_REASON_CR_ACCESS:
2330 __vmread(GUEST_RIP, &eip);
2331 __get_instruction_length(inst_len);
2332 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2334 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx, inst_len =%lx, exit_qualification = %lx",
2335 eip, inst_len, exit_qualification);
2336 if (vmx_cr_access(exit_qualification, &regs))
2337 __update_guest_eip(inst_len);
2338 TRACE_VMEXIT(3,regs.error_code);
2339 TRACE_VMEXIT(4,exit_qualification);
2340 break;
2342 case EXIT_REASON_DR_ACCESS:
2343 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2344 vmx_dr_access(exit_qualification, &regs);
2345 __get_instruction_length(inst_len);
2346 __update_guest_eip(inst_len);
2347 break;
2348 case EXIT_REASON_IO_INSTRUCTION:
2349 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2350 __get_instruction_length(inst_len);
2351 vmx_io_instruction(exit_qualification, inst_len);
2352 TRACE_VMEXIT(4,exit_qualification);
2353 break;
2354 case EXIT_REASON_MSR_READ:
2355 __get_instruction_length(inst_len);
2356 vmx_do_msr_read(&regs);
2357 __update_guest_eip(inst_len);
2358 break;
2359 case EXIT_REASON_MSR_WRITE:
2360 __vmread(GUEST_RIP, &eip);
2361 vmx_do_msr_write(&regs);
2362 __get_instruction_length(inst_len);
2363 __update_guest_eip(inst_len);
2364 break;
2365 case EXIT_REASON_MWAIT_INSTRUCTION:
2366 __hvm_bug(&regs);
2367 break;
2368 case EXIT_REASON_VMCLEAR:
2369 case EXIT_REASON_VMLAUNCH:
2370 case EXIT_REASON_VMPTRLD:
2371 case EXIT_REASON_VMPTRST:
2372 case EXIT_REASON_VMREAD:
2373 case EXIT_REASON_VMRESUME:
2374 case EXIT_REASON_VMWRITE:
2375 case EXIT_REASON_VMOFF:
2376 case EXIT_REASON_VMON:
2377 /* Report invalid opcode exception when a VMX guest tries to execute
2378 any of the VMX instructions */
2379 vmx_inject_hw_exception(v, TRAP_invalid_op, VMX_DELIVER_NO_ERROR_CODE);
2380 break;
2382 default:
2383 __hvm_bug(&regs); /* should not happen */
2387 asmlinkage void vmx_load_cr2(void)
2389 struct vcpu *v = current;
2391 local_irq_disable();
2392 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2395 asmlinkage void vmx_trace_vmentry (void)
2397 TRACE_5D(TRC_VMX_VMENTRY,
2398 trace_values[smp_processor_id()][0],
2399 trace_values[smp_processor_id()][1],
2400 trace_values[smp_processor_id()][2],
2401 trace_values[smp_processor_id()][3],
2402 trace_values[smp_processor_id()][4]);
2403 TRACE_VMEXIT(0,9);
2404 TRACE_VMEXIT(1,9);
2405 TRACE_VMEXIT(2,9);
2406 TRACE_VMEXIT(3,9);
2407 TRACE_VMEXIT(4,9);
2408 return;
2411 asmlinkage void vmx_trace_vmexit (void)
2413 TRACE_3D(TRC_VMX_VMEXIT,0,0,0);
2414 return;
2417 /*
2418 * Local variables:
2419 * mode: C
2420 * c-set-style: "BSD"
2421 * c-basic-offset: 4
2422 * tab-width: 4
2423 * indent-tabs-mode: nil
2424 * End:
2425 */