ia64/xen-unstable

view xen/arch/ia64/xen/relocate_kernel.S @ 18135:01a3bba6b96d

[IA64] typo in relocate_new_kernel.

typo in relocate_new_kernel.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jul 28 17:29:09 2008 +0900 (2008-07-28)
parents 0b20ac6ec64a
children
line source
1 /*
2 * arch/ia64/kernel/relocate_kernel.S
3 *
4 * Relocate kexec'able kernel and start it
5 *
6 * Copyright (C) 2005 Hewlett-Packard Development Company, L.P.
7 * Copyright (C) 2005 Khalid Aziz <khalid.aziz@hp.com>
8 * Copyright (C) 2005 Intel Corp, Zou Nan hai <nanhai.zou@intel.com>
9 *
10 * This source code is licensed under the GNU General Public License,
11 * Version 2. See the file COPYING for more details.
12 */
13 #include <asm/asmmacro.h>
14 #include <asm/kregs.h>
15 #include <asm/page.h>
16 #include <asm/pgtable.h>
17 #include <asm/mca_asm.h>
19 /* relocate_new_kernel
20 *
21 * Do all the unpinning here, as the hypervisor has all the relevant
22 * variables and constants. Then go into the reboot_code_buffer to
23 * relocaate the new kernel and then branch into purgatory.
24 *
25 * Based on ia64_jump_to_sal
26 *
27 * in0: indirection_page
28 * in1: start_address
29 * in2: boot_param
30 * in3: dom0_relocate_new_kernel
31 */
32 GLOBAL_ENTRY(relocate_new_kernel)
33 .prologue
34 alloc r31=ar.pfs,4,0,4,0
35 .body
36 rsm psr.i | psr.ic
37 {
38 flushrs
39 srlz.i
40 }
41 movl r18=tlb_purge_done;;
42 DATA_VA_TO_PA(r18);;
43 mov b1=r18 // Return location
44 movl r18=ia64_do_tlb_purge;;
45 DATA_VA_TO_PA(r18);;
46 mov b2=r18 // doing tlb_flush work
47 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
48 movl r17=1f;;
49 DATA_VA_TO_PA(r17);;
50 mov cr.iip=r17
51 movl r16=IA64_PSR_AC|IA64_PSR_BN|IA64_PSR_IC;;
52 mov cr.ipsr=r16
53 mov cr.ifs=r0;;
54 rfi;;
55 1:
56 /* Invalidate all TLB data/inst */
57 br.sptk.many b2;; // jump to tlb purge code
59 tlb_purge_done:
60 mov out0=in0 // out3 is ignored and thus can be garbage
61 mov out1=in1
62 mov out2=in2
63 mov b1=in3
64 ;;
65 br.sptk.many b1;; // jump to dom0-supplied relocate_new_kernel
67 /* We should never get here */
68 END(relocate_new_kernel)
70 GLOBAL_ENTRY(ia64_dump_cpu_regs)
71 .prologue
72 alloc loc0=ar.pfs,1,2,0,0
73 .body
74 mov ar.rsc=0 // put RSE in enforced lazy mode
75 add loc1=4*8, in0 // save r4 and r5 first
76 ;;
77 {
78 flushrs // flush dirty regs to backing store
79 srlz.i
80 }
81 st8 [loc1]=r4, 8
82 ;;
83 st8 [loc1]=r5, 8
84 ;;
85 add loc1=32*8, in0
86 mov r4=ar.rnat
87 ;;
88 st8 [in0]=r0, 8 // r0
89 st8 [loc1]=r4, 8 // rnat
90 mov r5=pr
91 ;;
92 st8 [in0]=r1, 8 // r1
93 st8 [loc1]=r5, 8 // pr
94 mov r4=b0
95 ;;
96 st8 [in0]=r2, 8 // r2
97 st8 [loc1]=r4, 8 // b0
98 mov r5=b1;
99 ;;
100 st8 [in0]=r3, 24 // r3
101 st8 [loc1]=r5, 8 // b1
102 mov r4=b2
103 ;;
104 st8 [in0]=r6, 8 // r6
105 st8 [loc1]=r4, 8 // b2
106 mov r5=b3
107 ;;
108 st8 [in0]=r7, 8 // r7
109 st8 [loc1]=r5, 8 // b3
110 mov r4=b4
111 ;;
112 st8 [in0]=r8, 8 // r8
113 st8 [loc1]=r4, 8 // b4
114 mov r5=b5
115 ;;
116 st8 [in0]=r9, 8 // r9
117 st8 [loc1]=r5, 8 // b5
118 mov r4=b6
119 ;;
120 st8 [in0]=r10, 8 // r10
121 st8 [loc1]=r5, 8 // b6
122 mov r5=b7
123 ;;
124 st8 [in0]=r11, 8 // r11
125 st8 [loc1]=r5, 8 // b7
126 mov r4=b0
127 ;;
128 st8 [in0]=r12, 8 // r12
129 st8 [loc1]=r4, 8 // ip
130 mov r5=loc0
131 ;;
132 st8 [in0]=r13, 8 // r13
133 extr.u r5=r5, 0, 38 // ar.pfs.pfm
134 mov r4=r0 // user mask
135 ;;
136 st8 [in0]=r14, 8 // r14
137 st8 [loc1]=r5, 8 // cfm
138 ;;
139 st8 [in0]=r15, 8 // r15
140 st8 [loc1]=r4, 8 // user mask
141 mov r5=ar.rsc
142 ;;
143 st8 [in0]=r16, 8 // r16
144 st8 [loc1]=r5, 8 // ar.rsc
145 mov r4=ar.bsp
146 ;;
147 st8 [in0]=r17, 8 // r17
148 st8 [loc1]=r4, 8 // ar.bsp
149 mov r5=ar.bspstore
150 ;;
151 st8 [in0]=r18, 8 // r18
152 st8 [loc1]=r5, 8 // ar.bspstore
153 mov r4=ar.rnat
154 ;;
155 st8 [in0]=r19, 8 // r19
156 st8 [loc1]=r4, 8 // ar.rnat
157 mov r5=ar.ccv
158 ;;
159 st8 [in0]=r20, 8 // r20
160 st8 [loc1]=r5, 8 // ar.ccv
161 mov r4=ar.unat
162 ;;
163 st8 [in0]=r21, 8 // r21
164 st8 [loc1]=r4, 8 // ar.unat
165 mov r5 = ar.fpsr
166 ;;
167 st8 [in0]=r22, 8 // r22
168 st8 [loc1]=r5, 8 // ar.fpsr
169 mov r4 = ar.unat
170 ;;
171 st8 [in0]=r23, 8 // r23
172 st8 [loc1]=r4, 8 // unat
173 mov r5 = ar.fpsr
174 ;;
175 st8 [in0]=r24, 8 // r24
176 st8 [loc1]=r5, 8 // fpsr
177 mov r4 = ar.pfs
178 ;;
179 st8 [in0]=r25, 8 // r25
180 st8 [loc1]=r4, 8 // ar.pfs
181 mov r5 = ar.lc
182 ;;
183 st8 [in0]=r26, 8 // r26
184 st8 [loc1]=r5, 8 // ar.lc
185 mov r4 = ar.ec
186 ;;
187 st8 [in0]=r27, 8 // r27
188 st8 [loc1]=r4, 8 // ar.ec
189 mov r5 = ar.csd
190 ;;
191 st8 [in0]=r28, 8 // r28
192 st8 [loc1]=r5, 8 // ar.csd
193 mov r4 = ar.ssd
194 ;;
195 st8 [in0]=r29, 8 // r29
196 st8 [loc1]=r4, 8 // ar.ssd
197 ;;
198 st8 [in0]=r30, 8 // r30
199 ;;
200 st8 [in0]=r31, 8 // r31
201 mov ar.pfs=loc0
202 ;;
203 br.ret.sptk.many rp
204 END(ia64_dump_cpu_regs)