ia64/xen-unstable

view xen/arch/x86/smp.c @ 17181:017927162815

x86: On CPU shutdown, clear pending FPU exceptions.
I've seen at least one BIOS which fails warm reboot if FPU exceptions
are pending.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Mar 04 10:33:50 2008 +0000 (2008-03-04)
parents 00fec8212ae6
children a5319f23db7c
line source
1 /*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * This code is released under the GNU General Public License version 2 or
8 * later.
9 */
11 #include <xen/config.h>
12 #include <xen/irq.h>
13 #include <xen/sched.h>
14 #include <xen/delay.h>
15 #include <xen/perfc.h>
16 #include <xen/spinlock.h>
17 #include <asm/current.h>
18 #include <asm/smp.h>
19 #include <asm/mc146818rtc.h>
20 #include <asm/flushtlb.h>
21 #include <asm/hardirq.h>
22 #include <asm/ipi.h>
23 #include <asm/hvm/support.h>
24 #include <mach_apic.h>
26 /*
27 * Some notes on x86 processor bugs affecting SMP operation:
28 *
29 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
30 * The Linux implications for SMP are handled as follows:
31 *
32 * Pentium III / [Xeon]
33 * None of the E1AP-E3AP errata are visible to the user.
34 *
35 * E1AP. see PII A1AP
36 * E2AP. see PII A2AP
37 * E3AP. see PII A3AP
38 *
39 * Pentium II / [Xeon]
40 * None of the A1AP-A3AP errata are visible to the user.
41 *
42 * A1AP. see PPro 1AP
43 * A2AP. see PPro 2AP
44 * A3AP. see PPro 7AP
45 *
46 * Pentium Pro
47 * None of 1AP-9AP errata are visible to the normal user,
48 * except occasional delivery of 'spurious interrupt' as trap #15.
49 * This is very rare and a non-problem.
50 *
51 * 1AP. Linux maps APIC as non-cacheable
52 * 2AP. worked around in hardware
53 * 3AP. fixed in C0 and above steppings microcode update.
54 * Linux does not use excessive STARTUP_IPIs.
55 * 4AP. worked around in hardware
56 * 5AP. symmetric IO mode (normal Linux operation) not affected.
57 * 'noapic' mode has vector 0xf filled out properly.
58 * 6AP. 'noapic' mode might be affected - fixed in later steppings
59 * 7AP. We do not assume writes to the LVT deassering IRQs
60 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
61 * 9AP. We do not use mixed mode
62 */
64 /*
65 * The following functions deal with sending IPIs between CPUs.
66 */
68 static inline int __prepare_ICR (unsigned int shortcut, int vector)
69 {
70 return APIC_DM_FIXED | shortcut | vector;
71 }
73 static inline int __prepare_ICR2 (unsigned int mask)
74 {
75 return SET_APIC_DEST_FIELD(mask);
76 }
78 static inline void check_IPI_mask(cpumask_t cpumask)
79 {
80 /*
81 * Sanity, and necessary. An IPI with no target generates a send accept
82 * error with Pentium and P6 APICs.
83 */
84 ASSERT(cpus_subset(cpumask, cpu_online_map));
85 ASSERT(!cpus_empty(cpumask));
86 }
88 void apic_wait_icr_idle(void)
89 {
90 while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
91 cpu_relax();
92 }
94 void send_IPI_mask_flat(cpumask_t cpumask, int vector)
95 {
96 unsigned long mask = cpus_addr(cpumask)[0];
97 unsigned long cfg;
98 unsigned long flags;
100 check_IPI_mask(cpumask);
102 local_irq_save(flags);
104 /*
105 * Wait for idle.
106 */
107 apic_wait_icr_idle();
109 /*
110 * prepare target chip field
111 */
112 cfg = __prepare_ICR2(mask);
113 apic_write_around(APIC_ICR2, cfg);
115 /*
116 * program the ICR
117 */
118 cfg = __prepare_ICR(0, vector) | APIC_DEST_LOGICAL;
120 /*
121 * Send the IPI. The write to APIC_ICR fires this off.
122 */
123 apic_write_around(APIC_ICR, cfg);
125 local_irq_restore(flags);
126 }
128 void send_IPI_mask_phys(cpumask_t mask, int vector)
129 {
130 unsigned long cfg, flags;
131 unsigned int query_cpu;
133 check_IPI_mask(mask);
135 /*
136 * Hack. The clustered APIC addressing mode doesn't allow us to send
137 * to an arbitrary mask, so I do a unicasts to each CPU instead. This
138 * should be modified to do 1 message per cluster ID - mbligh
139 */
141 local_irq_save(flags);
143 for_each_cpu_mask( query_cpu, mask )
144 {
145 /*
146 * Wait for idle.
147 */
148 apic_wait_icr_idle();
150 /*
151 * prepare target chip field
152 */
153 cfg = __prepare_ICR2(cpu_physical_id(query_cpu));
154 apic_write_around(APIC_ICR2, cfg);
156 /*
157 * program the ICR
158 */
159 cfg = __prepare_ICR(0, vector) | APIC_DEST_PHYSICAL;
161 /*
162 * Send the IPI. The write to APIC_ICR fires this off.
163 */
164 apic_write_around(APIC_ICR, cfg);
165 }
167 local_irq_restore(flags);
168 }
170 static DEFINE_SPINLOCK(flush_lock);
171 static cpumask_t flush_cpumask;
172 static const void *flush_va;
173 static unsigned int flush_flags;
175 fastcall void smp_invalidate_interrupt(void)
176 {
177 ack_APIC_irq();
178 perfc_incr(ipis);
179 irq_enter();
180 if ( !__sync_lazy_execstate() ||
181 (flush_flags & (FLUSH_TLB_GLOBAL | FLUSH_CACHE)) )
182 flush_area_local(flush_va, flush_flags);
183 cpu_clear(smp_processor_id(), flush_cpumask);
184 irq_exit();
185 }
187 void flush_area_mask(cpumask_t mask, const void *va, unsigned int flags)
188 {
189 ASSERT(local_irq_is_enabled());
191 if ( cpu_isset(smp_processor_id(), mask) )
192 {
193 flush_area_local(va, flags);
194 cpu_clear(smp_processor_id(), mask);
195 }
197 if ( !cpus_empty(mask) )
198 {
199 spin_lock(&flush_lock);
200 flush_cpumask = mask;
201 flush_va = va;
202 flush_flags = flags;
203 send_IPI_mask(mask, INVALIDATE_TLB_VECTOR);
204 while ( !cpus_empty(flush_cpumask) )
205 cpu_relax();
206 spin_unlock(&flush_lock);
207 }
208 }
210 /* Call with no locks held and interrupts enabled (e.g., softirq context). */
211 void new_tlbflush_clock_period(void)
212 {
213 cpumask_t allbutself;
215 /* Flush everyone else. We definitely flushed just before entry. */
216 allbutself = cpu_online_map;
217 cpu_clear(smp_processor_id(), allbutself);
218 flush_mask(allbutself, FLUSH_TLB);
220 /* No need for atomicity: we are the only possible updater. */
221 ASSERT(tlbflush_clock == 0);
222 tlbflush_clock++;
223 }
225 void smp_send_event_check_mask(cpumask_t mask)
226 {
227 cpu_clear(smp_processor_id(), mask);
228 if ( !cpus_empty(mask) )
229 send_IPI_mask(mask, EVENT_CHECK_VECTOR);
230 }
232 /*
233 * Structure and data for smp_call_function()/on_selected_cpus().
234 */
236 struct call_data_struct {
237 void (*func) (void *info);
238 void *info;
239 int wait;
240 atomic_t started;
241 atomic_t finished;
242 cpumask_t selected;
243 };
245 static DEFINE_SPINLOCK(call_lock);
246 static struct call_data_struct *call_data;
248 int smp_call_function(
249 void (*func) (void *info),
250 void *info,
251 int retry,
252 int wait)
253 {
254 cpumask_t allbutself = cpu_online_map;
255 cpu_clear(smp_processor_id(), allbutself);
256 return on_selected_cpus(allbutself, func, info, retry, wait);
257 }
259 int on_selected_cpus(
260 cpumask_t selected,
261 void (*func) (void *info),
262 void *info,
263 int retry,
264 int wait)
265 {
266 struct call_data_struct data;
267 unsigned int nr_cpus = cpus_weight(selected);
269 ASSERT(local_irq_is_enabled());
271 /* Legacy UP system with no APIC to deliver IPIs? */
272 if ( unlikely(!cpu_has_apic) )
273 {
274 ASSERT(num_online_cpus() == 1);
275 if ( cpu_isset(0, selected) )
276 {
277 local_irq_disable();
278 func(info);
279 local_irq_enable();
280 }
281 return 0;
282 }
284 if ( nr_cpus == 0 )
285 return 0;
287 data.func = func;
288 data.info = info;
289 data.wait = wait;
290 atomic_set(&data.started, 0);
291 atomic_set(&data.finished, 0);
292 data.selected = selected;
294 spin_lock(&call_lock);
296 call_data = &data;
297 wmb();
299 send_IPI_mask(selected, CALL_FUNCTION_VECTOR);
301 while ( atomic_read(wait ? &data.finished : &data.started) != nr_cpus )
302 cpu_relax();
304 spin_unlock(&call_lock);
306 return 0;
307 }
309 static void __stop_this_cpu(void)
310 {
311 ASSERT(!local_irq_is_enabled());
313 disable_local_APIC();
315 hvm_cpu_down();
317 /*
318 * Clear FPU, zapping any pending exceptions. Needed for warm reset with
319 * some BIOSes.
320 */
321 clts();
322 asm volatile ( "fninit" );
323 }
325 static void stop_this_cpu(void *dummy)
326 {
327 __stop_this_cpu();
328 cpu_clear(smp_processor_id(), cpu_online_map);
329 for ( ; ; )
330 halt();
331 }
333 /*
334 * Stop all CPUs and turn off local APICs and the IO-APIC, so other OSs see a
335 * clean IRQ state.
336 */
337 void smp_send_stop(void)
338 {
339 int timeout = 10;
341 smp_call_function(stop_this_cpu, NULL, 1, 0);
343 /* Wait 10ms for all other CPUs to go offline. */
344 while ( (num_online_cpus() > 1) && (timeout-- > 0) )
345 mdelay(1);
347 local_irq_disable();
348 __stop_this_cpu();
349 disable_IO_APIC();
350 local_irq_enable();
351 }
353 fastcall void smp_event_check_interrupt(struct cpu_user_regs *regs)
354 {
355 ack_APIC_irq();
356 perfc_incr(ipis);
357 }
359 fastcall void smp_call_function_interrupt(struct cpu_user_regs *regs)
360 {
361 void (*func)(void *info) = call_data->func;
362 void *info = call_data->info;
364 ack_APIC_irq();
365 perfc_incr(ipis);
367 if ( !cpu_isset(smp_processor_id(), call_data->selected) )
368 return;
370 irq_enter();
372 if ( call_data->wait )
373 {
374 (*func)(info);
375 mb();
376 atomic_inc(&call_data->finished);
377 }
378 else
379 {
380 mb();
381 atomic_inc(&call_data->started);
382 (*func)(info);
383 }
385 irq_exit();
386 }