ia64/xen-unstable

view tools/firmware/hvmloader/pci_regs.h @ 19709:011948e1b5a7

hvmloader: Scan for gpxe-capable NICs until one is found.

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jun 03 16:12:34 2009 +0100 (2009-06-03)
parents a8d31d5ce258
children
line source
1 /*
2 * pci_regs.h
3 *
4 * PCI standard defines
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
17 #ifndef __HVMLOADER_PCI_REGS_H__
18 #define __HVMLOADER_PCI_REGS_H__
20 #define PCI_VENDOR_ID 0x00 /* 16 bits */
21 #define PCI_DEVICE_ID 0x02 /* 16 bits */
22 #define PCI_COMMAND 0x04 /* 16 bits */
23 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
24 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
25 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
26 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
27 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
28 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
29 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
30 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
31 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
32 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
33 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
35 #define PCI_STATUS 0x06 /* 16 bits */
36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42 #define PCI_STATUS_DEVSEL_FAST 0x000
43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
44 #define PCI_STATUS_DEVSEL_SLOW 0x400
45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
52 #define PCI_REVISION_ID 0x08 /* Revision ID */
53 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
54 #define PCI_CLASS_DEVICE 0x0a /* Device class */
56 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
57 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
58 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
59 #define PCI_HEADER_TYPE_NORMAL 0
60 #define PCI_HEADER_TYPE_BRIDGE 1
61 #define PCI_HEADER_TYPE_CARDBUS 2
63 #define PCI_BIST 0x0f /* 8 bits */
64 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
65 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
66 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
68 /*
69 * Base addresses specify locations in memory or I/O space.
70 * Decoded size can be determined by writing a value of
71 * 0xffffffff to the register, and reading it back. Only
72 * 1 bits are decoded.
73 */
74 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
75 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
76 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
77 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
78 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
79 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
80 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
81 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
82 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
83 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
84 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
85 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
86 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
87 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
88 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
89 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
90 /* bit 1 is reserved if address_space = 1 */
92 /* Header type 0 (normal devices) */
93 #define PCI_CARDBUS_CIS 0x28
94 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
95 #define PCI_SUBSYSTEM_ID 0x2e
96 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
97 #define PCI_ROM_ADDRESS_ENABLE 0x01
98 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
100 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
102 /* 0x35-0x3b are reserved */
103 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
104 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
105 #define PCI_MIN_GNT 0x3e /* 8 bits */
106 #define PCI_MAX_LAT 0x3f /* 8 bits */
108 #endif /* __HVMLOADER_PCI_REGS_H__ */