ia64/xen-unstable

diff linux-2.6-xen-sparse/arch/ia64/kernel/iosapic.c @ 9747:de2dc4e7966a

[IA64] Add support to physdev_ops

Add support to physdev ops, and thus give IOSAPIC RTEs
managed by Xen now. Dom0 now issues hypercall to r/w
RTE entry. Another change is the irq vector allocation
which is also owned by xen now.

After this change, the IOSAPIC is almost owned by xen
with only exception as IOSAPIC EOI which is still issued
by dom0 directly. But that's OK since currently dom0
owns all external physical devices. Later full event
channel mechanism will provide necessary support for
driver domain, and at that time, dom0 instead issues
physdev_op (PHYSDEVOP_IRQ_UNMASK_NOTIFY) naturally as
replace of IOSAPIC EOI.

Signed-off-by Kevin Tian <kevin.tian@intel.com>
author awilliam@xenbuild.aw
date Fri Apr 21 09:03:19 2006 -0600 (2006-04-21)
parents 19148831ab05
children 42a8e3101c6c
line diff
     1.1 --- a/linux-2.6-xen-sparse/arch/ia64/kernel/iosapic.c	Fri Apr 21 08:56:34 2006 -0600
     1.2 +++ b/linux-2.6-xen-sparse/arch/ia64/kernel/iosapic.c	Fri Apr 21 09:03:19 2006 -0600
     1.3 @@ -140,6 +140,68 @@ static unsigned char pcat_compat __devin
     1.4  static int iosapic_kmalloc_ok;
     1.5  static LIST_HEAD(free_rte_list);
     1.6  
     1.7 +#ifdef CONFIG_XEN
     1.8 +#include <xen/interface/xen.h>
     1.9 +#include <xen/interface/physdev.h>
    1.10 +#include <asm/hypervisor.h>
    1.11 +static inline unsigned int xen_iosapic_read(char __iomem *iosapic, unsigned int reg)
    1.12 +{
    1.13 +	physdev_op_t op;
    1.14 +	int ret;
    1.15 +
    1.16 +	op.cmd = PHYSDEVOP_APIC_READ;
    1.17 +	op.u.apic_op.apic_physbase = (unsigned long)iosapic -
    1.18 +					__IA64_UNCACHED_OFFSET;
    1.19 +	op.u.apic_op.reg = reg;
    1.20 +	ret = HYPERVISOR_physdev_op(&op);
    1.21 +	if (ret)
    1.22 +		return ret;
    1.23 +	return op.u.apic_op.value;
    1.24 +}
    1.25 +
    1.26 +static inline void xen_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
    1.27 +{
    1.28 +	physdev_op_t op;
    1.29 +
    1.30 +	op.cmd = PHYSDEVOP_APIC_WRITE;
    1.31 +	op.u.apic_op.apic_physbase = (unsigned long)iosapic - 
    1.32 +					__IA64_UNCACHED_OFFSET;
    1.33 +	op.u.apic_op.reg = reg;
    1.34 +	op.u.apic_op.value = val;
    1.35 +	HYPERVISOR_physdev_op(&op);
    1.36 +}
    1.37 +
    1.38 +static inline unsigned int iosapic_read(char __iomem *iosapic, unsigned int reg)
    1.39 +{
    1.40 +	if (!running_on_xen) {
    1.41 +		writel(reg, iosapic + IOSAPIC_REG_SELECT);
    1.42 +		return readl(iosapic + IOSAPIC_WINDOW);
    1.43 +	} else
    1.44 +		return xen_iosapic_read(iosapic, reg);
    1.45 +}
    1.46 +
    1.47 +static inline void iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
    1.48 +{
    1.49 +	if (!running_on_xen) {
    1.50 +		writel(reg, iosapic + IOSAPIC_REG_SELECT);
    1.51 +		writel(val, iosapic + IOSAPIC_WINDOW);
    1.52 +	} else
    1.53 +		xen_iosapic_write(iosapic, reg, val);
    1.54 +}
    1.55 +
    1.56 +int xen_assign_irq_vector(int irq)
    1.57 +{
    1.58 +	physdev_op_t op;
    1.59 +
    1.60 +	op.cmd = PHYSDEVOP_ASSIGN_VECTOR;
    1.61 +	op.u.irq_op.irq = irq;
    1.62 +	if (HYPERVISOR_physdev_op(&op))
    1.63 +		return -ENOSPC;
    1.64 +
    1.65 +	return op.u.irq_op.vector;
    1.66 +}
    1.67 +#endif /* XEN */
    1.68 +
    1.69  /*
    1.70   * Find an IOSAPIC associated with a GSI
    1.71   */
    1.72 @@ -953,6 +1015,10 @@ iosapic_system_init (int system_pcat_com
    1.73  	}
    1.74  
    1.75  	pcat_compat = system_pcat_compat;
    1.76 +#ifdef CONFIG_XEN
    1.77 +	if (running_on_xen)
    1.78 +		return;
    1.79 +#endif
    1.80  	if (pcat_compat) {
    1.81  		/*
    1.82  		 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support