ia64/xen-unstable

diff old/xenolinux-2.4.16-sparse/include/asm-xeno/debugreg.h @ 235:d7d0a23b2e07

bitkeeper revision 1.93 (3e5a4e6bkPheUp3x1uufN2MS3LAB7A)

Latest and Greatest version of XenoLinux based on the Linux-2.4.21-pre4
kernel.
author iap10@labyrinth.cl.cam.ac.uk
date Mon Feb 24 16:55:07 2003 +0000 (2003-02-24)
parents
children
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/old/xenolinux-2.4.16-sparse/include/asm-xeno/debugreg.h	Mon Feb 24 16:55:07 2003 +0000
     1.3 @@ -0,0 +1,64 @@
     1.4 +#ifndef _I386_DEBUGREG_H
     1.5 +#define _I386_DEBUGREG_H
     1.6 +
     1.7 +
     1.8 +/* Indicate the register numbers for a number of the specific
     1.9 +   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
    1.10 +#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
    1.11 +#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
    1.12 +
    1.13 +#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
    1.14 +#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
    1.15 +
    1.16 +/* Define a few things for the status register.  We can use this to determine
    1.17 +   which debugging register was responsible for the trap.  The other bits
    1.18 +   are either reserved or not of interest to us. */
    1.19 +
    1.20 +#define DR_TRAP0	(0x1)		/* db0 */
    1.21 +#define DR_TRAP1	(0x2)		/* db1 */
    1.22 +#define DR_TRAP2	(0x4)		/* db2 */
    1.23 +#define DR_TRAP3	(0x8)		/* db3 */
    1.24 +
    1.25 +#define DR_STEP		(0x4000)	/* single-step */
    1.26 +#define DR_SWITCH	(0x8000)	/* task switch */
    1.27 +
    1.28 +/* Now define a bunch of things for manipulating the control register.
    1.29 +   The top two bytes of the control register consist of 4 fields of 4
    1.30 +   bits - each field corresponds to one of the four debug registers,
    1.31 +   and indicates what types of access we trap on, and how large the data
    1.32 +   field is that we are looking at */
    1.33 +
    1.34 +#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
    1.35 +#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
    1.36 +
    1.37 +#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
    1.38 +#define DR_RW_WRITE (0x1)
    1.39 +#define DR_RW_READ (0x3)
    1.40 +
    1.41 +#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
    1.42 +#define DR_LEN_2 (0x4)
    1.43 +#define DR_LEN_4 (0xC)
    1.44 +
    1.45 +/* The low byte to the control register determine which registers are
    1.46 +   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
    1.47 +   that the processor will reset the bit after a task switch and the other
    1.48 +   is global meaning that we have to explicitly reset the bit.  With linux,
    1.49 +   you can use either one, since we explicitly zero the register when we enter
    1.50 +   kernel mode. */
    1.51 +
    1.52 +#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
    1.53 +#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
    1.54 +#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
    1.55 +
    1.56 +#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
    1.57 +#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
    1.58 +
    1.59 +/* The second byte to the control register has a few special things.
    1.60 +   We can slow the instruction pipeline for instructions coming via the
    1.61 +   gdt or the ldt if we want to.  I am not sure why this is an advantage */
    1.62 +
    1.63 +#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
    1.64 +#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
    1.65 +#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
    1.66 +
    1.67 +#endif