ia64/xen-unstable

diff xen/include/public/arch-x86/hvm/save.h @ 16153:a87d94be1172

Split xen/include/public/hvm/save.h into common part and x86 specific part.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Keir Fraser <keir@xensource.com>
date Thu Oct 18 10:58:36 2007 +0100 (2007-10-18)
parents
children 5a451d2c36bc
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/xen/include/public/arch-x86/hvm/save.h	Thu Oct 18 10:58:36 2007 +0100
     1.3 @@ -0,0 +1,413 @@
     1.4 +/* 
     1.5 + * Structure definitions for HVM state that is held by Xen and must
     1.6 + * be saved along with the domain's memory and device-model state.
     1.7 + * 
     1.8 + * Copyright (c) 2007 XenSource Ltd.
     1.9 + *
    1.10 + * Permission is hereby granted, free of charge, to any person obtaining a copy
    1.11 + * of this software and associated documentation files (the "Software"), to
    1.12 + * deal in the Software without restriction, including without limitation the
    1.13 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
    1.14 + * sell copies of the Software, and to permit persons to whom the Software is
    1.15 + * furnished to do so, subject to the following conditions:
    1.16 + *
    1.17 + * The above copyright notice and this permission notice shall be included in
    1.18 + * all copies or substantial portions of the Software.
    1.19 + *
    1.20 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1.21 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    1.22 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    1.23 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    1.24 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
    1.25 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
    1.26 + * DEALINGS IN THE SOFTWARE.
    1.27 + */
    1.28 +
    1.29 +#ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__
    1.30 +#define __XEN_PUBLIC_HVM_SAVE_X86_H__
    1.31 +
    1.32 +/* 
    1.33 + * Save/restore header: general info about the save file. 
    1.34 + */
    1.35 +
    1.36 +#define HVM_FILE_MAGIC   0x54381286
    1.37 +#define HVM_FILE_VERSION 0x00000001
    1.38 +
    1.39 +struct hvm_save_header {
    1.40 +    uint32_t magic;             /* Must be HVM_FILE_MAGIC */
    1.41 +    uint32_t version;           /* File format version */
    1.42 +    uint64_t changeset;         /* Version of Xen that saved this file */
    1.43 +    uint32_t cpuid;             /* CPUID[0x01][%eax] on the saving machine */
    1.44 +    uint32_t pad0;
    1.45 +};
    1.46 +
    1.47 +DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
    1.48 +
    1.49 +
    1.50 +/*
    1.51 + * Processor
    1.52 + */
    1.53 +
    1.54 +struct hvm_hw_cpu {
    1.55 +    uint8_t  fpu_regs[512];
    1.56 +
    1.57 +    uint64_t rax;
    1.58 +    uint64_t rbx;
    1.59 +    uint64_t rcx;
    1.60 +    uint64_t rdx;
    1.61 +    uint64_t rbp;
    1.62 +    uint64_t rsi;
    1.63 +    uint64_t rdi;
    1.64 +    uint64_t rsp;
    1.65 +    uint64_t r8;
    1.66 +    uint64_t r9;
    1.67 +    uint64_t r10;
    1.68 +    uint64_t r11;
    1.69 +    uint64_t r12;
    1.70 +    uint64_t r13;
    1.71 +    uint64_t r14;
    1.72 +    uint64_t r15;
    1.73 +
    1.74 +    uint64_t rip;
    1.75 +    uint64_t rflags;
    1.76 +
    1.77 +    uint64_t cr0;
    1.78 +    uint64_t cr2;
    1.79 +    uint64_t cr3;
    1.80 +    uint64_t cr4;
    1.81 +
    1.82 +    uint64_t dr0;
    1.83 +    uint64_t dr1;
    1.84 +    uint64_t dr2;
    1.85 +    uint64_t dr3;
    1.86 +    uint64_t dr6;
    1.87 +    uint64_t dr7;    
    1.88 +
    1.89 +    uint32_t cs_sel;
    1.90 +    uint32_t ds_sel;
    1.91 +    uint32_t es_sel;
    1.92 +    uint32_t fs_sel;
    1.93 +    uint32_t gs_sel;
    1.94 +    uint32_t ss_sel;
    1.95 +    uint32_t tr_sel;
    1.96 +    uint32_t ldtr_sel;
    1.97 +
    1.98 +    uint32_t cs_limit;
    1.99 +    uint32_t ds_limit;
   1.100 +    uint32_t es_limit;
   1.101 +    uint32_t fs_limit;
   1.102 +    uint32_t gs_limit;
   1.103 +    uint32_t ss_limit;
   1.104 +    uint32_t tr_limit;
   1.105 +    uint32_t ldtr_limit;
   1.106 +    uint32_t idtr_limit;
   1.107 +    uint32_t gdtr_limit;
   1.108 +
   1.109 +    uint64_t cs_base;
   1.110 +    uint64_t ds_base;
   1.111 +    uint64_t es_base;
   1.112 +    uint64_t fs_base;
   1.113 +    uint64_t gs_base;
   1.114 +    uint64_t ss_base;
   1.115 +    uint64_t tr_base;
   1.116 +    uint64_t ldtr_base;
   1.117 +    uint64_t idtr_base;
   1.118 +    uint64_t gdtr_base;
   1.119 +
   1.120 +    uint32_t cs_arbytes;
   1.121 +    uint32_t ds_arbytes;
   1.122 +    uint32_t es_arbytes;
   1.123 +    uint32_t fs_arbytes;
   1.124 +    uint32_t gs_arbytes;
   1.125 +    uint32_t ss_arbytes;
   1.126 +    uint32_t tr_arbytes;
   1.127 +    uint32_t ldtr_arbytes;
   1.128 +
   1.129 +    uint32_t sysenter_cs;
   1.130 +    uint32_t padding0;
   1.131 +
   1.132 +    uint64_t sysenter_esp;
   1.133 +    uint64_t sysenter_eip;
   1.134 +
   1.135 +    /* msr for em64t */
   1.136 +    uint64_t shadow_gs;
   1.137 +
   1.138 +    /* msr content saved/restored. */
   1.139 +    uint64_t msr_flags;
   1.140 +    uint64_t msr_lstar;
   1.141 +    uint64_t msr_star;
   1.142 +    uint64_t msr_cstar;
   1.143 +    uint64_t msr_syscall_mask;
   1.144 +    uint64_t msr_efer;
   1.145 +
   1.146 +    /* guest's idea of what rdtsc() would return */
   1.147 +    uint64_t tsc;
   1.148 +
   1.149 +    /* pending event, if any */
   1.150 +    union {
   1.151 +        uint32_t pending_event;
   1.152 +        struct {
   1.153 +            uint8_t  pending_vector:8;
   1.154 +            uint8_t  pending_type:3;
   1.155 +            uint8_t  pending_error_valid:1;
   1.156 +            uint32_t pending_reserved:19;
   1.157 +            uint8_t  pending_valid:1;
   1.158 +        };
   1.159 +    };
   1.160 +    /* error code for pending event */
   1.161 +    uint32_t error_code;
   1.162 +};
   1.163 +
   1.164 +DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_cpu);
   1.165 +
   1.166 +
   1.167 +/*
   1.168 + * PIC
   1.169 + */
   1.170 +
   1.171 +struct hvm_hw_vpic {
   1.172 +    /* IR line bitmasks. */
   1.173 +    uint8_t irr;
   1.174 +    uint8_t imr;
   1.175 +    uint8_t isr;
   1.176 +
   1.177 +    /* Line IRx maps to IRQ irq_base+x */
   1.178 +    uint8_t irq_base;
   1.179 +
   1.180 +    /*
   1.181 +     * Where are we in ICW2-4 initialisation (0 means no init in progress)?
   1.182 +     * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
   1.183 +     * Bit 2: ICW1.IC4  (1 == ICW4 included in init sequence)
   1.184 +     * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
   1.185 +     */
   1.186 +    uint8_t init_state:4;
   1.187 +
   1.188 +    /* IR line with highest priority. */
   1.189 +    uint8_t priority_add:4;
   1.190 +
   1.191 +    /* Reads from A=0 obtain ISR or IRR? */
   1.192 +    uint8_t readsel_isr:1;
   1.193 +
   1.194 +    /* Reads perform a polling read? */
   1.195 +    uint8_t poll:1;
   1.196 +
   1.197 +    /* Automatically clear IRQs from the ISR during INTA? */
   1.198 +    uint8_t auto_eoi:1;
   1.199 +
   1.200 +    /* Automatically rotate IRQ priorities during AEOI? */
   1.201 +    uint8_t rotate_on_auto_eoi:1;
   1.202 +
   1.203 +    /* Exclude slave inputs when considering in-service IRQs? */
   1.204 +    uint8_t special_fully_nested_mode:1;
   1.205 +
   1.206 +    /* Special mask mode excludes masked IRs from AEOI and priority checks. */
   1.207 +    uint8_t special_mask_mode:1;
   1.208 +
   1.209 +    /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
   1.210 +    uint8_t is_master:1;
   1.211 +
   1.212 +    /* Edge/trigger selection. */
   1.213 +    uint8_t elcr;
   1.214 +
   1.215 +    /* Virtual INT output. */
   1.216 +    uint8_t int_output;
   1.217 +};
   1.218 +
   1.219 +DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
   1.220 +
   1.221 +
   1.222 +/*
   1.223 + * IO-APIC
   1.224 + */
   1.225 +
   1.226 +#ifdef __ia64__
   1.227 +#define VIOAPIC_IS_IOSAPIC 1
   1.228 +#define VIOAPIC_NUM_PINS  24
   1.229 +#else
   1.230 +#define VIOAPIC_NUM_PINS  48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
   1.231 +#endif
   1.232 +
   1.233 +struct hvm_hw_vioapic {
   1.234 +    uint64_t base_address;
   1.235 +    uint32_t ioregsel;
   1.236 +    uint32_t id;
   1.237 +    union vioapic_redir_entry
   1.238 +    {
   1.239 +        uint64_t bits;
   1.240 +        struct {
   1.241 +            uint8_t vector;
   1.242 +            uint8_t delivery_mode:3;
   1.243 +            uint8_t dest_mode:1;
   1.244 +            uint8_t delivery_status:1;
   1.245 +            uint8_t polarity:1;
   1.246 +            uint8_t remote_irr:1;
   1.247 +            uint8_t trig_mode:1;
   1.248 +            uint8_t mask:1;
   1.249 +            uint8_t reserve:7;
   1.250 +#if !VIOAPIC_IS_IOSAPIC
   1.251 +            uint8_t reserved[4];
   1.252 +            uint8_t dest_id;
   1.253 +#else
   1.254 +            uint8_t reserved[3];
   1.255 +            uint16_t dest_id;
   1.256 +#endif
   1.257 +        } fields;
   1.258 +    } redirtbl[VIOAPIC_NUM_PINS];
   1.259 +};
   1.260 +
   1.261 +DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
   1.262 +
   1.263 +
   1.264 +/*
   1.265 + * LAPIC
   1.266 + */
   1.267 +
   1.268 +struct hvm_hw_lapic {
   1.269 +    uint64_t             apic_base_msr;
   1.270 +    uint32_t             disabled; /* VLAPIC_xx_DISABLED */
   1.271 +    uint32_t             timer_divisor;
   1.272 +};
   1.273 +
   1.274 +DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
   1.275 +
   1.276 +struct hvm_hw_lapic_regs {
   1.277 +    /* A 4k page of register state */
   1.278 +    uint8_t  data[0x400];
   1.279 +};
   1.280 +
   1.281 +DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
   1.282 +
   1.283 +
   1.284 +/*
   1.285 + * IRQs
   1.286 + */
   1.287 +
   1.288 +struct hvm_hw_pci_irqs {
   1.289 +    /*
   1.290 +     * Virtual interrupt wires for a single PCI bus.
   1.291 +     * Indexed by: device*4 + INTx#.
   1.292 +     */
   1.293 +    union {
   1.294 +        DECLARE_BITMAP(i, 32*4);
   1.295 +        uint64_t pad[2];
   1.296 +    };
   1.297 +};
   1.298 +
   1.299 +DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
   1.300 +
   1.301 +struct hvm_hw_isa_irqs {
   1.302 +    /*
   1.303 +     * Virtual interrupt wires for ISA devices.
   1.304 +     * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
   1.305 +     */
   1.306 +    union {
   1.307 +        DECLARE_BITMAP(i, 16);
   1.308 +        uint64_t pad[1];
   1.309 +    };
   1.310 +};
   1.311 +
   1.312 +DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
   1.313 +
   1.314 +struct hvm_hw_pci_link {
   1.315 +    /*
   1.316 +     * PCI-ISA interrupt router.
   1.317 +     * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
   1.318 +     * the traditional 'barber's pole' mapping ((device + INTx#) & 3).
   1.319 +     * The router provides a programmable mapping from each link to a GSI.
   1.320 +     */
   1.321 +    uint8_t route[4];
   1.322 +    uint8_t pad0[4];
   1.323 +};
   1.324 +
   1.325 +DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
   1.326 +
   1.327 +/* 
   1.328 + *  PIT
   1.329 + */
   1.330 +
   1.331 +struct hvm_hw_pit {
   1.332 +    struct hvm_hw_pit_channel {
   1.333 +        uint32_t count; /* can be 65536 */
   1.334 +        uint16_t latched_count;
   1.335 +        uint8_t count_latched;
   1.336 +        uint8_t status_latched;
   1.337 +        uint8_t status;
   1.338 +        uint8_t read_state;
   1.339 +        uint8_t write_state;
   1.340 +        uint8_t write_latch;
   1.341 +        uint8_t rw_mode;
   1.342 +        uint8_t mode;
   1.343 +        uint8_t bcd; /* not supported */
   1.344 +        uint8_t gate; /* timer start */
   1.345 +    } channels[3];  /* 3 x 16 bytes */
   1.346 +    uint32_t speaker_data_on;
   1.347 +    uint32_t pad0;
   1.348 +};
   1.349 +
   1.350 +DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
   1.351 +
   1.352 +
   1.353 +/* 
   1.354 + * RTC
   1.355 + */ 
   1.356 +
   1.357 +#define RTC_CMOS_SIZE 14
   1.358 +struct hvm_hw_rtc {
   1.359 +    /* CMOS bytes */
   1.360 +    uint8_t cmos_data[RTC_CMOS_SIZE];
   1.361 +    /* Index register for 2-part operations */
   1.362 +    uint8_t cmos_index;
   1.363 +    uint8_t pad0;
   1.364 +};
   1.365 +
   1.366 +DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
   1.367 +
   1.368 +
   1.369 +/*
   1.370 + * HPET
   1.371 + */
   1.372 +
   1.373 +#define HPET_TIMER_NUM     3    /* 3 timers supported now */
   1.374 +struct hvm_hw_hpet {
   1.375 +    /* Memory-mapped, software visible registers */
   1.376 +    uint64_t capability;        /* capabilities */
   1.377 +    uint64_t res0;              /* reserved */
   1.378 +    uint64_t config;            /* configuration */
   1.379 +    uint64_t res1;              /* reserved */
   1.380 +    uint64_t isr;               /* interrupt status reg */
   1.381 +    uint64_t res2[25];          /* reserved */
   1.382 +    uint64_t mc64;              /* main counter */
   1.383 +    uint64_t res3;              /* reserved */
   1.384 +    struct {                    /* timers */
   1.385 +        uint64_t config;        /* configuration/cap */
   1.386 +        uint64_t cmp;           /* comparator */
   1.387 +        uint64_t fsb;           /* FSB route, not supported now */
   1.388 +        uint64_t res4;          /* reserved */
   1.389 +    } timers[HPET_TIMER_NUM];
   1.390 +    uint64_t res5[4*(24-HPET_TIMER_NUM)];  /* reserved, up to 0x3ff */
   1.391 +
   1.392 +    /* Hidden register state */
   1.393 +    uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
   1.394 +};
   1.395 +
   1.396 +DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
   1.397 +
   1.398 +
   1.399 +/*
   1.400 + * PM timer
   1.401 + */
   1.402 +
   1.403 +struct hvm_hw_pmtimer {
   1.404 +    uint32_t tmr_val;   /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
   1.405 +    uint16_t pm1a_sts;  /* PM1a_EVT_BLK.PM1a_STS: status register */
   1.406 +    uint16_t pm1a_en;   /* PM1a_EVT_BLK.PM1a_EN: enable register */
   1.407 +};
   1.408 +
   1.409 +DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
   1.410 +
   1.411 +/* 
   1.412 + * Largest type-code in use
   1.413 + */
   1.414 +#define HVM_SAVE_CODE_MAX 13
   1.415 +
   1.416 +#endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */