ia64/xen-unstable

diff xen/arch/ia64/xen/vcpu.c @ 10692:306d7857928c

[IA64] Save & restore.

xc_ia64_linux_save.c and xc_ia64_linux_restore.c added.
vcpu context has more registers and states (eg: tr registers).
Per cpu irqs are deallocated when cpu is switched off.
#if/#endif added in reboot.c for ia64.

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Jul 11 12:51:18 2006 -0600 (2006-07-11)
parents bdc0258e162a
children 000789c36d28
line diff
     1.1 --- a/xen/arch/ia64/xen/vcpu.c	Tue Jul 11 11:29:25 2006 -0600
     1.2 +++ b/xen/arch/ia64/xen/vcpu.c	Tue Jul 11 12:51:18 2006 -0600
     1.3 @@ -1880,13 +1880,15 @@ IA64FAULT vcpu_set_pkr(VCPU *vcpu, UINT6
     1.4   VCPU translation register access routines
     1.5  **************************************************************************/
     1.6  
     1.7 -static void vcpu_set_tr_entry(TR_ENTRY *trp, UINT64 pte, UINT64 itir, UINT64 ifa)
     1.8 +static void
     1.9 +vcpu_set_tr_entry_rid(TR_ENTRY *trp, UINT64 pte,
    1.10 +                      UINT64 itir, UINT64 ifa, UINT64 rid)
    1.11  {
    1.12  	UINT64 ps;
    1.13  	union pte_flags new_pte;
    1.14  
    1.15  	trp->itir = itir;
    1.16 -	trp->rid = VCPU(current,rrs[ifa>>61]) & RR_RID_MASK;
    1.17 +	trp->rid = rid;
    1.18  	ps = trp->ps;
    1.19  	new_pte.val = pte;
    1.20  	if (new_pte.pl < 2) new_pte.pl = 2;
    1.21 @@ -1900,8 +1902,15 @@ static void vcpu_set_tr_entry(TR_ENTRY *
    1.22  	trp->pte.val = new_pte.val;
    1.23  }
    1.24  
    1.25 +static inline void
    1.26 +vcpu_set_tr_entry(TR_ENTRY *trp, UINT64 pte, UINT64 itir, UINT64 ifa)
    1.27 +{
    1.28 +	vcpu_set_tr_entry_rid(trp, pte, itir, ifa,
    1.29 +			      VCPU(current, rrs[ifa>>61]) & RR_RID_MASK);
    1.30 +}
    1.31 +
    1.32  IA64FAULT vcpu_itr_d(VCPU *vcpu, UINT64 slot, UINT64 pte,
    1.33 -		UINT64 itir, UINT64 ifa)
    1.34 +                     UINT64 itir, UINT64 ifa)
    1.35  {
    1.36  	TR_ENTRY *trp;
    1.37  
    1.38 @@ -1920,7 +1929,7 @@ IA64FAULT vcpu_itr_d(VCPU *vcpu, UINT64 
    1.39  }
    1.40  
    1.41  IA64FAULT vcpu_itr_i(VCPU *vcpu, UINT64 slot, UINT64 pte,
    1.42 -		UINT64 itir, UINT64 ifa)
    1.43 +                     UINT64 itir, UINT64 ifa)
    1.44  {
    1.45  	TR_ENTRY *trp;
    1.46  
    1.47 @@ -1938,6 +1947,44 @@ IA64FAULT vcpu_itr_i(VCPU *vcpu, UINT64 
    1.48  	return IA64_NO_FAULT;
    1.49  }
    1.50  
    1.51 +IA64FAULT vcpu_set_itr(VCPU *vcpu, u64 slot, u64 pte,
    1.52 +                       u64 itir, u64 ifa, u64 rid)
    1.53 +{
    1.54 +	TR_ENTRY *trp;
    1.55 +
    1.56 +	if (slot >= NITRS)
    1.57 + 		return IA64_RSVDREG_FAULT;
    1.58 +	trp = &PSCBX(vcpu, itrs[slot]);
    1.59 +	vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
    1.60 +
    1.61 +	/* Recompute the itr_region.  */
    1.62 +	vcpu->arch.itr_regions = 0;
    1.63 +	for (trp = vcpu->arch.itrs; trp < &vcpu->arch.itrs[NITRS]; trp++)
    1.64 +		if (trp->pte.p)
    1.65 +			vcpu_quick_region_set(vcpu->arch.itr_regions,
    1.66 +			                      trp->vadr);
    1.67 +	return IA64_NO_FAULT;
    1.68 +}
    1.69 +
    1.70 +IA64FAULT vcpu_set_dtr(VCPU *vcpu, u64 slot, u64 pte,
    1.71 +                       u64 itir, u64 ifa, u64 rid)
    1.72 +{
    1.73 +	TR_ENTRY *trp;
    1.74 +
    1.75 +	if (slot >= NDTRS)
    1.76 +		return IA64_RSVDREG_FAULT;
    1.77 +	trp = &PSCBX(vcpu, dtrs[slot]);
    1.78 +	vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
    1.79 +
    1.80 +	/* Recompute the dtr_region.  */
    1.81 +	vcpu->arch.dtr_regions = 0;
    1.82 +	for (trp = vcpu->arch.dtrs; trp < &vcpu->arch.dtrs[NDTRS]; trp++)
    1.83 +		if (trp->pte.p)
    1.84 +			vcpu_quick_region_set(vcpu->arch.dtr_regions,
    1.85 +			                      trp->vadr);
    1.86 +	return IA64_NO_FAULT;
    1.87 +}
    1.88 +
    1.89  /**************************************************************************
    1.90   VCPU translation cache access routines
    1.91  **************************************************************************/
    1.92 @@ -2159,7 +2206,6 @@ IA64FAULT vcpu_ptr_i(VCPU *vcpu,UINT64 v
    1.93  			vcpu_quick_region_set(vcpu->arch.itr_regions,
    1.94  					      trp->vadr);
    1.95  
    1.96 -
    1.97  	vcpu_flush_tlb_vhpt_range (vadr, log_range);
    1.98  
    1.99  	return IA64_NO_FAULT;