ia64/xen-unstable

diff xen/include/asm-ia64/xenprocessor.h @ 5046:0554a6615257

bitkeeper revision 1.1389.23.4 (428e13b9Hne7WMFOPqv3id1PNB6EYg)

- CONFIG_VTI=n by default.
- Reorganize code such that the changes to cp_patch files are minimized

Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author adsharma@linux-t08.sc.intel.com
date Fri May 20 16:43:37 2005 +0000 (2005-05-20)
parents
children 541012edd6e5
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/xen/include/asm-ia64/xenprocessor.h	Fri May 20 16:43:37 2005 +0000
     1.3 @@ -0,0 +1,213 @@
     1.4 +#ifndef _ASM_IA64_XENPROCESSOR_H
     1.5 +#define _ASM_IA64_XENPROCESSOR_H
     1.6 +/*
     1.7 + * xen specific processor definition
     1.8 + *
     1.9 + * Copyright (C) 2005 Hewlett-Packard Co.
    1.10 + *	Dan Magenheimer (dan.magenheimer@hp.com)
    1.11 + *
    1.12 + * Copyright (C) 2005 Intel Co.
    1.13 + * 	Kun Tian (Kevin Tian) <kevin.tian@intel.com>
    1.14 + *
    1.15 + */
    1.16 +
    1.17 +
    1.18 +#define ia64_is_local_fpu_owner(t) 0
    1.19 +
    1.20 +/* like above but expressed as bitfields for more efficient access: */
    1.21 +struct ia64_psr {
    1.22 +	__u64 reserved0 : 1;
    1.23 +	__u64 be : 1;
    1.24 +	__u64 up : 1;
    1.25 +	__u64 ac : 1;
    1.26 +	__u64 mfl : 1;
    1.27 +	__u64 mfh : 1;
    1.28 +	__u64 reserved1 : 7;
    1.29 +	__u64 ic : 1;
    1.30 +	__u64 i : 1;
    1.31 +	__u64 pk : 1;
    1.32 +	__u64 reserved2 : 1;
    1.33 +	__u64 dt : 1;
    1.34 +	__u64 dfl : 1;
    1.35 +	__u64 dfh : 1;
    1.36 +	__u64 sp : 1;
    1.37 +	__u64 pp : 1;
    1.38 +	__u64 di : 1;
    1.39 +	__u64 si : 1;
    1.40 +	__u64 db : 1;
    1.41 +	__u64 lp : 1;
    1.42 +	__u64 tb : 1;
    1.43 +	__u64 rt : 1;
    1.44 +	__u64 reserved3 : 4;
    1.45 +	__u64 cpl : 2;
    1.46 +	__u64 is : 1;
    1.47 +	__u64 mc : 1;
    1.48 +	__u64 it : 1;
    1.49 +	__u64 id : 1;
    1.50 +	__u64 da : 1;
    1.51 +	__u64 dd : 1;
    1.52 +	__u64 ss : 1;
    1.53 +	__u64 ri : 2;
    1.54 +	__u64 ed : 1;
    1.55 +	__u64 bn : 1;
    1.56 +#ifdef CONFIG_VTI
    1.57 +	__u64 ia : 1;
    1.58 +	__u64 vm : 1;
    1.59 +	__u64 reserved5 : 17;
    1.60 +#else // CONFIG_VTI
    1.61 +	__u64 reserved4 : 19;
    1.62 +#endif // CONFIG_VTI
    1.63 +};
    1.64 +
    1.65 +#ifdef  CONFIG_VTI
    1.66 +/* vmx like above but expressed as bitfields for more efficient access: */
    1.67 +typedef  union{
    1.68 +    __u64 val;
    1.69 +    struct{
    1.70 +    	__u64 reserved0 : 1;
    1.71 +	__u64 be : 1;
    1.72 +    	__u64 up : 1;
    1.73 +    	__u64 ac : 1;
    1.74 +    	__u64 mfl : 1;
    1.75 +    	__u64 mfh : 1;
    1.76 +    	__u64 reserved1 : 7;
    1.77 +    	__u64 ic : 1;
    1.78 +    	__u64 i : 1;
    1.79 +    	__u64 pk : 1;
    1.80 +    	__u64 reserved2 : 1;
    1.81 +    	__u64 dt : 1;
    1.82 +    	__u64 dfl : 1;
    1.83 +    	__u64 dfh : 1;
    1.84 +    	__u64 sp : 1;
    1.85 +    	__u64 pp : 1;
    1.86 +    	__u64 di : 1;
    1.87 +	__u64 si : 1;
    1.88 +    	__u64 db : 1;
    1.89 +    	__u64 lp : 1;
    1.90 +    	__u64 tb : 1;
    1.91 +    	__u64 rt : 1;
    1.92 +    	__u64 reserved3 : 4;
    1.93 +    	__u64 cpl : 2;
    1.94 +    	__u64 is : 1;
    1.95 +    	__u64 mc : 1;
    1.96 +    	__u64 it : 1;
    1.97 +    	__u64 id : 1;
    1.98 +    	__u64 da : 1;
    1.99 +    	__u64 dd : 1;
   1.100 +    	__u64 ss : 1;
   1.101 +    	__u64 ri : 2;
   1.102 +    	__u64 ed : 1;
   1.103 +    	__u64 bn : 1;
   1.104 +    	__u64 reserved4 : 19;
   1.105 +    };
   1.106 +}   IA64_PSR;
   1.107 +
   1.108 +typedef union {
   1.109 +    __u64 val;
   1.110 +    struct {
   1.111 +        __u64 code : 16;
   1.112 +        __u64 vector : 8;
   1.113 +        __u64 reserved1 : 8;
   1.114 +        __u64 x : 1;
   1.115 +        __u64 w : 1;
   1.116 +        __u64 r : 1;
   1.117 +        __u64 na : 1;
   1.118 +        __u64 sp : 1;
   1.119 +        __u64 rs : 1;
   1.120 +        __u64 ir : 1;
   1.121 +        __u64 ni : 1;
   1.122 +        __u64 so : 1;
   1.123 +        __u64 ei : 2;
   1.124 +        __u64 ed : 1;
   1.125 +        __u64 reserved2 : 20;
   1.126 +    };
   1.127 +}   ISR;
   1.128 +
   1.129 +
   1.130 +typedef union {
   1.131 +    __u64 val;
   1.132 +    struct {
   1.133 +        __u64 ve : 1;
   1.134 +        __u64 reserved0 : 1;
   1.135 +        __u64 size : 6;
   1.136 +        __u64 vf : 1;
   1.137 +        __u64 reserved1 : 6;
   1.138 +        __u64 base : 49;
   1.139 +    };
   1.140 +}   PTA;
   1.141 +
   1.142 +typedef union {
   1.143 +    __u64 val;
   1.144 +    struct {
   1.145 +        __u64  rv  : 16;
   1.146 +        __u64  eid : 8;
   1.147 +        __u64  id  : 8;
   1.148 +        __u64  ig  : 32;
   1.149 +    };
   1.150 +} LID;
   1.151 +
   1.152 +typedef union{
   1.153 +    __u64 val;
   1.154 +    struct {
   1.155 +        __u64 rv  : 3;
   1.156 +        __u64 ir  : 1;
   1.157 +        __u64 eid : 8;
   1.158 +        __u64 id  : 8;
   1.159 +        __u64 ib_base : 44;
   1.160 +    };
   1.161 +} ipi_a_t;
   1.162 +
   1.163 +typedef union{
   1.164 +    __u64 val;
   1.165 +    struct {
   1.166 +        __u64 vector : 8;
   1.167 +        __u64 dm  : 3;
   1.168 +        __u64 ig  : 53;
   1.169 +    };
   1.170 +} ipi_d_t;
   1.171 +
   1.172 +
   1.173 +#define IA64_ISR_CODE_MASK0     0xf
   1.174 +#define IA64_UNIMPL_DADDR_FAULT     0x30
   1.175 +#define IA64_UNIMPL_IADDR_TRAP      0x10
   1.176 +#define IA64_RESERVED_REG_FAULT     0x30
   1.177 +#define IA64_REG_NAT_CONSUMPTION_FAULT  0x10
   1.178 +#define IA64_NAT_CONSUMPTION_FAULT  0x20
   1.179 +#define IA64_PRIV_OP_FAULT      0x10
   1.180 +
   1.181 +/* indirect register type */
   1.182 +enum {
   1.183 +    IA64_CPUID,     /*  cpuid */
   1.184 +    IA64_DBR,       /*  dbr */
   1.185 +    IA64_IBR,       /*  ibr */
   1.186 +    IA64_PKR,       /*  pkr */
   1.187 +    IA64_PMC,       /*  pmc */
   1.188 +    IA64_PMD,       /*  pmd */
   1.189 +    IA64_RR         /*  rr */
   1.190 +};
   1.191 +
   1.192 +/* instruction type */
   1.193 +enum {
   1.194 +    IA64_INST_TPA=1,
   1.195 +    IA64_INST_TAK
   1.196 +};
   1.197 +
   1.198 +/* Generate Mask
   1.199 + * Parameter:
   1.200 + *  bit -- starting bit
   1.201 + *  len -- how many bits
   1.202 + */
   1.203 +#define MASK(bit,len)                   \
   1.204 +({                              \
   1.205 +        __u64    ret;                    \
   1.206 +                                \
   1.207 +        __asm __volatile("dep %0=-1, r0, %1, %2"    \
   1.208 +                : "=r" (ret):                   \
   1.209 +          "M" (bit),                    \
   1.210 +          "M" (len) );                  \
   1.211 +        ret;                            \
   1.212 +})
   1.213 +
   1.214 +#endif  //  CONFIG_VTI
   1.215 +
   1.216 +#endif // _ASM_IA64_XENPROCESSOR_H