ia64/xen-unstable

annotate xen/include/asm-ia64/linux-xen/asm/io.h @ 5974:f242de2e5a3c

Move copy+patched files to linux-xen directory.

Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author adsharma@xuni-t01.sc.intel.com
date Tue Aug 02 16:25:11 2005 -0800 (2005-08-02)
parents
children 1ee9236cc224
rev   line source
adsharma@5974 1 #ifndef _ASM_IA64_IO_H
adsharma@5974 2 #define _ASM_IA64_IO_H
adsharma@5974 3
adsharma@5974 4 /*
adsharma@5974 5 * This file contains the definitions for the emulated IO instructions
adsharma@5974 6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
adsharma@5974 7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
adsharma@5974 8 * versions of the single-IO instructions (inb_p/inw_p/..).
adsharma@5974 9 *
adsharma@5974 10 * This file is not meant to be obfuscating: it's just complicated to
adsharma@5974 11 * (a) handle it all in a way that makes gcc able to optimize it as
adsharma@5974 12 * well as possible and (b) trying to avoid writing the same thing
adsharma@5974 13 * over and over again with slight variations and possibly making a
adsharma@5974 14 * mistake somewhere.
adsharma@5974 15 *
adsharma@5974 16 * Copyright (C) 1998-2003 Hewlett-Packard Co
adsharma@5974 17 * David Mosberger-Tang <davidm@hpl.hp.com>
adsharma@5974 18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
adsharma@5974 19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
adsharma@5974 20 */
adsharma@5974 21
adsharma@5974 22 /* We don't use IO slowdowns on the ia64, but.. */
adsharma@5974 23 #define __SLOW_DOWN_IO do { } while (0)
adsharma@5974 24 #define SLOW_DOWN_IO do { } while (0)
adsharma@5974 25
adsharma@5974 26 #ifdef XEN
adsharma@5974 27 #define __IA64_UNCACHED_OFFSET 0xe800000000000000UL
adsharma@5974 28 #else
adsharma@5974 29 #define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */
adsharma@5974 30 #endif
adsharma@5974 31
adsharma@5974 32 /*
adsharma@5974 33 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
adsharma@5974 34 * large machines may have multiple other I/O spaces so we can't place any a priori limit
adsharma@5974 35 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
adsharma@5974 36 */
adsharma@5974 37 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
adsharma@5974 38
adsharma@5974 39 #define MAX_IO_SPACES_BITS 4
adsharma@5974 40 #define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
adsharma@5974 41 #define IO_SPACE_BITS 24
adsharma@5974 42 #define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
adsharma@5974 43
adsharma@5974 44 #define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
adsharma@5974 45 #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
adsharma@5974 46 #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
adsharma@5974 47
adsharma@5974 48 #define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | (p & 0xfff))
adsharma@5974 49
adsharma@5974 50 struct io_space {
adsharma@5974 51 unsigned long mmio_base; /* base in MMIO space */
adsharma@5974 52 int sparse;
adsharma@5974 53 };
adsharma@5974 54
adsharma@5974 55 extern struct io_space io_space[];
adsharma@5974 56 extern unsigned int num_io_spaces;
adsharma@5974 57
adsharma@5974 58 # ifdef __KERNEL__
adsharma@5974 59
adsharma@5974 60 /*
adsharma@5974 61 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
adsharma@5974 62 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
adsharma@5974 63 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
adsharma@5974 64 *
adsharma@5974 65 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
adsharma@5974 66 * code that uses bare port numbers without the prerequisite pci_iomap().
adsharma@5974 67 */
adsharma@5974 68 #define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
adsharma@5974 69 #define PIO_MASK (PIO_OFFSET - 1)
adsharma@5974 70 #define PIO_RESERVED __IA64_UNCACHED_OFFSET
adsharma@5974 71 #define HAVE_ARCH_PIO_SIZE
adsharma@5974 72
adsharma@5974 73 #include <asm/intrinsics.h>
adsharma@5974 74 #include <asm/machvec.h>
adsharma@5974 75 #include <asm/page.h>
adsharma@5974 76 #include <asm/system.h>
adsharma@5974 77 #include <asm-generic/iomap.h>
adsharma@5974 78
adsharma@5974 79 /*
adsharma@5974 80 * Change virtual addresses to physical addresses and vv.
adsharma@5974 81 */
adsharma@5974 82 static inline unsigned long
adsharma@5974 83 virt_to_phys (volatile void *address)
adsharma@5974 84 {
adsharma@5974 85 return (unsigned long) address - PAGE_OFFSET;
adsharma@5974 86 }
adsharma@5974 87
adsharma@5974 88 static inline void*
adsharma@5974 89 phys_to_virt (unsigned long address)
adsharma@5974 90 {
adsharma@5974 91 return (void *) (address + PAGE_OFFSET);
adsharma@5974 92 }
adsharma@5974 93
adsharma@5974 94 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
adsharma@5974 95 extern int valid_phys_addr_range (unsigned long addr, size_t *count); /* efi.c */
adsharma@5974 96
adsharma@5974 97 /*
adsharma@5974 98 * The following two macros are deprecated and scheduled for removal.
adsharma@5974 99 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
adsharma@5974 100 */
adsharma@5974 101 #define bus_to_virt phys_to_virt
adsharma@5974 102 #define virt_to_bus virt_to_phys
adsharma@5974 103 #define page_to_bus page_to_phys
adsharma@5974 104
adsharma@5974 105 # endif /* KERNEL */
adsharma@5974 106
adsharma@5974 107 /*
adsharma@5974 108 * Memory fence w/accept. This should never be used in code that is
adsharma@5974 109 * not IA-64 specific.
adsharma@5974 110 */
adsharma@5974 111 #define __ia64_mf_a() ia64_mfa()
adsharma@5974 112
adsharma@5974 113 /**
adsharma@5974 114 * ___ia64_mmiowb - I/O write barrier
adsharma@5974 115 *
adsharma@5974 116 * Ensure ordering of I/O space writes. This will make sure that writes
adsharma@5974 117 * following the barrier will arrive after all previous writes. For most
adsharma@5974 118 * ia64 platforms, this is a simple 'mf.a' instruction.
adsharma@5974 119 *
adsharma@5974 120 * See Documentation/DocBook/deviceiobook.tmpl for more information.
adsharma@5974 121 */
adsharma@5974 122 static inline void ___ia64_mmiowb(void)
adsharma@5974 123 {
adsharma@5974 124 ia64_mfa();
adsharma@5974 125 }
adsharma@5974 126
adsharma@5974 127 static inline const unsigned long
adsharma@5974 128 __ia64_get_io_port_base (void)
adsharma@5974 129 {
adsharma@5974 130 extern unsigned long ia64_iobase;
adsharma@5974 131
adsharma@5974 132 return ia64_iobase;
adsharma@5974 133 }
adsharma@5974 134
adsharma@5974 135 static inline void*
adsharma@5974 136 __ia64_mk_io_addr (unsigned long port)
adsharma@5974 137 {
adsharma@5974 138 struct io_space *space;
adsharma@5974 139 unsigned long offset;
adsharma@5974 140
adsharma@5974 141 space = &io_space[IO_SPACE_NR(port)];
adsharma@5974 142 port = IO_SPACE_PORT(port);
adsharma@5974 143 if (space->sparse)
adsharma@5974 144 offset = IO_SPACE_SPARSE_ENCODING(port);
adsharma@5974 145 else
adsharma@5974 146 offset = port;
adsharma@5974 147
adsharma@5974 148 return (void *) (space->mmio_base | offset);
adsharma@5974 149 }
adsharma@5974 150
adsharma@5974 151 #define __ia64_inb ___ia64_inb
adsharma@5974 152 #define __ia64_inw ___ia64_inw
adsharma@5974 153 #define __ia64_inl ___ia64_inl
adsharma@5974 154 #define __ia64_outb ___ia64_outb
adsharma@5974 155 #define __ia64_outw ___ia64_outw
adsharma@5974 156 #define __ia64_outl ___ia64_outl
adsharma@5974 157 #define __ia64_readb ___ia64_readb
adsharma@5974 158 #define __ia64_readw ___ia64_readw
adsharma@5974 159 #define __ia64_readl ___ia64_readl
adsharma@5974 160 #define __ia64_readq ___ia64_readq
adsharma@5974 161 #define __ia64_readb_relaxed ___ia64_readb
adsharma@5974 162 #define __ia64_readw_relaxed ___ia64_readw
adsharma@5974 163 #define __ia64_readl_relaxed ___ia64_readl
adsharma@5974 164 #define __ia64_readq_relaxed ___ia64_readq
adsharma@5974 165 #define __ia64_writeb ___ia64_writeb
adsharma@5974 166 #define __ia64_writew ___ia64_writew
adsharma@5974 167 #define __ia64_writel ___ia64_writel
adsharma@5974 168 #define __ia64_writeq ___ia64_writeq
adsharma@5974 169 #define __ia64_mmiowb ___ia64_mmiowb
adsharma@5974 170
adsharma@5974 171 /*
adsharma@5974 172 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
adsharma@5974 173 * that the access has completed before executing other I/O accesses. Since we're doing
adsharma@5974 174 * the accesses through an uncachable (UC) translation, the CPU will execute them in
adsharma@5974 175 * program order. However, we still need to tell the compiler not to shuffle them around
adsharma@5974 176 * during optimization, which is why we use "volatile" pointers.
adsharma@5974 177 */
adsharma@5974 178
adsharma@5974 179 static inline unsigned int
adsharma@5974 180 ___ia64_inb (unsigned long port)
adsharma@5974 181 {
adsharma@5974 182 volatile unsigned char *addr = __ia64_mk_io_addr(port);
adsharma@5974 183 unsigned char ret;
adsharma@5974 184
adsharma@5974 185 ret = *addr;
adsharma@5974 186 __ia64_mf_a();
adsharma@5974 187 return ret;
adsharma@5974 188 }
adsharma@5974 189
adsharma@5974 190 static inline unsigned int
adsharma@5974 191 ___ia64_inw (unsigned long port)
adsharma@5974 192 {
adsharma@5974 193 volatile unsigned short *addr = __ia64_mk_io_addr(port);
adsharma@5974 194 unsigned short ret;
adsharma@5974 195
adsharma@5974 196 ret = *addr;
adsharma@5974 197 __ia64_mf_a();
adsharma@5974 198 return ret;
adsharma@5974 199 }
adsharma@5974 200
adsharma@5974 201 static inline unsigned int
adsharma@5974 202 ___ia64_inl (unsigned long port)
adsharma@5974 203 {
adsharma@5974 204 volatile unsigned int *addr = __ia64_mk_io_addr(port);
adsharma@5974 205 unsigned int ret;
adsharma@5974 206
adsharma@5974 207 ret = *addr;
adsharma@5974 208 __ia64_mf_a();
adsharma@5974 209 return ret;
adsharma@5974 210 }
adsharma@5974 211
adsharma@5974 212 static inline void
adsharma@5974 213 ___ia64_outb (unsigned char val, unsigned long port)
adsharma@5974 214 {
adsharma@5974 215 volatile unsigned char *addr = __ia64_mk_io_addr(port);
adsharma@5974 216
adsharma@5974 217 *addr = val;
adsharma@5974 218 __ia64_mf_a();
adsharma@5974 219 }
adsharma@5974 220
adsharma@5974 221 static inline void
adsharma@5974 222 ___ia64_outw (unsigned short val, unsigned long port)
adsharma@5974 223 {
adsharma@5974 224 volatile unsigned short *addr = __ia64_mk_io_addr(port);
adsharma@5974 225
adsharma@5974 226 *addr = val;
adsharma@5974 227 __ia64_mf_a();
adsharma@5974 228 }
adsharma@5974 229
adsharma@5974 230 static inline void
adsharma@5974 231 ___ia64_outl (unsigned int val, unsigned long port)
adsharma@5974 232 {
adsharma@5974 233 volatile unsigned int *addr = __ia64_mk_io_addr(port);
adsharma@5974 234
adsharma@5974 235 *addr = val;
adsharma@5974 236 __ia64_mf_a();
adsharma@5974 237 }
adsharma@5974 238
adsharma@5974 239 static inline void
adsharma@5974 240 __insb (unsigned long port, void *dst, unsigned long count)
adsharma@5974 241 {
adsharma@5974 242 unsigned char *dp = dst;
adsharma@5974 243
adsharma@5974 244 while (count--)
adsharma@5974 245 *dp++ = platform_inb(port);
adsharma@5974 246 }
adsharma@5974 247
adsharma@5974 248 static inline void
adsharma@5974 249 __insw (unsigned long port, void *dst, unsigned long count)
adsharma@5974 250 {
adsharma@5974 251 unsigned short *dp = dst;
adsharma@5974 252
adsharma@5974 253 while (count--)
adsharma@5974 254 *dp++ = platform_inw(port);
adsharma@5974 255 }
adsharma@5974 256
adsharma@5974 257 static inline void
adsharma@5974 258 __insl (unsigned long port, void *dst, unsigned long count)
adsharma@5974 259 {
adsharma@5974 260 unsigned int *dp = dst;
adsharma@5974 261
adsharma@5974 262 while (count--)
adsharma@5974 263 *dp++ = platform_inl(port);
adsharma@5974 264 }
adsharma@5974 265
adsharma@5974 266 static inline void
adsharma@5974 267 __outsb (unsigned long port, const void *src, unsigned long count)
adsharma@5974 268 {
adsharma@5974 269 const unsigned char *sp = src;
adsharma@5974 270
adsharma@5974 271 while (count--)
adsharma@5974 272 platform_outb(*sp++, port);
adsharma@5974 273 }
adsharma@5974 274
adsharma@5974 275 static inline void
adsharma@5974 276 __outsw (unsigned long port, const void *src, unsigned long count)
adsharma@5974 277 {
adsharma@5974 278 const unsigned short *sp = src;
adsharma@5974 279
adsharma@5974 280 while (count--)
adsharma@5974 281 platform_outw(*sp++, port);
adsharma@5974 282 }
adsharma@5974 283
adsharma@5974 284 static inline void
adsharma@5974 285 __outsl (unsigned long port, const void *src, unsigned long count)
adsharma@5974 286 {
adsharma@5974 287 const unsigned int *sp = src;
adsharma@5974 288
adsharma@5974 289 while (count--)
adsharma@5974 290 platform_outl(*sp++, port);
adsharma@5974 291 }
adsharma@5974 292
adsharma@5974 293 /*
adsharma@5974 294 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
adsharma@5974 295 * specification regarding legacy I/O support. Thus, we have to make these operations
adsharma@5974 296 * platform dependent...
adsharma@5974 297 */
adsharma@5974 298 #define __inb platform_inb
adsharma@5974 299 #define __inw platform_inw
adsharma@5974 300 #define __inl platform_inl
adsharma@5974 301 #define __outb platform_outb
adsharma@5974 302 #define __outw platform_outw
adsharma@5974 303 #define __outl platform_outl
adsharma@5974 304 #define __mmiowb platform_mmiowb
adsharma@5974 305
adsharma@5974 306 #define inb(p) __inb(p)
adsharma@5974 307 #define inw(p) __inw(p)
adsharma@5974 308 #define inl(p) __inl(p)
adsharma@5974 309 #define insb(p,d,c) __insb(p,d,c)
adsharma@5974 310 #define insw(p,d,c) __insw(p,d,c)
adsharma@5974 311 #define insl(p,d,c) __insl(p,d,c)
adsharma@5974 312 #define outb(v,p) __outb(v,p)
adsharma@5974 313 #define outw(v,p) __outw(v,p)
adsharma@5974 314 #define outl(v,p) __outl(v,p)
adsharma@5974 315 #define outsb(p,s,c) __outsb(p,s,c)
adsharma@5974 316 #define outsw(p,s,c) __outsw(p,s,c)
adsharma@5974 317 #define outsl(p,s,c) __outsl(p,s,c)
adsharma@5974 318 #define mmiowb() __mmiowb()
adsharma@5974 319
adsharma@5974 320 /*
adsharma@5974 321 * The address passed to these functions are ioremap()ped already.
adsharma@5974 322 *
adsharma@5974 323 * We need these to be machine vectors since some platforms don't provide
adsharma@5974 324 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
adsharma@5974 325 * a good idea). Writes are ok though for all existing ia64 platforms (and
adsharma@5974 326 * hopefully it'll stay that way).
adsharma@5974 327 */
adsharma@5974 328 static inline unsigned char
adsharma@5974 329 ___ia64_readb (const volatile void __iomem *addr)
adsharma@5974 330 {
adsharma@5974 331 return *(volatile unsigned char __force *)addr;
adsharma@5974 332 }
adsharma@5974 333
adsharma@5974 334 static inline unsigned short
adsharma@5974 335 ___ia64_readw (const volatile void __iomem *addr)
adsharma@5974 336 {
adsharma@5974 337 return *(volatile unsigned short __force *)addr;
adsharma@5974 338 }
adsharma@5974 339
adsharma@5974 340 static inline unsigned int
adsharma@5974 341 ___ia64_readl (const volatile void __iomem *addr)
adsharma@5974 342 {
adsharma@5974 343 return *(volatile unsigned int __force *) addr;
adsharma@5974 344 }
adsharma@5974 345
adsharma@5974 346 static inline unsigned long
adsharma@5974 347 ___ia64_readq (const volatile void __iomem *addr)
adsharma@5974 348 {
adsharma@5974 349 return *(volatile unsigned long __force *) addr;
adsharma@5974 350 }
adsharma@5974 351
adsharma@5974 352 static inline void
adsharma@5974 353 __writeb (unsigned char val, volatile void __iomem *addr)
adsharma@5974 354 {
adsharma@5974 355 *(volatile unsigned char __force *) addr = val;
adsharma@5974 356 }
adsharma@5974 357
adsharma@5974 358 static inline void
adsharma@5974 359 __writew (unsigned short val, volatile void __iomem *addr)
adsharma@5974 360 {
adsharma@5974 361 *(volatile unsigned short __force *) addr = val;
adsharma@5974 362 }
adsharma@5974 363
adsharma@5974 364 static inline void
adsharma@5974 365 __writel (unsigned int val, volatile void __iomem *addr)
adsharma@5974 366 {
adsharma@5974 367 *(volatile unsigned int __force *) addr = val;
adsharma@5974 368 }
adsharma@5974 369
adsharma@5974 370 static inline void
adsharma@5974 371 __writeq (unsigned long val, volatile void __iomem *addr)
adsharma@5974 372 {
adsharma@5974 373 *(volatile unsigned long __force *) addr = val;
adsharma@5974 374 }
adsharma@5974 375
adsharma@5974 376 #define __readb platform_readb
adsharma@5974 377 #define __readw platform_readw
adsharma@5974 378 #define __readl platform_readl
adsharma@5974 379 #define __readq platform_readq
adsharma@5974 380 #define __readb_relaxed platform_readb_relaxed
adsharma@5974 381 #define __readw_relaxed platform_readw_relaxed
adsharma@5974 382 #define __readl_relaxed platform_readl_relaxed
adsharma@5974 383 #define __readq_relaxed platform_readq_relaxed
adsharma@5974 384
adsharma@5974 385 #define readb(a) __readb((a))
adsharma@5974 386 #define readw(a) __readw((a))
adsharma@5974 387 #define readl(a) __readl((a))
adsharma@5974 388 #define readq(a) __readq((a))
adsharma@5974 389 #define readb_relaxed(a) __readb_relaxed((a))
adsharma@5974 390 #define readw_relaxed(a) __readw_relaxed((a))
adsharma@5974 391 #define readl_relaxed(a) __readl_relaxed((a))
adsharma@5974 392 #define readq_relaxed(a) __readq_relaxed((a))
adsharma@5974 393 #define __raw_readb readb
adsharma@5974 394 #define __raw_readw readw
adsharma@5974 395 #define __raw_readl readl
adsharma@5974 396 #define __raw_readq readq
adsharma@5974 397 #define __raw_readb_relaxed readb_relaxed
adsharma@5974 398 #define __raw_readw_relaxed readw_relaxed
adsharma@5974 399 #define __raw_readl_relaxed readl_relaxed
adsharma@5974 400 #define __raw_readq_relaxed readq_relaxed
adsharma@5974 401 #define writeb(v,a) __writeb((v), (a))
adsharma@5974 402 #define writew(v,a) __writew((v), (a))
adsharma@5974 403 #define writel(v,a) __writel((v), (a))
adsharma@5974 404 #define writeq(v,a) __writeq((v), (a))
adsharma@5974 405 #define __raw_writeb writeb
adsharma@5974 406 #define __raw_writew writew
adsharma@5974 407 #define __raw_writel writel
adsharma@5974 408 #define __raw_writeq writeq
adsharma@5974 409
adsharma@5974 410 #ifndef inb_p
adsharma@5974 411 # define inb_p inb
adsharma@5974 412 #endif
adsharma@5974 413 #ifndef inw_p
adsharma@5974 414 # define inw_p inw
adsharma@5974 415 #endif
adsharma@5974 416 #ifndef inl_p
adsharma@5974 417 # define inl_p inl
adsharma@5974 418 #endif
adsharma@5974 419
adsharma@5974 420 #ifndef outb_p
adsharma@5974 421 # define outb_p outb
adsharma@5974 422 #endif
adsharma@5974 423 #ifndef outw_p
adsharma@5974 424 # define outw_p outw
adsharma@5974 425 #endif
adsharma@5974 426 #ifndef outl_p
adsharma@5974 427 # define outl_p outl
adsharma@5974 428 #endif
adsharma@5974 429
adsharma@5974 430 /*
adsharma@5974 431 * An "address" in IO memory space is not clearly either an integer or a pointer. We will
adsharma@5974 432 * accept both, thus the casts.
adsharma@5974 433 *
adsharma@5974 434 * On ia-64, we access the physical I/O memory space through the uncached kernel region.
adsharma@5974 435 */
adsharma@5974 436 static inline void __iomem *
adsharma@5974 437 ioremap (unsigned long offset, unsigned long size)
adsharma@5974 438 {
adsharma@5974 439 return (void __iomem *) (__IA64_UNCACHED_OFFSET | (offset));
adsharma@5974 440 }
adsharma@5974 441
adsharma@5974 442 static inline void
adsharma@5974 443 iounmap (volatile void __iomem *addr)
adsharma@5974 444 {
adsharma@5974 445 }
adsharma@5974 446
adsharma@5974 447 #define ioremap_nocache(o,s) ioremap(o,s)
adsharma@5974 448
adsharma@5974 449 # ifdef __KERNEL__
adsharma@5974 450
adsharma@5974 451 /*
adsharma@5974 452 * String version of IO memory access ops:
adsharma@5974 453 */
adsharma@5974 454 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
adsharma@5974 455 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
adsharma@5974 456 extern void memset_io(volatile void __iomem *s, int c, long n);
adsharma@5974 457
adsharma@5974 458 #define dma_cache_inv(_start,_size) do { } while (0)
adsharma@5974 459 #define dma_cache_wback(_start,_size) do { } while (0)
adsharma@5974 460 #define dma_cache_wback_inv(_start,_size) do { } while (0)
adsharma@5974 461
adsharma@5974 462 # endif /* __KERNEL__ */
adsharma@5974 463
adsharma@5974 464 /*
adsharma@5974 465 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
adsharma@5974 466 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
adsharma@5974 467 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
adsharma@5974 468 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
adsharma@5974 469 * over BIO-level virtual merging.
adsharma@5974 470 */
adsharma@5974 471 extern unsigned long ia64_max_iommu_merge_mask;
adsharma@5974 472 #if 1
adsharma@5974 473 #define BIO_VMERGE_BOUNDARY 0
adsharma@5974 474 #else
adsharma@5974 475 /*
adsharma@5974 476 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
adsharma@5974 477 * replaced by dma_merge_mask() or something of that sort. Note: the only way
adsharma@5974 478 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
adsharma@5974 479 * expanded into:
adsharma@5974 480 *
adsharma@5974 481 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
adsharma@5974 482 *
adsharma@5974 483 * which is precisely what we want.
adsharma@5974 484 */
adsharma@5974 485 #define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
adsharma@5974 486 #endif
adsharma@5974 487
adsharma@5974 488 #endif /* _ASM_IA64_IO_H */