ia64/xen-unstable

annotate xen/arch/ia64/vmx/pal_emul.c @ 10686:e5c7350b8cbb

[IA64] clean up pal_emul.c compiler warnings

This patch cleans up some compiler warnings in pal_emul.c. The
problem was that a struct ia64_pal_retval was being used to return
the results from emulated PAL calls, but not all of the fields
were being initialized. Given that fields were not initialized,
I was also thinking that there might be a remote chance of data
leaking between vcpu's -- but I haven't convinced myself that
that could actually happen.

Signed-off-by: Al Stone <ahs3@fc.hp.com>
[whitespace and line wrapping cleanup throughout file]
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild.aw
date Mon Jul 10 13:53:17 2006 -0600 (2006-07-10)
parents aa8257def6dc
children 6703fed8870f
rev   line source
djm@6458 1 /*
djm@6458 2 * PAL/SAL call delegation
djm@6458 3 *
djm@6458 4 * Copyright (c) 2004 Li Susie <susie.li@intel.com>
djm@6458 5 * Copyright (c) 2005 Yu Ke <ke.yu@intel.com>
djm@6458 6 *
djm@6458 7 * This program is free software; you can redistribute it and/or modify it
djm@6458 8 * under the terms and conditions of the GNU General Public License,
djm@6458 9 * version 2, as published by the Free Software Foundation.
djm@6458 10 *
djm@6458 11 * This program is distributed in the hope it will be useful, but WITHOUT
djm@6458 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
djm@6458 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
djm@6458 14 * more details.
djm@6458 15 *
djm@6458 16 * You should have received a copy of the GNU General Public License along with
djm@6458 17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
djm@6458 18 * Place - Suite 330, Boston, MA 02111-1307 USA.
djm@6458 19 */
djm@6458 20
djm@6458 21 #include <asm/vmx_vcpu.h>
awilliam@8903 22 #include <asm/pal.h>
awilliam@9154 23 #include <asm/sal.h>
awilliam@10203 24 #include <asm/dom_fw.h>
awilliam@9852 25 #include <asm/tlb.h>
awilliam@9852 26 #include <asm/vmx_mm_def.h>
awilliam@10563 27 #include <xen/hypercall.h>
awilliam@10563 28 #include <public/sched.h>
djm@6458 29
awilliam@10686 30 /*
awilliam@10686 31 * Handy macros to make sure that the PAL return values start out
awilliam@10686 32 * as something meaningful.
awilliam@10686 33 */
awilliam@10686 34 #define INIT_PAL_STATUS_UNIMPLEMENTED(x) \
awilliam@10686 35 { \
awilliam@10686 36 x.status = PAL_STATUS_UNIMPLEMENTED; \
awilliam@10686 37 x.v0 = 0; \
awilliam@10686 38 x.v1 = 0; \
awilliam@10686 39 x.v2 = 0; \
awilliam@10686 40 }
awilliam@10686 41
awilliam@10686 42 #define INIT_PAL_STATUS_SUCCESS(x) \
awilliam@10686 43 { \
awilliam@10686 44 x.status = PAL_STATUS_SUCCESS; \
awilliam@10686 45 x.v0 = 0; \
awilliam@10686 46 x.v1 = 0; \
awilliam@10686 47 x.v2 = 0; \
awilliam@10686 48 }
awilliam@10686 49
djm@6458 50 static void
awilliam@10686 51 get_pal_parameters(VCPU *vcpu, UINT64 *gr29, UINT64 *gr30, UINT64 *gr31) {
djm@6458 52
awilliam@10686 53 vcpu_get_gr_nat(vcpu,29,gr29);
awilliam@10686 54 vcpu_get_gr_nat(vcpu,30,gr30);
awilliam@10686 55 vcpu_get_gr_nat(vcpu,31,gr31);
djm@6458 56 }
djm@6458 57
djm@6458 58 static void
awilliam@10686 59 set_pal_result(VCPU *vcpu,struct ia64_pal_retval result) {
djm@6458 60
djm@6867 61 vcpu_set_gr(vcpu,8, result.status,0);
djm@6867 62 vcpu_set_gr(vcpu,9, result.v0,0);
djm@6867 63 vcpu_set_gr(vcpu,10, result.v1,0);
djm@6867 64 vcpu_set_gr(vcpu,11, result.v2,0);
djm@6458 65 }
djm@6458 66
awilliam@10203 67 static void
awilliam@10686 68 set_sal_result(VCPU *vcpu,struct sal_ret_values result) {
djm@6458 69
awilliam@10203 70 vcpu_set_gr(vcpu,8, result.r8,0);
awilliam@10203 71 vcpu_set_gr(vcpu,9, result.r9,0);
awilliam@10203 72 vcpu_set_gr(vcpu,10, result.r10,0);
awilliam@10203 73 vcpu_set_gr(vcpu,11, result.r11,0);
awilliam@10203 74 }
awilliam@10686 75
djm@6458 76 static struct ia64_pal_retval
awilliam@10686 77 pal_cache_flush(VCPU *vcpu) {
djm@6458 78 UINT64 gr28,gr29, gr30, gr31;
djm@6458 79 struct ia64_pal_retval result;
djm@6458 80
awilliam@10686 81 get_pal_parameters(vcpu, &gr29, &gr30, &gr31);
awilliam@10686 82 vcpu_get_gr_nat(vcpu, 28, &gr28);
djm@6458 83
djm@6458 84 /* Always call Host Pal in int=1 */
awilliam@10686 85 gr30 = gr30 & ~0x2UL;
djm@6458 86
awilliam@10686 87 /*
awilliam@10686 88 * Call Host PAL cache flush
awilliam@10686 89 * Clear psr.ic when call PAL_CACHE_FLUSH
awilliam@10686 90 */
awilliam@10686 91 result = ia64_pal_call_static(gr28 ,gr29, gr30, gr31, 1);
djm@6458 92
djm@6458 93 /* If host PAL call is interrupted, then loop to complete it */
awilliam@10686 94 // while (result.status == 1)
awilliam@10686 95 // ia64_pal_call_static(gr28 ,gr29, gr30, result.v1, 1LL);
awilliam@10686 96 //
awilliam@10686 97 if (result.status != 0)
awilliam@10686 98 panic_domain(vcpu_regs(vcpu), "PAL_CACHE_FLUSH ERROR, "
awilliam@10686 99 "status %ld", result.status);
djm@6458 100
djm@6458 101 return result;
djm@6458 102 }
djm@6458 103
djm@6458 104 static struct ia64_pal_retval
awilliam@10686 105 pal_vm_tr_read(VCPU *vcpu) {
djm@6458 106 struct ia64_pal_retval result;
djm@6458 107
awilliam@10686 108 INIT_PAL_STATUS_UNIMPLEMENTED(result);
djm@6458 109
djm@6458 110 return result;
djm@6458 111 }
djm@6458 112
djm@6458 113 static struct ia64_pal_retval
awilliam@10686 114 pal_prefetch_visibility(VCPU *vcpu) {
djm@6458 115 /* Due to current MM virtualization algorithm,
djm@6458 116 * We do not allow guest to change mapping attribute.
djm@6458 117 * Thus we will not support PAL_PREFETCH_VISIBILITY
djm@6458 118 */
djm@6458 119 struct ia64_pal_retval result;
djm@6458 120
awilliam@10686 121 INIT_PAL_STATUS_UNIMPLEMENTED(result);
djm@6458 122
djm@6458 123 return result;
djm@6458 124 }
djm@6458 125
djm@6458 126 static struct ia64_pal_retval
djm@6458 127 pal_platform_addr(VCPU *vcpu) {
djm@6458 128 struct ia64_pal_retval result;
djm@6458 129
awilliam@10686 130 INIT_PAL_STATUS_SUCCESS(result);
djm@6458 131
djm@6458 132 return result;
djm@6458 133 }
djm@6458 134
djm@6458 135 static struct ia64_pal_retval
awilliam@10686 136 pal_halt(VCPU *vcpu) {
awilliam@10686 137 //bugbug: to be implement.
awilliam@9169 138 struct ia64_pal_retval result;
awilliam@9169 139
awilliam@10686 140 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@9169 141
awilliam@10204 142 return result;
djm@6458 143 }
djm@6458 144
djm@6458 145 static struct ia64_pal_retval
awilliam@10686 146 pal_halt_light(VCPU *vcpu) {
awilliam@10686 147 struct ia64_pal_retval result;
awilliam@10686 148
awilliam@10686 149 if (SPURIOUS_VECTOR == vmx_check_pending_irq(vcpu))
awilliam@10686 150 do_sched_op_compat(SCHEDOP_block, 0);
awilliam@10686 151
awilliam@10686 152 INIT_PAL_STATUS_SUCCESS(result);
djm@6458 153
awilliam@9169 154 return result;
djm@6458 155 }
djm@6458 156
djm@6458 157 static struct ia64_pal_retval
awilliam@10686 158 pal_cache_read(VCPU *vcpu) {
awilliam@9169 159 struct ia64_pal_retval result;
awilliam@9169 160
awilliam@10686 161 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@9169 162
awilliam@9169 163 return result;
djm@6458 164 }
djm@6458 165
djm@6458 166 static struct ia64_pal_retval
awilliam@10686 167 pal_cache_write(VCPU *vcpu) {
awilliam@9169 168 struct ia64_pal_retval result;
awilliam@9169 169
awilliam@10686 170 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 171
awilliam@9169 172 return result;
djm@6458 173 }
djm@6458 174
djm@6458 175 static struct ia64_pal_retval
awilliam@10686 176 pal_bus_get_features(VCPU *vcpu) {
awilliam@9169 177 struct ia64_pal_retval result;
awilliam@9169 178
awilliam@10686 179 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@9169 180
awilliam@9169 181 return result;
djm@6458 182 }
djm@6458 183
djm@6458 184 static struct ia64_pal_retval
awilliam@10686 185 pal_cache_summary(VCPU *vcpu) {
awilliam@10686 186 struct ia64_pal_retval result;
awilliam@10686 187
awilliam@10686 188 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 189
awilliam@10686 190 return result;
awilliam@10686 191 }
awilliam@10686 192
awilliam@10686 193 static struct ia64_pal_retval
awilliam@10686 194 pal_cache_init(VCPU *vcpu) {
awilliam@10686 195 struct ia64_pal_retval result;
awilliam@10686 196
awilliam@10686 197 INIT_PAL_STATUS_SUCCESS(result);
awilliam@10686 198
awilliam@10686 199 return result;
awilliam@10686 200 }
awilliam@10686 201
awilliam@10686 202 static struct ia64_pal_retval
awilliam@10686 203 pal_cache_info(VCPU *vcpu) {
awilliam@10686 204 struct ia64_pal_retval result;
awilliam@10686 205
awilliam@10686 206 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 207
awilliam@10686 208 return result;
awilliam@10686 209 }
awilliam@10686 210
awilliam@10686 211 static struct ia64_pal_retval
awilliam@10686 212 pal_cache_prot_info(VCPU *vcpu) {
awilliam@10686 213 struct ia64_pal_retval result;
awilliam@10686 214
awilliam@10686 215 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 216
awilliam@10686 217 return result;
awilliam@10686 218 }
awilliam@10686 219
awilliam@10686 220 static struct ia64_pal_retval
awilliam@10686 221 pal_mem_attrib(VCPU *vcpu) {
awilliam@10686 222 struct ia64_pal_retval result;
awilliam@10686 223
awilliam@10686 224 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 225
awilliam@10686 226 return result;
awilliam@10686 227 }
awilliam@10686 228
awilliam@10686 229 static struct ia64_pal_retval
awilliam@10686 230 pal_debug_info(VCPU *vcpu) {
awilliam@10686 231 struct ia64_pal_retval result;
awilliam@10686 232
awilliam@10686 233 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 234
awilliam@10686 235 return result;
awilliam@10686 236 }
awilliam@10686 237
awilliam@10686 238 static struct ia64_pal_retval
awilliam@10686 239 pal_fixed_addr(VCPU *vcpu) {
awilliam@10686 240 struct ia64_pal_retval result;
awilliam@10686 241
awilliam@10686 242 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 243
awilliam@10686 244 return result;
awilliam@10686 245 }
awilliam@10686 246
awilliam@10686 247 static struct ia64_pal_retval
awilliam@10686 248 pal_freq_base(VCPU *vcpu) {
awilliam@10686 249 struct ia64_pal_retval result;
awilliam@10686 250 struct ia64_sal_retval isrv;
awilliam@10686 251
awilliam@10686 252 PAL_CALL(result,PAL_FREQ_BASE, 0, 0, 0);
awilliam@10686 253 /*
awilliam@10686 254 * PAL_FREQ_BASE may not be implemented in some platforms,
awilliam@10686 255 * call SAL instead.
awilliam@10686 256 */
awilliam@10686 257 if (result.v0 == 0) {
awilliam@10686 258 SAL_CALL(isrv, SAL_FREQ_BASE,
awilliam@10686 259 SAL_FREQ_BASE_PLATFORM, 0, 0, 0, 0, 0, 0);
awilliam@10686 260 result.status = isrv.status;
awilliam@10686 261 result.v0 = isrv.v0;
awilliam@10686 262 result.v1 = result.v2 = 0;
awilliam@10686 263 }
awilliam@10686 264 return result;
awilliam@10686 265 }
awilliam@10686 266
awilliam@10686 267 static struct ia64_pal_retval
awilliam@10686 268 pal_freq_ratios(VCPU *vcpu) {
awilliam@10686 269 struct ia64_pal_retval result;
awilliam@10686 270
awilliam@10686 271 PAL_CALL(result, PAL_FREQ_RATIOS, 0, 0, 0);
awilliam@10686 272 return result;
awilliam@10686 273 }
awilliam@10686 274
awilliam@10686 275 static struct ia64_pal_retval
awilliam@10686 276 pal_halt_info(VCPU *vcpu) {
awilliam@10686 277 struct ia64_pal_retval result;
awilliam@10686 278
awilliam@10686 279 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 280
awilliam@10686 281 return result;
awilliam@10686 282 }
awilliam@10686 283
awilliam@10686 284 static struct ia64_pal_retval
awilliam@10686 285 pal_logical_to_physica(VCPU *vcpu) {
awilliam@10686 286 struct ia64_pal_retval result;
awilliam@10686 287
awilliam@10686 288 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 289
awilliam@10686 290 return result;
awilliam@10686 291 }
awilliam@10686 292
awilliam@10686 293 static struct ia64_pal_retval
awilliam@10686 294 pal_perf_mon_info(VCPU *vcpu) {
awilliam@10686 295 struct ia64_pal_retval result;
awilliam@10686 296
awilliam@10686 297 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 298
awilliam@10686 299 return result;
awilliam@10686 300 }
awilliam@10686 301
awilliam@10686 302 static struct ia64_pal_retval
awilliam@10686 303 pal_proc_get_features(VCPU *vcpu) {
awilliam@10686 304 struct ia64_pal_retval result;
awilliam@10686 305
awilliam@10686 306 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 307
awilliam@10686 308 return result;
awilliam@10686 309 }
awilliam@10686 310
awilliam@10686 311 static struct ia64_pal_retval
awilliam@10686 312 pal_ptce_info(VCPU *vcpu) {
awilliam@10686 313 struct ia64_pal_retval result;
awilliam@10686 314
awilliam@10686 315 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 316
awilliam@10686 317 return result;
awilliam@10686 318 }
awilliam@10686 319
awilliam@10686 320 static struct ia64_pal_retval
awilliam@10686 321 pal_register_info(VCPU *vcpu) {
awilliam@10686 322 struct ia64_pal_retval result;
awilliam@10686 323
awilliam@10686 324 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 325
awilliam@10686 326 return result;
awilliam@10686 327 }
awilliam@10686 328
awilliam@10686 329 static struct ia64_pal_retval
awilliam@10686 330 pal_rse_info(VCPU *vcpu) {
awilliam@10686 331 struct ia64_pal_retval result;
awilliam@10686 332
awilliam@10686 333 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 334
awilliam@10686 335 return result;
awilliam@10686 336 }
awilliam@10686 337
awilliam@10686 338 static struct ia64_pal_retval
awilliam@10686 339 pal_test_info(VCPU *vcpu) {
awilliam@10686 340 struct ia64_pal_retval result;
awilliam@10686 341
awilliam@10686 342 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 343
awilliam@10686 344 return result;
awilliam@10686 345 }
awilliam@10686 346
awilliam@10686 347 static struct ia64_pal_retval
awilliam@10686 348 pal_vm_summary(VCPU *vcpu) {
awilliam@9852 349 pal_vm_info_1_u_t vminfo1;
awilliam@9852 350 pal_vm_info_2_u_t vminfo2;
awilliam@9169 351 struct ia64_pal_retval result;
awilliam@9852 352
awilliam@10686 353 PAL_CALL(result, PAL_VM_SUMMARY, 0, 0, 0);
awilliam@10686 354 if (!result.status) {
awilliam@9852 355 vminfo1.pvi1_val = result.v0;
awilliam@9852 356 vminfo1.pal_vm_info_1_s.max_itr_entry = NITRS -1;
awilliam@9852 357 vminfo1.pal_vm_info_1_s.max_dtr_entry = NDTRS -1;
awilliam@9852 358 result.v0 = vminfo1.pvi1_val;
awilliam@9852 359 vminfo2.pal_vm_info_2_s.impl_va_msb = GUEST_IMPL_VA_MSB;
awilliam@10686 360 vminfo2.pal_vm_info_2_s.rid_size =
awilliam@10686 361 current->domain->arch.rid_bits;
awilliam@9852 362 result.v1 = vminfo2.pvi2_val;
awilliam@9852 363 }
awilliam@9169 364 return result;
djm@6458 365 }
djm@6458 366
djm@6458 367 static struct ia64_pal_retval
awilliam@10686 368 pal_vm_info(VCPU *vcpu) {
awilliam@9169 369 struct ia64_pal_retval result;
awilliam@9169 370
awilliam@10686 371 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 372
awilliam@9169 373 return result;
djm@6458 374 }
djm@6458 375
djm@6458 376 static struct ia64_pal_retval
awilliam@10686 377 pal_vm_page_size(VCPU *vcpu) {
awilliam@9169 378 struct ia64_pal_retval result;
awilliam@9169 379
awilliam@10686 380 INIT_PAL_STATUS_UNIMPLEMENTED(result);
awilliam@10686 381
awilliam@9169 382 return result;
djm@6458 383 }
awilliam@10686 384
djm@6458 385 void
awilliam@10686 386 pal_emul(VCPU *vcpu) {
djm@6458 387 UINT64 gr28;
djm@6458 388 struct ia64_pal_retval result;
djm@6458 389
djm@6867 390 vcpu_get_gr_nat(vcpu,28,&gr28); //bank1
djm@6458 391
djm@6458 392 switch (gr28) {
djm@6458 393 case PAL_CACHE_FLUSH:
awilliam@10686 394 result = pal_cache_flush(vcpu);
djm@6458 395 break;
djm@6458 396
djm@6458 397 case PAL_PREFETCH_VISIBILITY:
awilliam@10686 398 result = pal_prefetch_visibility(vcpu);
djm@6458 399 break;
djm@6458 400
djm@6458 401 case PAL_VM_TR_READ:
awilliam@10686 402 result = pal_vm_tr_read(vcpu);
djm@6458 403 break;
djm@6458 404
djm@6458 405 case PAL_HALT:
awilliam@10686 406 result = pal_halt(vcpu);
djm@6458 407 break;
djm@6458 408
djm@6458 409 case PAL_HALT_LIGHT:
awilliam@10686 410 result = pal_halt_light(vcpu);
djm@6458 411 break;
djm@6458 412
djm@6458 413 case PAL_CACHE_READ:
awilliam@10686 414 result = pal_cache_read(vcpu);
djm@6458 415 break;
djm@6458 416
djm@6458 417 case PAL_CACHE_WRITE:
awilliam@10686 418 result = pal_cache_write(vcpu);
djm@6458 419 break;
awilliam@8903 420
djm@6458 421 case PAL_PLATFORM_ADDR:
awilliam@10686 422 result = pal_platform_addr(vcpu);
djm@6458 423 break;
djm@6458 424
awilliam@8903 425 case PAL_FREQ_RATIOS:
awilliam@10686 426 result = pal_freq_ratios(vcpu);
awilliam@8903 427 break;
awilliam@8903 428
awilliam@8903 429 case PAL_FREQ_BASE:
awilliam@10686 430 result = pal_freq_base(vcpu);
awilliam@8903 431 break;
awilliam@8903 432
awilliam@9169 433 case PAL_BUS_GET_FEATURES :
awilliam@10686 434 result = pal_bus_get_features(vcpu);
awilliam@9169 435 break;
awilliam@9169 436
awilliam@9169 437 case PAL_CACHE_SUMMARY :
awilliam@10686 438 result = pal_cache_summary(vcpu);
awilliam@9169 439 break;
awilliam@9169 440
awilliam@9169 441 case PAL_CACHE_INIT :
awilliam@9169 442 result = pal_cache_init(vcpu);
awilliam@9169 443 break;
awilliam@9169 444
awilliam@9169 445 case PAL_CACHE_INFO :
awilliam@9169 446 result = pal_cache_info(vcpu);
awilliam@9169 447 break;
awilliam@9169 448
awilliam@9169 449 case PAL_CACHE_PROT_INFO :
awilliam@9169 450 result = pal_cache_prot_info(vcpu);
awilliam@9169 451 break;
awilliam@9169 452
awilliam@9169 453 case PAL_MEM_ATTRIB :
awilliam@9169 454 result = pal_mem_attrib(vcpu);
awilliam@9169 455 break;
awilliam@9169 456
awilliam@9169 457 case PAL_DEBUG_INFO :
awilliam@9169 458 result = pal_debug_info(vcpu);
awilliam@9169 459 break;
awilliam@9169 460
awilliam@9169 461 case PAL_FIXED_ADDR :
awilliam@9169 462 result = pal_fixed_addr(vcpu);
awilliam@9169 463 break;
awilliam@9169 464
awilliam@9169 465 case PAL_HALT_INFO :
awilliam@9169 466 result = pal_halt_info(vcpu);
awilliam@9169 467 break;
awilliam@9169 468
awilliam@9169 469 case PAL_LOGICAL_TO_PHYSICAL :
awilliam@9169 470 result = pal_logical_to_physica(vcpu);
awilliam@9169 471 break;
awilliam@9169 472
awilliam@9169 473 case PAL_PERF_MON_INFO :
awilliam@9169 474 result = pal_perf_mon_info(vcpu);
awilliam@9169 475 break;
awilliam@9169 476
awilliam@9169 477 case PAL_PROC_GET_FEATURES:
awilliam@9169 478 result = pal_proc_get_features(vcpu);
awilliam@9169 479 break;
awilliam@9169 480
awilliam@9169 481 case PAL_PTCE_INFO :
awilliam@9169 482 result = pal_ptce_info(vcpu);
awilliam@9169 483 break;
awilliam@9169 484
awilliam@9169 485 case PAL_REGISTER_INFO :
awilliam@9169 486 result = pal_register_info(vcpu);
awilliam@9169 487 break;
awilliam@9169 488
awilliam@9169 489 case PAL_RSE_INFO :
awilliam@9169 490 result = pal_rse_info(vcpu);
awilliam@9169 491 break;
awilliam@9169 492
awilliam@9169 493 case PAL_TEST_PROC :
awilliam@9169 494 result = pal_test_info(vcpu);
awilliam@9169 495 break;
awilliam@9169 496
awilliam@9169 497 case PAL_VM_SUMMARY :
awilliam@9169 498 result = pal_vm_summary(vcpu);
awilliam@9169 499 break;
awilliam@9169 500
awilliam@9169 501 case PAL_VM_INFO :
awilliam@9169 502 result = pal_vm_info(vcpu);
awilliam@9169 503 break;
awilliam@9169 504
awilliam@9169 505 case PAL_VM_PAGE_SIZE :
awilliam@9169 506 result = pal_vm_page_size(vcpu);
awilliam@9169 507 break;
awilliam@9169 508
djm@6458 509 default:
awilliam@10686 510 panic_domain(vcpu_regs(vcpu),"pal_emul(): guest "
awilliam@10686 511 "call unsupported pal" );
awilliam@10686 512 }
awilliam@10686 513 set_pal_result(vcpu, result);
djm@6458 514 }
djm@6458 515
awilliam@10203 516 void
awilliam@10203 517 sal_emul(VCPU *v) {
awilliam@10203 518 struct sal_ret_values result;
awilliam@10686 519 result = sal_emulator(vcpu_get_gr(v, 32), vcpu_get_gr(v, 33),
awilliam@10686 520 vcpu_get_gr(v, 34), vcpu_get_gr(v, 35),
awilliam@10686 521 vcpu_get_gr(v, 36), vcpu_get_gr(v, 37),
awilliam@10686 522 vcpu_get_gr(v, 38), vcpu_get_gr(v, 39));
awilliam@10203 523 set_sal_result(v, result);
awilliam@10203 524 }