ia64/xen-unstable

annotate xen/include/asm-x86/msr.h @ 3959:da3bec7765d1

bitkeeper revision 1.1236.1.42 (4224bb8fOnbAClkv82bfZwfayrn5Rw)

Fix error-code generation in rdmsr_user and wrmsr_user.
Signed-off-by: Keir Fraser <keir.fraser@cl.cam.ac.uk>
author kaf24@scramble.cl.cam.ac.uk
date Tue Mar 01 18:59:27 2005 +0000 (2005-03-01)
parents f25349622916
children 24703bde489b
rev   line source
kaf24@1452 1 #ifndef __ASM_MSR_H
kaf24@1452 2 #define __ASM_MSR_H
kaf24@1452 3
kaf24@1452 4 #define rdmsr(msr,val1,val2) \
kaf24@1452 5 __asm__ __volatile__("rdmsr" \
kaf24@1452 6 : "=a" (val1), "=d" (val2) \
kaf24@1452 7 : "c" (msr))
kaf24@1452 8
kaf24@1452 9 #define wrmsr(msr,val1,val2) \
kaf24@1452 10 __asm__ __volatile__("wrmsr" \
kaf24@1452 11 : /* no outputs */ \
kaf24@1452 12 : "c" (msr), "a" (val1), "d" (val2))
kaf24@1452 13
kaf24@3861 14 #define rdmsr_user(msr,val1,val2) ({\
kaf24@3959 15 int _rc; \
kaf24@3861 16 __asm__ __volatile__( \
kaf24@3861 17 "1: rdmsr\n2:\n" \
kaf24@3861 18 ".section .fixup,\"ax\"\n" \
kaf24@3861 19 "3: movl $1,%2\n; jmp 2b\n" \
kaf24@3861 20 ".previous\n" \
kaf24@3861 21 ".section __ex_table,\"a\"\n" \
kaf24@3861 22 " "__FIXUP_ALIGN"\n" \
kaf24@3861 23 " "__FIXUP_WORD" 1b,3b\n" \
kaf24@3861 24 ".previous\n" \
kaf24@3959 25 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
kaf24@3959 26 : "c" (msr), "2" (0)); \
kaf24@3861 27 _rc; })
kaf24@3861 28
kaf24@3861 29 #define wrmsr_user(msr,val1,val2) ({\
kaf24@3959 30 int _rc; \
kaf24@3861 31 __asm__ __volatile__( \
kaf24@3861 32 "1: wrmsr\n2:\n" \
kaf24@3861 33 ".section .fixup,\"ax\"\n" \
kaf24@3861 34 "3: movl $1,%0\n; jmp 2b\n" \
kaf24@3861 35 ".previous\n" \
kaf24@3861 36 ".section __ex_table,\"a\"\n" \
kaf24@3861 37 " "__FIXUP_ALIGN"\n" \
kaf24@3861 38 " "__FIXUP_WORD" 1b,3b\n" \
kaf24@3861 39 ".previous\n" \
kaf24@3959 40 : "=&r" (_rc) \
kaf24@3959 41 : "c" (msr), "a" (val1), "d" (val2), "0" (0)); \
kaf24@3861 42 _rc; })
kaf24@3861 43
kaf24@1452 44 #define rdtsc(low,high) \
kaf24@1452 45 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
kaf24@1452 46
kaf24@1452 47 #define rdtscl(low) \
kaf24@1452 48 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
kaf24@1452 49
kaf24@1463 50 #if defined(__i386__)
kaf24@1452 51 #define rdtscll(val) \
kaf24@1452 52 __asm__ __volatile__("rdtsc" : "=A" (val))
kaf24@1463 53 #elif defined(__x86_64__)
kaf24@1452 54 #define rdtscll(val) do { \
kaf24@1452 55 unsigned int a,d; \
kaf24@1452 56 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
kaf24@1452 57 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
kaf24@1452 58 } while(0)
kaf24@1452 59 #endif
kaf24@1452 60
kaf24@1452 61 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
kaf24@1452 62
kaf24@1452 63 #define rdpmc(counter,low,high) \
kaf24@1452 64 __asm__ __volatile__("rdpmc" \
kaf24@1452 65 : "=a" (low), "=d" (high) \
kaf24@1452 66 : "c" (counter))
kaf24@1452 67
kaf24@1452 68 /* symbolic names for some interesting MSRs */
kaf24@1452 69 /* Intel defined MSRs. */
kaf24@1452 70 #define MSR_IA32_P5_MC_ADDR 0
kaf24@1452 71 #define MSR_IA32_P5_MC_TYPE 1
kaf24@1452 72 #define MSR_IA32_PLATFORM_ID 0x17
kaf24@1452 73 #define MSR_IA32_EBL_CR_POWERON 0x2a
kaf24@1452 74
kaf24@1452 75 /* AMD/K8 specific MSRs */
kaf24@1452 76 #define MSR_EFER 0xc0000080 /* extended feature register */
kaf24@1452 77 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
kaf24@1452 78 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
kaf24@1452 79 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
kaf24@1452 80 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
kaf24@1452 81 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */
kaf24@1452 82 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */
kaf24@3761 83 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
kaf24@1452 84 /* EFER bits: */
kaf24@1452 85 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
kaf24@1452 86 #define _EFER_LME 8 /* Long mode enable */
kaf24@1452 87 #define _EFER_LMA 10 /* Long mode active (read-only) */
kaf24@1452 88 #define _EFER_NX 11 /* No execute enable */
kaf24@1452 89
kaf24@1452 90 #define EFER_SCE (1<<_EFER_SCE)
kaf24@1739 91 #define EFER_LME (1<<_EFER_LME)
kaf24@1739 92 #define EFER_LMA (1<<_EFER_LMA)
kaf24@1452 93 #define EFER_NX (1<<_EFER_NX)
kaf24@1452 94
kaf24@1452 95 /* Intel MSRs. Some also available on other CPUs */
kaf24@1452 96 #define MSR_IA32_PLATFORM_ID 0x17
kaf24@1452 97
kaf24@1452 98 #define MSR_IA32_PERFCTR0 0xc1
kaf24@1452 99 #define MSR_IA32_PERFCTR1 0xc2
kaf24@1452 100
kaf24@1452 101 #define MSR_MTRRcap 0x0fe
kaf24@1452 102 #define MSR_IA32_BBL_CR_CTL 0x119
kaf24@1452 103
iap10@3290 104 #define MSR_IA32_SYSENTER_CS 0x174
iap10@3290 105 #define MSR_IA32_SYSENTER_ESP 0x175
iap10@3290 106 #define MSR_IA32_SYSENTER_EIP 0x176
iap10@3290 107
kaf24@1452 108 #define MSR_IA32_MCG_CAP 0x179
kaf24@1452 109 #define MSR_IA32_MCG_STATUS 0x17a
kaf24@1452 110 #define MSR_IA32_MCG_CTL 0x17b
kaf24@1452 111
kaf24@1452 112 #define MSR_IA32_EVNTSEL0 0x186
kaf24@1452 113 #define MSR_IA32_EVNTSEL1 0x187
kaf24@1452 114
kaf24@1452 115 #define MSR_MTRRfix64K_00000 0x250
kaf24@1452 116 #define MSR_MTRRfix16K_80000 0x258
kaf24@1452 117 #define MSR_MTRRfix16K_A0000 0x259
kaf24@1452 118 #define MSR_MTRRfix4K_C0000 0x268
kaf24@1452 119 #define MSR_MTRRfix4K_C8000 0x269
kaf24@1452 120 #define MSR_MTRRfix4K_D0000 0x26a
kaf24@1452 121 #define MSR_MTRRfix4K_D8000 0x26b
kaf24@1452 122 #define MSR_MTRRfix4K_E0000 0x26c
kaf24@1452 123 #define MSR_MTRRfix4K_E8000 0x26d
kaf24@1452 124 #define MSR_MTRRfix4K_F0000 0x26e
kaf24@1452 125 #define MSR_MTRRfix4K_F8000 0x26f
kaf24@1452 126 #define MSR_MTRRdefType 0x2ff
kaf24@1452 127
kaf24@1452 128 #define MSR_IA32_MC0_CTL 0x400
kaf24@1452 129 #define MSR_IA32_MC0_STATUS 0x401
kaf24@1452 130 #define MSR_IA32_MC0_ADDR 0x402
kaf24@1452 131 #define MSR_IA32_MC0_MISC 0x403
kaf24@1452 132
mafetter@3507 133 #define MSR_IA32_DS_AREA 0x600
mafetter@3507 134
kaf24@1452 135 #define MSR_IA32_APICBASE 0x1b
kaf24@1452 136 #define MSR_IA32_APICBASE_BSP (1<<8)
kaf24@1452 137 #define MSR_IA32_APICBASE_ENABLE (1<<11)
kaf24@1452 138 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
kaf24@1452 139
kaf24@1452 140 #define MSR_IA32_UCODE_WRITE 0x79
kaf24@1452 141 #define MSR_IA32_UCODE_REV 0x8b
kaf24@1452 142
kaf24@1452 143 #define MSR_IA32_BBL_CR_CTL 0x119
kaf24@1452 144
kaf24@1452 145 #define MSR_IA32_MCG_CAP 0x179
kaf24@1452 146 #define MSR_IA32_MCG_STATUS 0x17a
kaf24@1452 147 #define MSR_IA32_MCG_CTL 0x17b
kaf24@1452 148
kaf24@1452 149 #define MSR_IA32_THERM_CONTROL 0x19a
kaf24@1452 150 #define MSR_IA32_THERM_INTERRUPT 0x19b
kaf24@1452 151 #define MSR_IA32_THERM_STATUS 0x19c
kaf24@1452 152 #define MSR_IA32_MISC_ENABLE 0x1a0
kaf24@1452 153
mafetter@3507 154 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
mafetter@3507 155 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
mafetter@3507 156 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
mafetter@3507 157
kaf24@1452 158 #define MSR_IA32_DEBUGCTLMSR 0x1d9
mafetter@3507 159 #define MSR_IA32_DEBUGCTLMSR_LBR (1<<0)
mafetter@3507 160 #define MSR_IA32_DEBUGCTLMSR_BTF (1<<1)
mafetter@3507 161 #define MSR_IA32_DEBUGCTLMSR_TR (1<<2)
mafetter@3507 162 #define MSR_IA32_DEBUGCTLMSR_BTS (1<<3)
mafetter@3507 163 #define MSR_IA32_DEBUGCTLMSR_BTINT (1<<4)
mafetter@3507 164
mafetter@3507 165 #define MSR_IA32_LASTBRANCH_TOS 0x1da
mafetter@3507 166 #define MSR_IA32_LASTBRANCH_0 0x1db
mafetter@3507 167 #define MSR_IA32_LASTBRANCH_1 0x1dc
mafetter@3507 168 #define MSR_IA32_LASTBRANCH_2 0x1dd
mafetter@3507 169 #define MSR_IA32_LASTBRANCH_3 0x1de
kaf24@1452 170
kaf24@1452 171 #define MSR_IA32_MC0_CTL 0x400
kaf24@1452 172 #define MSR_IA32_MC0_STATUS 0x401
kaf24@1452 173 #define MSR_IA32_MC0_ADDR 0x402
kaf24@1452 174 #define MSR_IA32_MC0_MISC 0x403
kaf24@1452 175
kaf24@1452 176 #define MSR_P6_PERFCTR0 0xc1
kaf24@1452 177 #define MSR_P6_PERFCTR1 0xc2
kaf24@1452 178 #define MSR_P6_EVNTSEL0 0x186
kaf24@1452 179 #define MSR_P6_EVNTSEL1 0x187
kaf24@1452 180
mafetter@3507 181
kaf24@1452 182 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
kaf24@1452 183 #define MSR_K7_EVNTSEL0 0xC0010000
kaf24@1452 184 #define MSR_K7_PERFCTR0 0xC0010004
kaf24@1452 185 #define MSR_K7_EVNTSEL1 0xC0010001
kaf24@1452 186 #define MSR_K7_PERFCTR1 0xC0010005
kaf24@1452 187 #define MSR_K7_EVNTSEL2 0xC0010002
kaf24@1452 188 #define MSR_K7_PERFCTR2 0xC0010006
kaf24@1452 189 #define MSR_K7_EVNTSEL3 0xC0010003
kaf24@1452 190 #define MSR_K7_PERFCTR3 0xC0010007
kaf24@1452 191 #define MSR_K8_TOP_MEM1 0xC001001A
kaf24@1452 192 #define MSR_K8_TOP_MEM2 0xC001001D
kaf24@1452 193 #define MSR_K8_SYSCFG 0xC0000010
kaf24@1452 194 #define MSR_K7_HWCR 0xC0010015
kaf24@1452 195 #define MSR_K7_CLK_CTL 0xC001001b
kaf24@1452 196 #define MSR_K7_FID_VID_CTL 0xC0010041
kaf24@1452 197 #define MSR_K7_VID_STATUS 0xC0010042
kaf24@1452 198
kaf24@1452 199 /* K6 MSRs */
kaf24@1452 200 #define MSR_K6_EFER 0xC0000080
kaf24@1452 201 #define MSR_K6_STAR 0xC0000081
kaf24@1452 202 #define MSR_K6_WHCR 0xC0000082
kaf24@1452 203 #define MSR_K6_UWCCR 0xC0000085
kaf24@1452 204 #define MSR_K6_EPMR 0xC0000086
kaf24@1452 205 #define MSR_K6_PSOR 0xC0000087
kaf24@1452 206 #define MSR_K6_PFIR 0xC0000088
kaf24@1452 207
kaf24@1452 208 /* Centaur-Hauls/IDT defined MSRs. */
kaf24@1452 209 #define MSR_IDT_FCR1 0x107
kaf24@1452 210 #define MSR_IDT_FCR2 0x108
kaf24@1452 211 #define MSR_IDT_FCR3 0x109
kaf24@1452 212 #define MSR_IDT_FCR4 0x10a
kaf24@1452 213
kaf24@1452 214 #define MSR_IDT_MCR0 0x110
kaf24@1452 215 #define MSR_IDT_MCR1 0x111
kaf24@1452 216 #define MSR_IDT_MCR2 0x112
kaf24@1452 217 #define MSR_IDT_MCR3 0x113
kaf24@1452 218 #define MSR_IDT_MCR4 0x114
kaf24@1452 219 #define MSR_IDT_MCR5 0x115
kaf24@1452 220 #define MSR_IDT_MCR6 0x116
kaf24@1452 221 #define MSR_IDT_MCR7 0x117
kaf24@1452 222 #define MSR_IDT_MCR_CTRL 0x120
kaf24@1452 223
kaf24@1452 224 /* VIA Cyrix defined MSRs*/
kaf24@1452 225 #define MSR_VIA_FCR 0x1107
kaf24@1452 226 #define MSR_VIA_LONGHAUL 0x110a
kaf24@1452 227 #define MSR_VIA_BCR2 0x1147
kaf24@1452 228
kaf24@1452 229 /* Transmeta defined MSRs */
kaf24@1452 230 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
kaf24@1452 231 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
kaf24@1452 232 #define MSR_TMTA_LRTI_READOUT 0x80868018
kaf24@1452 233 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
kaf24@1452 234
kaf24@1452 235 #endif /* __ASM_MSR_H */