ia64/xen-unstable

annotate old/xenolinux-2.4.16-sparse/include/asm-xeno/debugreg.h @ 235:d7d0a23b2e07

bitkeeper revision 1.93 (3e5a4e6bkPheUp3x1uufN2MS3LAB7A)

Latest and Greatest version of XenoLinux based on the Linux-2.4.21-pre4
kernel.
author iap10@labyrinth.cl.cam.ac.uk
date Mon Feb 24 16:55:07 2003 +0000 (2003-02-24)
parents
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iap10@235 1 #ifndef _I386_DEBUGREG_H
iap10@235 2 #define _I386_DEBUGREG_H
iap10@235 3
iap10@235 4
iap10@235 5 /* Indicate the register numbers for a number of the specific
iap10@235 6 debug registers. Registers 0-3 contain the addresses we wish to trap on */
iap10@235 7 #define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
iap10@235 8 #define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
iap10@235 9
iap10@235 10 #define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
iap10@235 11 #define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
iap10@235 12
iap10@235 13 /* Define a few things for the status register. We can use this to determine
iap10@235 14 which debugging register was responsible for the trap. The other bits
iap10@235 15 are either reserved or not of interest to us. */
iap10@235 16
iap10@235 17 #define DR_TRAP0 (0x1) /* db0 */
iap10@235 18 #define DR_TRAP1 (0x2) /* db1 */
iap10@235 19 #define DR_TRAP2 (0x4) /* db2 */
iap10@235 20 #define DR_TRAP3 (0x8) /* db3 */
iap10@235 21
iap10@235 22 #define DR_STEP (0x4000) /* single-step */
iap10@235 23 #define DR_SWITCH (0x8000) /* task switch */
iap10@235 24
iap10@235 25 /* Now define a bunch of things for manipulating the control register.
iap10@235 26 The top two bytes of the control register consist of 4 fields of 4
iap10@235 27 bits - each field corresponds to one of the four debug registers,
iap10@235 28 and indicates what types of access we trap on, and how large the data
iap10@235 29 field is that we are looking at */
iap10@235 30
iap10@235 31 #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
iap10@235 32 #define DR_CONTROL_SIZE 4 /* 4 control bits per register */
iap10@235 33
iap10@235 34 #define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
iap10@235 35 #define DR_RW_WRITE (0x1)
iap10@235 36 #define DR_RW_READ (0x3)
iap10@235 37
iap10@235 38 #define DR_LEN_1 (0x0) /* Settings for data length to trap on */
iap10@235 39 #define DR_LEN_2 (0x4)
iap10@235 40 #define DR_LEN_4 (0xC)
iap10@235 41
iap10@235 42 /* The low byte to the control register determine which registers are
iap10@235 43 enabled. There are 4 fields of two bits. One bit is "local", meaning
iap10@235 44 that the processor will reset the bit after a task switch and the other
iap10@235 45 is global meaning that we have to explicitly reset the bit. With linux,
iap10@235 46 you can use either one, since we explicitly zero the register when we enter
iap10@235 47 kernel mode. */
iap10@235 48
iap10@235 49 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
iap10@235 50 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
iap10@235 51 #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
iap10@235 52
iap10@235 53 #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
iap10@235 54 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
iap10@235 55
iap10@235 56 /* The second byte to the control register has a few special things.
iap10@235 57 We can slow the instruction pipeline for instructions coming via the
iap10@235 58 gdt or the ldt if we want to. I am not sure why this is an advantage */
iap10@235 59
iap10@235 60 #define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
iap10@235 61 #define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
iap10@235 62 #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
iap10@235 63
iap10@235 64 #endif