ia64/xen-unstable

annotate xen/arch/ia64/vmx/vmx_entry.S @ 9770:ced37bea0647

[IA64] FPH enabling + cleanup

Move contents of switch_to macro from xensystem.h to context_switch function.
Initialize FPU on all processors. FPH is always enabled in Xen.
Speed up context-switch (a little bit!) by not enabling/disabling FPH.
Cleanup (unused function/variablesi/fields, debug printf...)
vmx_ia64_switch_to removed (was unused).

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Apr 25 22:35:41 2006 -0600 (2006-04-25)
parents cfe20f41f043
children 70b7d520bda4
rev   line source
djm@6458 1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
djm@6458 2 /*
djm@6458 3 * vmx_entry.S:
djm@6458 4 * Copyright (c) 2005, Intel Corporation.
djm@6458 5 *
djm@6458 6 * This program is free software; you can redistribute it and/or modify it
djm@6458 7 * under the terms and conditions of the GNU General Public License,
djm@6458 8 * version 2, as published by the Free Software Foundation.
djm@6458 9 *
djm@6458 10 * This program is distributed in the hope it will be useful, but WITHOUT
djm@6458 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
djm@6458 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
djm@6458 13 * more details.
djm@6458 14 *
djm@6458 15 * You should have received a copy of the GNU General Public License along with
djm@6458 16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
djm@6458 17 * Place - Suite 330, Boston, MA 02111-1307 USA.
djm@6458 18 *
djm@6458 19 * Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
djm@6458 20 * Kun Tian (Kevin Tian) (kevin.tian@intel.com)
djm@6458 21 */
djm@6458 22
djm@6458 23 #ifndef VCPU_TLB_SHIFT
djm@6458 24 #define VCPU_TLB_SHIFT 22
djm@6458 25 #endif
djm@6458 26 #include <linux/config.h>
djm@6458 27 #include <asm/asmmacro.h>
djm@6458 28 #include <asm/cache.h>
djm@6458 29 #include <asm/kregs.h>
djm@6458 30 #include <asm/offsets.h>
djm@6458 31 #include <asm/pgtable.h>
djm@6458 32 #include <asm/percpu.h>
djm@6458 33 #include <asm/processor.h>
djm@6458 34 #include <asm/thread_info.h>
djm@6458 35 #include <asm/unistd.h>
djm@6469 36 #include <asm/vhpt.h>
awilliam@9011 37 #include <asm/vmmu.h>
djm@6458 38 #include "vmx_minstate.h"
djm@6458 39
djm@6458 40 GLOBAL_ENTRY(ia64_leave_nested)
djm@6458 41 rsm psr.i
djm@6458 42 ;;
djm@6458 43 adds r21=PT(PR)+16,r12
djm@6458 44 ;;
djm@6458 45 lfetch [r21],PT(CR_IPSR)-PT(PR)
djm@6458 46 adds r2=PT(B6)+16,r12
djm@6458 47 adds r3=PT(R16)+16,r12
djm@6458 48 ;;
djm@6458 49 lfetch [r21]
djm@6458 50 ld8 r28=[r2],8 // load b6
djm@6458 51 adds r29=PT(R24)+16,r12
djm@6458 52
djm@6458 53 ld8.fill r16=[r3]
djm@6458 54 adds r3=PT(AR_CSD)-PT(R16),r3
djm@6458 55 adds r30=PT(AR_CCV)+16,r12
djm@6458 56 ;;
djm@6458 57 ld8.fill r24=[r29]
djm@6458 58 ld8 r15=[r30] // load ar.ccv
djm@6458 59 ;;
djm@6458 60 ld8 r29=[r2],16 // load b7
djm@6458 61 ld8 r30=[r3],16 // load ar.csd
djm@6458 62 ;;
djm@6458 63 ld8 r31=[r2],16 // load ar.ssd
djm@6458 64 ld8.fill r8=[r3],16
djm@6458 65 ;;
djm@6458 66 ld8.fill r9=[r2],16
djm@6458 67 ld8.fill r10=[r3],PT(R17)-PT(R10)
djm@6458 68 ;;
djm@6458 69 ld8.fill r11=[r2],PT(R18)-PT(R11)
djm@6458 70 ld8.fill r17=[r3],16
djm@6458 71 ;;
djm@6458 72 ld8.fill r18=[r2],16
djm@6458 73 ld8.fill r19=[r3],16
djm@6458 74 ;;
djm@6458 75 ld8.fill r20=[r2],16
djm@6458 76 ld8.fill r21=[r3],16
djm@6458 77 mov ar.csd=r30
djm@6458 78 mov ar.ssd=r31
djm@6458 79 ;;
djm@6458 80 rsm psr.i | psr.ic // initiate turning off of interrupt and interruption collection
djm@6458 81 invala // invalidate ALAT
djm@6458 82 ;;
djm@6458 83 ld8.fill r22=[r2],24
djm@6458 84 ld8.fill r23=[r3],24
djm@6458 85 mov b6=r28
djm@6458 86 ;;
djm@6458 87 ld8.fill r25=[r2],16
djm@6458 88 ld8.fill r26=[r3],16
djm@6458 89 mov b7=r29
djm@6458 90 ;;
djm@6458 91 ld8.fill r27=[r2],16
djm@6458 92 ld8.fill r28=[r3],16
djm@6458 93 ;;
djm@6458 94 ld8.fill r29=[r2],16
djm@6458 95 ld8.fill r30=[r3],24
djm@6458 96 ;;
djm@6458 97 ld8.fill r31=[r2],PT(F9)-PT(R31)
djm@6458 98 adds r3=PT(F10)-PT(F6),r3
djm@6458 99 ;;
djm@6458 100 ldf.fill f9=[r2],PT(F6)-PT(F9)
djm@6458 101 ldf.fill f10=[r3],PT(F8)-PT(F10)
djm@6458 102 ;;
djm@6458 103 ldf.fill f6=[r2],PT(F7)-PT(F6)
djm@6458 104 ;;
djm@6458 105 ldf.fill f7=[r2],PT(F11)-PT(F7)
djm@6458 106 ldf.fill f8=[r3],32
djm@6458 107 ;;
djm@6458 108 srlz.i // ensure interruption collection is off
djm@6458 109 mov ar.ccv=r15
djm@6458 110 ;;
djm@6458 111 bsw.0 // switch back to bank 0 (no stop bit required beforehand...)
djm@6458 112 ;;
djm@6458 113 ldf.fill f11=[r2]
djm@6458 114 // mov r18=r13
djm@6458 115 // mov r21=r13
djm@6458 116 adds r16=PT(CR_IPSR)+16,r12
djm@6458 117 adds r17=PT(CR_IIP)+16,r12
djm@6458 118 ;;
djm@6458 119 ld8 r29=[r16],16 // load cr.ipsr
djm@6458 120 ld8 r28=[r17],16 // load cr.iip
djm@6458 121 ;;
djm@6458 122 ld8 r30=[r16],16 // load cr.ifs
djm@6458 123 ld8 r25=[r17],16 // load ar.unat
djm@6458 124 ;;
djm@6458 125 ld8 r26=[r16],16 // load ar.pfs
djm@6458 126 ld8 r27=[r17],16 // load ar.rsc
djm@6458 127 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
djm@6458 128 ;;
djm@6458 129 ld8 r24=[r16],16 // load ar.rnat (may be garbage)
djm@6458 130 ld8 r23=[r17],16// load ar.bspstore (may be garbage)
djm@6458 131 ;;
djm@6458 132 ld8 r31=[r16],16 // load predicates
djm@6458 133 ld8 r22=[r17],16 // load b0
djm@6458 134 ;;
djm@6458 135 ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
djm@6458 136 ld8.fill r1=[r17],16 // load r1
djm@6458 137 ;;
djm@6458 138 ld8.fill r12=[r16],16
djm@6458 139 ld8.fill r13=[r17],16
djm@6458 140 ;;
djm@6458 141 ld8 r20=[r16],16 // ar.fpsr
djm@6458 142 ld8.fill r15=[r17],16
djm@6458 143 ;;
djm@6458 144 ld8.fill r14=[r16],16
djm@6458 145 ld8.fill r2=[r17]
djm@6458 146 ;;
djm@6458 147 ld8.fill r3=[r16]
djm@6458 148 ;;
djm@6458 149 mov r16=ar.bsp // get existing backing store pointer
djm@6458 150 ;;
djm@6458 151 mov b0=r22
djm@6458 152 mov ar.pfs=r26
djm@6458 153 mov cr.ifs=r30
djm@6458 154 mov cr.ipsr=r29
djm@6458 155 mov ar.fpsr=r20
djm@6458 156 mov cr.iip=r28
djm@6458 157 ;;
djm@6458 158 mov ar.rsc=r27
djm@6458 159 mov ar.unat=r25
djm@6458 160 mov pr=r31,-1
djm@6458 161 rfi
djm@6458 162 END(ia64_leave_nested)
djm@6458 163
djm@6458 164
djm@6458 165
djm@6458 166 GLOBAL_ENTRY(ia64_leave_hypervisor)
djm@6458 167 PT_REGS_UNWIND_INFO(0)
djm@6458 168 /*
djm@6458 169 * work.need_resched etc. mustn't get changed by this CPU before it returns to
djm@6458 170 ;;
djm@6458 171 * user- or fsys-mode, hence we disable interrupts early on:
djm@6458 172 */
djm@6458 173 rsm psr.i
djm@6458 174 ;;
djm@6458 175 alloc loc0=ar.pfs,0,1,1,0
djm@6458 176 adds out0=16,r12
djm@6867 177 adds r7 = PT(EML_UNAT)+16,r12
djm@6458 178 ;;
djm@6867 179 ld8 r7 = [r7]
djm@6458 180 br.call.sptk.many b0=leave_hypervisor_tail
djm@6801 181 ;;
djm@6458 182 mov ar.pfs=loc0
djm@6458 183 mov ar.unat=r7
djm@6458 184 adds r20=PT(PR)+16,r12
djm@6458 185 ;;
djm@6458 186 lfetch [r20],PT(CR_IPSR)-PT(PR)
djm@6867 187 adds r2 = PT(B6)+16,r12
djm@6867 188 adds r3 = PT(B7)+16,r12
djm@6458 189 ;;
djm@6458 190 lfetch [r20]
djm@6458 191 ;;
djm@6867 192 ld8 r24=[r2],16 /* B6 */
djm@6867 193 ld8 r25=[r3],16 /* B7 */
djm@6458 194 ;;
djm@6867 195 ld8 r26=[r2],16 /* ar_csd */
djm@6867 196 ld8 r27=[r3],16 /* ar_ssd */
djm@6867 197 mov b6 = r24
djm@6458 198 ;;
djm@6867 199 ld8.fill r8=[r2],16
djm@6867 200 ld8.fill r9=[r3],16
djm@6867 201 mov b7 = r25
djm@6458 202 ;;
djm@6867 203 mov ar.csd = r26
djm@6867 204 mov ar.ssd = r27
djm@6867 205 ;;
djm@6867 206 ld8.fill r10=[r2],PT(R15)-PT(R10)
djm@6867 207 ld8.fill r11=[r3],PT(R14)-PT(R11)
djm@6867 208 ;;
djm@6867 209 ld8.fill r15=[r2],PT(R16)-PT(R15)
djm@6867 210 ld8.fill r14=[r3],PT(R17)-PT(R14)
djm@6867 211 ;;
djm@6867 212 ld8.fill r16=[r2],16
djm@6867 213 ld8.fill r17=[r3],16
djm@6867 214 ;;
djm@6867 215 ld8.fill r18=[r2],16
djm@6867 216 ld8.fill r19=[r3],16
djm@6867 217 ;;
djm@6867 218 ld8.fill r20=[r2],16
djm@6867 219 ld8.fill r21=[r3],16
djm@6867 220 ;;
djm@6867 221 ld8.fill r22=[r2],16
djm@6867 222 ld8.fill r23=[r3],16
djm@6867 223 ;;
djm@6867 224 ld8.fill r24=[r2],16
djm@6867 225 ld8.fill r25=[r3],16
djm@6867 226 ;;
djm@6867 227 ld8.fill r26=[r2],16
djm@6867 228 ld8.fill r27=[r3],16
djm@6867 229 ;;
djm@6867 230 ld8.fill r28=[r2],16
djm@6867 231 ld8.fill r29=[r3],16
djm@6867 232 ;;
djm@6867 233 ld8.fill r30=[r2],PT(F6)-PT(R30)
djm@6867 234 ld8.fill r31=[r3],PT(F7)-PT(R31)
djm@6867 235 ;;
djm@6458 236 rsm psr.i | psr.ic // initiate turning off of interrupt and interruption collection
djm@6867 237 invala // invalidate ALAT
djm@6867 238 ;;
djm@6867 239 ldf.fill f6=[r2],32
djm@6867 240 ldf.fill f7=[r3],32
djm@6867 241 ;;
djm@6867 242 ldf.fill f8=[r2],32
djm@6867 243 ldf.fill f9=[r3],32
djm@6867 244 ;;
djm@6867 245 ldf.fill f10=[r2],32
djm@6867 246 ldf.fill f11=[r3],24
djm@6867 247 ;;
djm@6867 248 ld8.fill r4=[r2],16 //load r4
djm@6867 249 ld8.fill r5=[r3],16 //load r5
djm@6867 250 ;;
djm@6867 251 ld8.fill r6=[r2] //load r6
djm@6867 252 ld8.fill r7=[r3] //load r7
djm@6458 253 ;;
djm@6458 254 srlz.i // ensure interruption collection is off
djm@6458 255 ;;
djm@6867 256 bsw.0
djm@6458 257 ;;
djm@6867 258 adds r16 = PT(CR_IPSR)+16,r12
djm@6867 259 adds r17 = PT(CR_IIP)+16,r12
djm@6867 260 mov r21=r13 // get current
djm@6458 261 ;;
djm@6458 262 ld8 r31=[r16],16 // load cr.ipsr
djm@6458 263 ld8 r30=[r17],16 // load cr.iip
djm@6458 264 ;;
djm@6458 265 ld8 r29=[r16],16 // load cr.ifs
djm@6458 266 ld8 r28=[r17],16 // load ar.unat
djm@6458 267 ;;
djm@6458 268 ld8 r27=[r16],16 // load ar.pfs
djm@6458 269 ld8 r26=[r17],16 // load ar.rsc
djm@6458 270 ;;
djm@6867 271 ld8 r25=[r16],16 // load ar.rnat
djm@6867 272 ld8 r24=[r17],16 // load ar.bspstore
djm@6458 273 ;;
djm@6458 274 ld8 r23=[r16],16 // load predicates
djm@6867 275 ld8 r22=[r17],16 // load b0
djm@6458 276 ;;
djm@6458 277 ld8 r20=[r16],16 // load ar.rsc value for "loadrs"
djm@6867 278 ld8.fill r1=[r17],16 //load r1
djm@6867 279 ;;
djm@6867 280 ld8.fill r12=[r16],16 //load r12
djm@6867 281 ld8.fill r13=[r17],PT(R2)-PT(R13) //load r13
djm@6867 282 ;;
djm@6867 283 ld8 r19=[r16],PT(R3)-PT(AR_FPSR) //load ar_fpsr
djm@6867 284 ld8.fill r2=[r17],PT(AR_CCV)-PT(R2) //load r2
djm@6867 285 ;;
djm@6867 286 ld8.fill r3=[r16] //load r3
djm@6867 287 ld8 r18=[r17],PT(RFI_PFS)-PT(AR_CCV) //load ar_ccv
djm@6867 288 ;;
djm@6867 289 mov ar.fpsr=r19
djm@6867 290 mov ar.ccv=r18
djm@6458 291 ;;
djm@6458 292 //rbs_switch
djm@6458 293 // loadrs has already been shifted
djm@6458 294 alloc r16=ar.pfs,0,0,0,0 // drop current register frame
djm@6458 295 ;;
djm@6458 296 mov ar.rsc=r20
djm@6458 297 ;;
djm@6458 298 loadrs
djm@6458 299 ;;
djm@6458 300 mov ar.bspstore=r24
djm@6458 301 ;;
djm@6458 302 ld8 r24=[r17] //load rfi_pfs
djm@6458 303 mov ar.unat=r28
djm@6458 304 mov ar.rnat=r25
djm@6458 305 mov ar.rsc=r26
djm@6458 306 ;;
djm@6458 307 mov cr.ipsr=r31
djm@6458 308 mov cr.iip=r30
djm@6458 309 mov cr.ifs=r29
djm@6458 310 cmp.ne p6,p0=r24,r0
djm@6458 311 (p6)br.sptk vmx_dorfirfi
djm@6458 312 ;;
djm@6458 313 vmx_dorfirfi_back:
djm@6458 314 mov ar.pfs=r27
djm@6867 315 adds r18=IA64_VPD_BASE_OFFSET,r21
djm@6867 316 ;;
djm@6867 317 ld8 r18=[r18] //vpd
djm@6867 318 ;;
djm@6867 319 adds r19=VPD(VPSR),r18
djm@6867 320 ;;
djm@6867 321 ld8 r19=[r19] //vpsr
djm@6458 322 //vsa_sync_write_start
djm@6458 323 movl r20=__vsa_base
djm@6458 324 ;;
djm@6458 325 ld8 r20=[r20] // read entry point
djm@6458 326 mov r25=r18
djm@6458 327 ;;
djm@6458 328 add r16=PAL_VPS_SYNC_WRITE,r20
djm@6458 329 movl r24=switch_rr7 // calculate return address
djm@6458 330 ;;
djm@6458 331 mov b0=r16
djm@6458 332 br.cond.sptk b0 // call the service
djm@6458 333 ;;
djm@6469 334 switch_rr7:
djm@6458 335 // fall through
djm@6458 336 GLOBAL_ENTRY(ia64_vmm_entry)
djm@6458 337 /*
djm@6458 338 * must be at bank 0
djm@6458 339 * parameter:
djm@6458 340 * r18:vpd
djm@6458 341 * r19:vpsr
djm@6458 342 * r20:__vsa_base
djm@6458 343 * r22:b0
djm@6458 344 * r23:predicate
djm@6458 345 */
djm@6458 346 mov r24=r22
djm@6458 347 mov r25=r18
djm@6458 348 tbit.nz p1,p2 = r19,IA64_PSR_IC_BIT // p1=vpsr.ic
djm@6458 349 ;;
djm@6458 350 (p1) add r29=PAL_VPS_RESUME_NORMAL,r20
djm@6458 351 (p2) add r29=PAL_VPS_RESUME_HANDLER,r20
djm@6458 352 ;;
djm@6458 353 mov pr=r23,-2
djm@6458 354 mov b0=r29
djm@6458 355 ;;
djm@6458 356 br.cond.sptk b0 // call pal service
djm@6458 357 END(ia64_leave_hypervisor)
djm@6458 358
djm@6458 359 //r24 rfi_pfs
djm@6458 360 //r17 address of rfi_pfs
djm@6458 361 GLOBAL_ENTRY(vmx_dorfirfi)
djm@6458 362 mov r16=ar.ec
djm@6458 363 movl r20 = vmx_dorfirfi_back
djm@6458 364 ;;
djm@6458 365 // clean rfi_pfs
djm@6458 366 st8 [r17]=r0
djm@6458 367 mov b0=r20
djm@6458 368 // pfs.pec=ar.ec
djm@6458 369 dep r24 = r16, r24, 52, 6
djm@6458 370 ;;
djm@6458 371 mov ar.pfs=r24
djm@6458 372 ;;
djm@6458 373 br.ret.sptk b0
djm@6458 374 ;;
djm@6458 375 END(vmx_dorfirfi)
djm@6458 376
djm@6469 377 #ifdef XEN_DBL_MAPPING /* will be removed */
djm@6458 378
djm@6458 379 #define VMX_PURGE_RR7 0
djm@6458 380 #define VMX_INSERT_RR7 1
djm@6458 381 /*
djm@6458 382 * in0: old rr7
djm@6458 383 * in1: virtual address of xen image
djm@6458 384 * in2: virtual address of vhpt table
djm@6458 385 */
djm@6458 386 GLOBAL_ENTRY(vmx_purge_double_mapping)
djm@6458 387 alloc loc1 = ar.pfs,5,9,0,0
djm@6458 388 mov loc0 = rp
djm@6458 389 movl r8 = 1f
djm@6458 390 ;;
djm@6458 391 movl loc4 = KERNEL_TR_PAGE_SHIFT
djm@6458 392 movl loc5 = VCPU_TLB_SHIFT
djm@6458 393 mov loc6 = psr
djm@6458 394 movl loc7 = XEN_RR7_SWITCH_STUB
djm@6458 395 mov loc8 = (1<<VMX_PURGE_RR7)
djm@6458 396 ;;
djm@6458 397 srlz.i
djm@6458 398 ;;
djm@6458 399 rsm psr.i | psr.ic
djm@6458 400 ;;
djm@6458 401 srlz.i
djm@6458 402 ;;
djm@6458 403 mov ar.rsc = 0
djm@6458 404 mov b6 = loc7
djm@6458 405 mov rp = r8
djm@6458 406 ;;
djm@6458 407 br.sptk b6
djm@6458 408 1:
djm@6458 409 mov ar.rsc = 3
djm@6458 410 mov rp = loc0
djm@6458 411 ;;
djm@6458 412 mov psr.l = loc6
djm@6458 413 ;;
djm@6458 414 srlz.i
djm@6458 415 ;;
djm@6458 416 br.ret.sptk rp
djm@6458 417 END(vmx_purge_double_mapping)
djm@6458 418
djm@6458 419 /*
djm@6458 420 * in0: new rr7
djm@6458 421 * in1: virtual address of xen image
djm@6458 422 * in2: virtual address of vhpt table
djm@6458 423 * in3: pte entry of xen image
djm@6458 424 * in4: pte entry of vhpt table
djm@6458 425 */
djm@6458 426 GLOBAL_ENTRY(vmx_insert_double_mapping)
djm@6458 427 alloc loc1 = ar.pfs,5,9,0,0
djm@6458 428 mov loc0 = rp
djm@6458 429 movl loc2 = IA64_TR_XEN_IN_DOM // TR number for xen image
djm@6458 430 ;;
djm@6458 431 movl loc3 = IA64_TR_VHPT_IN_DOM // TR number for vhpt table
djm@6458 432 movl r8 = 1f
djm@6458 433 movl loc4 = KERNEL_TR_PAGE_SHIFT
djm@6458 434 ;;
djm@6458 435 movl loc5 = VCPU_TLB_SHIFT
djm@6458 436 mov loc6 = psr
djm@6458 437 movl loc7 = XEN_RR7_SWITCH_STUB
djm@6458 438 ;;
djm@6458 439 srlz.i
djm@6458 440 ;;
djm@6458 441 rsm psr.i | psr.ic
djm@6458 442 mov loc8 = (1<<VMX_INSERT_RR7)
djm@6458 443 ;;
djm@6458 444 srlz.i
djm@6458 445 ;;
djm@6458 446 mov ar.rsc = 0
djm@6458 447 mov b6 = loc7
djm@6458 448 mov rp = r8
djm@6458 449 ;;
djm@6458 450 br.sptk b6
djm@6458 451 1:
djm@6458 452 mov ar.rsc = 3
djm@6458 453 mov rp = loc0
djm@6458 454 ;;
djm@6458 455 mov psr.l = loc6
djm@6458 456 ;;
djm@6458 457 srlz.i
djm@6458 458 ;;
djm@6458 459 br.ret.sptk rp
djm@6458 460 END(vmx_insert_double_mapping)
djm@6458 461
djm@6458 462 .align PAGE_SIZE
djm@6458 463 /*
djm@6458 464 * Stub to add double mapping for new domain, which shouldn't
djm@6458 465 * access any memory when active. Before reaching this point,
djm@6458 466 * both psr.i/ic is cleared and rse is set in lazy mode.
djm@6458 467 *
djm@6458 468 * in0: new rr7
djm@6458 469 * in1: virtual address of xen image
djm@6458 470 * in2: virtual address of vhpt table
djm@6458 471 * in3: pte entry of xen image
djm@6458 472 * in4: pte entry of vhpt table
djm@6458 473 * loc2: TR number for xen image
djm@6458 474 * loc3: TR number for vhpt table
djm@6458 475 * loc4: page size for xen image
djm@6458 476 * loc5: page size of vhpt table
djm@6458 477 * loc7: free to use
djm@6458 478 * loc8: purge or insert
djm@6458 479 * r8: will contain old rid value
djm@6458 480 */
djm@6458 481 GLOBAL_ENTRY(vmx_switch_rr7)
djm@6458 482 movl loc7 = (7<<61)
djm@6458 483 dep.z loc4 = loc4, 2, 6
djm@6458 484 dep.z loc5 = loc5, 2, 6
djm@6458 485 ;;
djm@6458 486 tbit.nz p6,p7=loc8, VMX_INSERT_RR7
djm@6458 487 mov r8 = rr[loc7]
djm@6458 488 ;;
djm@6458 489 mov rr[loc7] = in0
djm@6458 490 (p6)mov cr.ifa = in1
djm@6458 491 (p6)mov cr.itir = loc4
djm@6458 492 ;;
djm@6458 493 srlz.i
djm@6458 494 ;;
djm@6458 495 (p6)itr.i itr[loc2] = in3
djm@6458 496 (p7)ptr.i in1, loc4
djm@6458 497 ;;
djm@6458 498 (p6)itr.d dtr[loc2] = in3
djm@6458 499 (p7)ptr.d in1, loc4
djm@6458 500 ;;
djm@6458 501 srlz.i
djm@6458 502 ;;
djm@6458 503 (p6)mov cr.ifa = in2
djm@6458 504 (p6)mov cr.itir = loc5
djm@6458 505 ;;
djm@6458 506 (p6)itr.d dtr[loc3] = in4
djm@6458 507 (p7)ptr.d in2, loc5
djm@6458 508 ;;
djm@6458 509 srlz.i
djm@6458 510 ;;
djm@6458 511 mov rr[loc7] = r8
djm@6458 512 ;;
djm@6458 513 srlz.i
djm@6458 514 br.sptk rp
djm@6458 515 END(vmx_switch_rr7)
djm@6458 516 .align PAGE_SIZE
djm@6469 517
djm@6469 518 #else
djm@6469 519 /*
djm@6469 520 * in0: new rr7
djm@6469 521 * in1: virtual address of shared_info
djm@6469 522 * in2: virtual address of shared_arch_info (VPD)
djm@6469 523 * in3: virtual address of guest_vhpt
djm@6469 524 * in4: virtual address of pal code segment
djm@6469 525 * r8: will contain old rid value
djm@6469 526 */
djm@6469 527
djm@6469 528
djm@6469 529 #define PSR_BITS_TO_CLEAR \
djm@6469 530 (IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB |IA64_PSR_RT | \
djm@6469 531 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \
djm@6469 532 IA64_PSR_DFL | IA64_PSR_DFH)
djm@6469 533 #define PSR_BITS_TO_SET IA64_PSR_BN
djm@6469 534
djm@6469 535 //extern void vmx_switch_rr7(unsigned long rid,void *shared_info, void *shared_arch_info, void *guest_vhpt, void * pal_vaddr );
djm@6469 536
djm@6469 537 GLOBAL_ENTRY(vmx_switch_rr7)
djm@6469 538 // not sure this unwind statement is correct...
djm@6469 539 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(1)
djm@6469 540 alloc loc1 = ar.pfs, 5, 9, 0, 0
djm@6469 541 1: {
djm@6469 542 mov r28 = in0 // copy procedure index
djm@6469 543 mov r8 = ip // save ip to compute branch
djm@6469 544 mov loc0 = rp // save rp
djm@6469 545 };;
djm@6469 546 .body
djm@6469 547 movl loc2=PERCPU_ADDR
djm@6469 548 ;;
djm@6469 549 tpa loc2 = loc2 // get physical address of per cpu date
djm@6469 550 ;;
djm@6469 551 dep loc3 = 0,in1,60,4 // get physical address of shared_info
djm@6469 552 dep loc4 = 0,in2,60,4 // get physical address of shared_arch_info
djm@6469 553 dep loc5 = 0,in3,60,4 // get physical address of guest_vhpt
djm@6469 554 dep loc6 = 0,in4,60,4 // get physical address of pal code
djm@6469 555 ;;
djm@6469 556 mov loc7 = psr // save psr
djm@6469 557 ;;
djm@6469 558 mov loc8 = ar.rsc // save RSE configuration
djm@6469 559 ;;
djm@6469 560 mov ar.rsc = 0 // put RSE in enforced lazy, LE mode
djm@6469 561 movl r16=PSR_BITS_TO_CLEAR
djm@6469 562 movl r17=PSR_BITS_TO_SET
djm@6469 563 ;;
djm@6469 564 or loc7 = loc7,r17 // add in psr the bits to set
djm@6469 565 ;;
djm@6469 566 andcm r16=loc7,r16 // removes bits to clear from psr
djm@6469 567 br.call.sptk.many rp=ia64_switch_mode_phys
djm@6469 568 1:
djm@6469 569 // now in physical mode with psr.i/ic off so do rr7 switch
djm@6469 570 dep r16=-1,r0,61,3
djm@6469 571 ;;
djm@6469 572 mov rr[r16]=in0
djm@6469 573 srlz.d
djm@6469 574 ;;
djm@6469 575 rsm 0x6000
djm@6469 576 ;;
djm@6469 577 srlz.d
djm@6469 578
djm@6469 579 // re-pin mappings for kernel text and data
djm@6469 580 mov r18=KERNEL_TR_PAGE_SHIFT<<2
djm@6469 581 movl r17=KERNEL_START
djm@6469 582 ;;
djm@6469 583 ptr.i r17,r18
djm@6469 584 ptr.d r17,r18
djm@6469 585 ;;
djm@6469 586 mov cr.itir=r18
djm@6469 587 mov cr.ifa=r17
djm@6469 588 mov r16=IA64_TR_KERNEL
djm@6469 589 //mov r3=ip
djm@6469 590 movl r25 = PAGE_KERNEL
djm@6469 591 ;;
djm@6469 592 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
djm@6469 593 ;;
djm@6469 594 or r18=r2,r25
djm@6469 595 ;;
djm@6469 596 srlz.i
djm@6469 597 ;;
djm@6469 598 itr.i itr[r16]=r18
djm@6469 599 ;;
djm@6469 600 itr.d dtr[r16]=r18
djm@6469 601 ;;
djm@6469 602
djm@6469 603 // re-pin mappings for per-cpu data
djm@6469 604
djm@6469 605 movl r22 = PERCPU_ADDR
djm@6469 606 ;;
djm@6469 607 mov r24=IA64_TR_PERCPU_DATA
djm@6469 608 or loc2 = r25,loc2 // construct PA | page properties
djm@6469 609 mov r23=PERCPU_PAGE_SHIFT<<2
djm@6469 610 ;;
djm@6469 611 ptr.d r22,r23
djm@6469 612 ;;
djm@6469 613 mov cr.itir=r23
djm@6469 614 mov cr.ifa=r22
djm@6469 615 ;;
djm@6469 616 itr.d dtr[r24]=loc2 // wire in new mapping...
djm@6469 617 ;;
djm@6469 618
djm@6469 619
djm@6469 620 #if 0
djm@6469 621 // re-pin mappings for shared_info
djm@6469 622
djm@6469 623 mov r24=IA64_TR_SHARED_INFO
djm@6469 624 movl r25=__pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RW)
djm@6469 625 ;;
djm@6469 626 or loc3 = r25,loc3 // construct PA | page properties
djm@6469 627 mov r23 = PAGE_SHIFT<<2
djm@6469 628 ;;
djm@6469 629 ptr.d in1,r23
djm@6469 630 ;;
djm@6469 631 mov cr.itir=r23
djm@6469 632 mov cr.ifa=in1
djm@6469 633 ;;
djm@6469 634 itr.d dtr[r24]=loc3 // wire in new mapping...
djm@6469 635 ;;
djm@6469 636 // re-pin mappings for shared_arch_info
djm@6469 637
djm@6469 638 mov r24=IA64_TR_ARCH_INFO
djm@6469 639 or loc4 = r25,loc4 // construct PA | page properties
djm@6469 640 mov r23 = PAGE_SHIFT<<2
djm@6469 641 ;;
djm@6469 642 ptr.d in2,r23
djm@6469 643 ;;
djm@6469 644 mov cr.itir=r23
djm@6469 645 mov cr.ifa=in2
djm@6469 646 ;;
djm@6469 647 itr.d dtr[r24]=loc4 // wire in new mapping...
djm@6469 648 ;;
djm@6469 649 #endif
djm@6469 650
djm@6469 651
djm@6469 652 // re-pin mappings for guest_vhpt
djm@6469 653
djm@7333 654 mov r24=IA64_TR_PERVP_VHPT
djm@6469 655 movl r25=PAGE_KERNEL
djm@6469 656 ;;
djm@6469 657 or loc5 = r25,loc5 // construct PA | page properties
awilliam@9011 658 mov r23 = VCPU_VHPT_SHIFT <<2
djm@6469 659 ;;
djm@6469 660 ptr.d in3,r23
djm@6469 661 ;;
djm@6469 662 mov cr.itir=r23
djm@6469 663 mov cr.ifa=in3
djm@6469 664 ;;
djm@6469 665 itr.d dtr[r24]=loc5 // wire in new mapping...
djm@6469 666 ;;
djm@6469 667
djm@6469 668 // re-pin mappings for PAL code section
djm@6469 669
djm@6469 670 mov r24=IA64_TR_PALCODE
djm@6469 671 or loc6 = r25,loc6 // construct PA | page properties
djm@6469 672 mov r23 = IA64_GRANULE_SHIFT<<2
djm@6469 673 ;;
djm@6469 674 ptr.i in4,r23
djm@6469 675 ;;
djm@6469 676 mov cr.itir=r23
djm@6469 677 mov cr.ifa=in4
djm@6469 678 ;;
djm@6469 679 itr.i itr[r24]=loc6 // wire in new mapping...
djm@6469 680 ;;
djm@6469 681
djm@6469 682 // done, switch back to virtual and return
djm@6469 683 mov r16=loc7 // r16= original psr
djm@6469 684 br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
djm@6469 685 mov ar.pfs = loc1
djm@6469 686 mov rp = loc0
djm@6469 687 ;;
djm@6469 688 mov ar.rsc=loc8 // restore RSE configuration
djm@6469 689 srlz.d // seralize restoration of psr.l
djm@6469 690 br.ret.sptk.many rp
djm@6469 691 END(vmx_switch_rr7)
djm@6469 692 #endif
djm@6469 693