ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 4620:caaf9d543bc5

bitkeeper revision 1.1357 (4267c91c8u7H5ttS9RWRyBY5FrTm3g)

Fix APIC setup on legacy systems.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Apr 21 15:39:08 2005 +0000 (2005-04-21)
parents 67c40314aa6e
children 38a02ee9a9c8 65b28c74cec2
rev   line source
kaf24@1452 1 /*
iap10@4548 2 * based on linux-2.6.10/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kaf24@1452 13 * Maciej W. Rozycki : Various updates and fixes.
kaf24@1452 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
iap10@4548 37 #include <asm/mach_apic.h>
iap10@4548 38 #include <asm/io_ports.h>
kaf24@1452 39
kaf24@1452 40 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 41 int using_apic_timer = 0;
kaf24@1452 42
kaf24@1452 43 static int enabled_via_apicbase;
kaf24@1452 44
kaf24@1452 45 int get_maxlvt(void)
kaf24@1452 46 {
kaf24@1452 47 unsigned int v, ver, maxlvt;
kaf24@1452 48
kaf24@1452 49 v = apic_read(APIC_LVR);
kaf24@1452 50 ver = GET_APIC_VERSION(v);
kaf24@1452 51 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 52 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 53 return maxlvt;
kaf24@1452 54 }
kaf24@1452 55
kaf24@1452 56 void clear_local_APIC(void)
kaf24@1452 57 {
kaf24@1452 58 int maxlvt;
kaf24@1452 59 unsigned long v;
kaf24@1452 60
kaf24@1452 61 maxlvt = get_maxlvt();
kaf24@1452 62
kaf24@1452 63 /*
kaf24@1452 64 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 65 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 66 */
kaf24@1452 67 if (maxlvt >= 3) {
kaf24@1452 68 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 69 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 70 }
kaf24@1452 71 /*
kaf24@1452 72 * Careful: we have to set masks only first to deassert
kaf24@1452 73 * any level-triggered sources.
kaf24@1452 74 */
kaf24@1452 75 v = apic_read(APIC_LVTT);
kaf24@1452 76 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 77 v = apic_read(APIC_LVT0);
kaf24@1452 78 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 79 v = apic_read(APIC_LVT1);
kaf24@1452 80 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 81 if (maxlvt >= 4) {
kaf24@1452 82 v = apic_read(APIC_LVTPC);
kaf24@1452 83 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 84 }
kaf24@1452 85
kaf24@1452 86 /*
kaf24@1452 87 * Clean APIC state for other OSs:
kaf24@1452 88 */
kaf24@1452 89 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 90 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 91 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 92 if (maxlvt >= 3)
kaf24@1452 93 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 94 if (maxlvt >= 4)
kaf24@1452 95 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 96
kaf24@1452 97 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@1452 98 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 99 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 100 apic_write(APIC_ESR, 0);
kaf24@1452 101 apic_read(APIC_ESR);
kaf24@1452 102 }
kaf24@1452 103 }
kaf24@1452 104
kaf24@1452 105 void __init connect_bsp_APIC(void)
kaf24@1452 106 {
kaf24@1452 107 if (pic_mode) {
kaf24@1452 108 /*
kaf24@1452 109 * Do not trust the local APIC being empty at bootup.
kaf24@1452 110 */
kaf24@1452 111 clear_local_APIC();
kaf24@1452 112 /*
kaf24@1452 113 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 114 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 115 */
kaf24@1452 116 printk("leaving PIC mode, enabling APIC mode.\n");
kaf24@1452 117 outb(0x70, 0x22);
kaf24@1452 118 outb(0x01, 0x23);
kaf24@1452 119 }
kaf24@1452 120 }
kaf24@1452 121
kaf24@1452 122 void disconnect_bsp_APIC(void)
kaf24@1452 123 {
kaf24@1452 124 if (pic_mode) {
kaf24@1452 125 /*
kaf24@1452 126 * Put the board back into PIC mode (has an effect
kaf24@1452 127 * only on certain older boards). Note that APIC
kaf24@1452 128 * interrupts, including IPIs, won't work beyond
kaf24@1452 129 * this point! The only exception are INIT IPIs.
kaf24@1452 130 */
kaf24@1452 131 printk("disabling APIC mode, entering PIC mode.\n");
kaf24@1452 132 outb(0x70, 0x22);
kaf24@1452 133 outb(0x00, 0x23);
kaf24@1452 134 }
kaf24@1452 135 }
kaf24@1452 136
kaf24@1452 137 void disable_local_APIC(void)
kaf24@1452 138 {
kaf24@1452 139 unsigned long value;
kaf24@1452 140
kaf24@1452 141 clear_local_APIC();
kaf24@1452 142
kaf24@1452 143 /*
kaf24@1452 144 * Disable APIC (implies clearing of registers
kaf24@1452 145 * for 82489DX!).
kaf24@1452 146 */
kaf24@1452 147 value = apic_read(APIC_SPIV);
kaf24@1452 148 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 149 apic_write_around(APIC_SPIV, value);
kaf24@1452 150
kaf24@1452 151 if (enabled_via_apicbase) {
kaf24@1452 152 unsigned int l, h;
kaf24@1452 153 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 154 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 155 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 156 }
kaf24@1452 157 }
kaf24@1452 158
kaf24@1452 159 /*
kaf24@1452 160 * This is to verify that we're looking at a real local APIC.
kaf24@1452 161 * Check these against your board if the CPUs aren't getting
kaf24@1452 162 * started for no apparent reason.
kaf24@1452 163 */
kaf24@1452 164 int __init verify_local_APIC(void)
kaf24@1452 165 {
kaf24@1452 166 unsigned int reg0, reg1;
kaf24@1452 167
kaf24@1452 168 /*
kaf24@1452 169 * The version register is read-only in a real APIC.
kaf24@1452 170 */
kaf24@1452 171 reg0 = apic_read(APIC_LVR);
kaf24@1452 172 Dprintk("Getting VERSION: %x\n", reg0);
kaf24@1452 173 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 174 reg1 = apic_read(APIC_LVR);
kaf24@1452 175 Dprintk("Getting VERSION: %x\n", reg1);
kaf24@1452 176
kaf24@1452 177 /*
kaf24@1452 178 * The two version reads above should print the same
kaf24@1452 179 * numbers. If the second one is different, then we
kaf24@1452 180 * poke at a non-APIC.
kaf24@1452 181 */
kaf24@1452 182 if (reg1 != reg0)
kaf24@1452 183 return 0;
kaf24@1452 184
kaf24@1452 185 /*
kaf24@1452 186 * Check if the version looks reasonably.
kaf24@1452 187 */
kaf24@1452 188 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 189 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 190 return 0;
kaf24@1452 191 reg1 = get_maxlvt();
kaf24@1452 192 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 193 return 0;
kaf24@1452 194
kaf24@1452 195 /*
kaf24@1452 196 * The ID register is read/write in a real APIC.
kaf24@1452 197 */
kaf24@1452 198 reg0 = apic_read(APIC_ID);
kaf24@1452 199 Dprintk("Getting ID: %x\n", reg0);
kaf24@1452 200
kaf24@1452 201 /*
kaf24@1452 202 * The next two are just to see if we have sane values.
kaf24@1452 203 * They're only really relevant if we're in Virtual Wire
kaf24@1452 204 * compatibility mode, but most boxes are anymore.
kaf24@1452 205 */
kaf24@1452 206 reg0 = apic_read(APIC_LVT0);
kaf24@1452 207 Dprintk("Getting LVT0: %x\n", reg0);
kaf24@1452 208 reg1 = apic_read(APIC_LVT1);
kaf24@1452 209 Dprintk("Getting LVT1: %x\n", reg1);
kaf24@1452 210
kaf24@1452 211 return 1;
kaf24@1452 212 }
kaf24@1452 213
kaf24@1452 214 void __init sync_Arb_IDs(void)
kaf24@1452 215 {
iap10@4548 216 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
iap10@4548 217 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
iap10@4548 218 if (ver >= 0x14) /* P4 or higher */
iap10@4548 219 return;
kaf24@1452 220 /*
kaf24@1452 221 * Wait for idle.
kaf24@1452 222 */
kaf24@1452 223 apic_wait_icr_idle();
kaf24@1452 224
kaf24@1452 225 Dprintk("Synchronizing Arb IDs.\n");
kaf24@1452 226 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 227 | APIC_DM_INIT);
kaf24@1452 228 }
kaf24@1452 229
kaf24@1452 230 extern void __error_in_apic_c (void);
kaf24@1452 231
kaf24@1452 232 void __init init_bsp_APIC(void)
kaf24@1452 233 {
kaf24@4620 234 unsigned long value, ver;
kaf24@4620 235
kaf24@4620 236 /*
kaf24@4620 237 * Don't do the setup now if we have a SMP BIOS as the through-I/O-APIC
kaf24@4620 238 * virtual wire mode might be active.
kaf24@4620 239 */
kaf24@4620 240 if (smp_found_config || !cpu_has_apic)
kaf24@4620 241 return;
kaf24@4620 242
kaf24@4620 243 value = apic_read(APIC_LVR);
kaf24@4620 244 ver = GET_APIC_VERSION(value);
kaf24@4620 245
kaf24@4620 246 /*
kaf24@4620 247 * Do not trust the local APIC being empty at bootup.
kaf24@4620 248 */
kaf24@4620 249 clear_local_APIC();
kaf24@4620 250
kaf24@4620 251 /*
kaf24@4620 252 * Enable APIC.
kaf24@4620 253 */
kaf24@4620 254 value = apic_read(APIC_SPIV);
kaf24@4620 255 value &= ~APIC_VECTOR_MASK;
kaf24@4620 256 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 257
kaf24@4620 258 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 259 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 260 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 261 else
kaf24@4620 262 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 263 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 264 apic_write_around(APIC_SPIV, value);
kaf24@4620 265
kaf24@4620 266 /*
kaf24@4620 267 * Set up the virtual wire mode.
kaf24@4620 268 */
kaf24@4620 269 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 270 value = APIC_DM_NMI;
kaf24@4620 271 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 272 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 273 apic_write_around(APIC_LVT1, value);
kaf24@1452 274 }
kaf24@1452 275
kaf24@1452 276 void __init setup_local_APIC (void)
kaf24@1452 277 {
iap10@4548 278 unsigned long oldvalue, value, ver, maxlvt;
iap10@4548 279
iap10@4548 280 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 281 if (esr_disable) {
iap10@4548 282 apic_write(APIC_ESR, 0);
iap10@4548 283 apic_write(APIC_ESR, 0);
iap10@4548 284 apic_write(APIC_ESR, 0);
iap10@4548 285 apic_write(APIC_ESR, 0);
iap10@4548 286 }
kaf24@1452 287
kaf24@1452 288 value = apic_read(APIC_LVR);
kaf24@1452 289 ver = GET_APIC_VERSION(value);
kaf24@1452 290
kaf24@1452 291 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 292 __error_in_apic_c();
kaf24@1452 293
iap10@4548 294 /*
iap10@4548 295 * Double-check whether this APIC is really registered.
iap10@4548 296 */
iap10@4548 297 if (!apic_id_registered())
kaf24@1452 298 BUG();
kaf24@1452 299
kaf24@1452 300 /*
kaf24@1452 301 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 302 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 303 * document number 292116). So here it goes...
kaf24@1452 304 */
iap10@4548 305 init_apic_ldr();
kaf24@1452 306
kaf24@1452 307 /*
kaf24@1452 308 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 309 * later on.
kaf24@1452 310 */
kaf24@1452 311 value = apic_read(APIC_TASKPRI);
kaf24@1452 312 value &= ~APIC_TPRI_MASK;
kaf24@1452 313 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 314
kaf24@1452 315 /*
kaf24@1452 316 * Now that we are all set up, enable the APIC
kaf24@1452 317 */
kaf24@1452 318 value = apic_read(APIC_SPIV);
kaf24@1452 319 value &= ~APIC_VECTOR_MASK;
kaf24@1452 320 /*
kaf24@1452 321 * Enable APIC
kaf24@1452 322 */
kaf24@1452 323 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 324
iap10@4548 325 /*
iap10@4548 326 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 327 * certain networking cards. If high frequency interrupts are
iap10@4548 328 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 329 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 330 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 331 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 332 * away, oh well :-(
iap10@4548 333 *
iap10@4548 334 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 335 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 336 * BX chipset. ]
iap10@4548 337 */
iap10@4548 338 /*
iap10@4548 339 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 340 * frequent as it makes the interrupt distributon model be more
iap10@4548 341 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 342 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 343 */
iap10@4548 344 #if 1
kaf24@1452 345 /* Enable focus processor (bit==0) */
kaf24@1452 346 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 347 #else
iap10@4548 348 /* Disable focus processor (bit==1) */
iap10@4548 349 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 350 #endif
iap10@4548 351 /*
iap10@4548 352 * Set spurious IRQ vector
iap10@4548 353 */
kaf24@1452 354 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 355 apic_write_around(APIC_SPIV, value);
kaf24@1452 356
kaf24@1452 357 /*
kaf24@1452 358 * Set up LVT0, LVT1:
kaf24@1452 359 *
kaf24@1452 360 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 361 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 362 * we delegate interrupts to the 8259A.
kaf24@1452 363 */
kaf24@1452 364 /*
kaf24@1452 365 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 366 */
kaf24@1452 367 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 368 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 369 value = APIC_DM_EXTINT;
kaf24@1452 370 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
kaf24@1452 371 } else {
kaf24@1452 372 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@1452 373 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
kaf24@1452 374 }
kaf24@1452 375 apic_write_around(APIC_LVT0, value);
kaf24@1452 376
kaf24@1452 377 /*
kaf24@1452 378 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 379 */
kaf24@1452 380 if (!smp_processor_id())
kaf24@1452 381 value = APIC_DM_NMI;
kaf24@1452 382 else
kaf24@1452 383 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 384 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 385 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 386 apic_write_around(APIC_LVT1, value);
kaf24@1452 387
iap10@4548 388 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 389 maxlvt = get_maxlvt();
kaf24@1452 390 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 391 apic_write(APIC_ESR, 0);
iap10@4548 392 oldvalue = apic_read(APIC_ESR);
kaf24@1452 393
iap10@4548 394 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 395 apic_write_around(APIC_LVTERR, value);
iap10@4548 396 /*
iap10@4548 397 * spec says clear errors after enabling vector.
iap10@4548 398 */
kaf24@1452 399 if (maxlvt > 3)
kaf24@1452 400 apic_write(APIC_ESR, 0);
kaf24@1452 401 value = apic_read(APIC_ESR);
iap10@4548 402 if (value != oldvalue)
iap10@4548 403 printk("ESR value before enabling vector: 0x%08lx "
iap10@4548 404 "after: 0x%08lx\n", oldvalue, value);
kaf24@1452 405 } else {
iap10@4548 406 if (esr_disable)
iap10@4548 407 /*
iap10@4548 408 * Something untraceble is creating bad interrupts on
iap10@4548 409 * secondary quads ... for the moment, just leave the
iap10@4548 410 * ESR disabled - we can't do anything useful with the
iap10@4548 411 * errors anyway - mbligh
iap10@4548 412 */
iap10@4548 413 printk("Leaving ESR disabled.\n");
iap10@4548 414 else
kaf24@1452 415 printk("No ESR for 82489DX.\n");
kaf24@1452 416 }
kaf24@1452 417
iap10@4548 418 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@1452 419 setup_apic_nmi_watchdog();
kaf24@1452 420 }
kaf24@1452 421
kaf24@1452 422 /*
kaf24@1452 423 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 424 * Original code written by Keir Fraser.
kaf24@1452 425 */
kaf24@1452 426
kaf24@1452 427 static int __init detect_init_APIC (void)
kaf24@1452 428 {
kaf24@1452 429 u32 h, l, features;
kaf24@1452 430 extern void get_cpu_vendor(struct cpuinfo_x86*);
kaf24@1452 431
kaf24@1452 432 /* Workaround for us being called before identify_cpu(). */
kaf24@1452 433 get_cpu_vendor(&boot_cpu_data);
kaf24@1452 434
kaf24@1452 435 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 436 case X86_VENDOR_AMD:
iap10@4548 437 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 438 (boot_cpu_data.x86 == 15))
kaf24@1452 439 break;
kaf24@1452 440 goto no_apic;
kaf24@1452 441 case X86_VENDOR_INTEL:
iap10@4548 442 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 443 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 444 break;
kaf24@1452 445 goto no_apic;
kaf24@1452 446 default:
kaf24@1452 447 goto no_apic;
kaf24@1452 448 }
kaf24@1452 449
kaf24@1452 450 if (!cpu_has_apic) {
kaf24@1452 451 /*
kaf24@1452 452 * Some BIOSes disable the local APIC in the
kaf24@1452 453 * APIC_BASE MSR. This can only be done in
iap10@4548 454 * software for Intel P6 or later and AMD K7
iap10@4548 455 * (Model > 1) or later.
kaf24@1452 456 */
kaf24@1452 457 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 458 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 459 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 460 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 461 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 462 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 463 enabled_via_apicbase = 1;
kaf24@1452 464 }
kaf24@1452 465 }
kaf24@4619 466
kaf24@4619 467 /* The APIC feature bit should now be enabled in `cpuid' */
kaf24@1452 468 features = cpuid_edx(1);
kaf24@1452 469 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 470 printk("Could not enable APIC!\n");
kaf24@1452 471 return -1;
kaf24@1452 472 }
kaf24@4619 473
iap10@4548 474 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 475 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 476
kaf24@1452 477 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 478 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 479 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 480 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 481
kaf24@4619 482 if (nmi_watchdog != NMI_NONE)
kaf24@4619 483 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 484
kaf24@1452 485 printk("Found and enabled local APIC!\n");
iap10@4548 486
kaf24@1452 487 return 0;
kaf24@1452 488
iap10@4548 489 no_apic:
kaf24@1452 490 printk("No local APIC present or hardware disabled\n");
kaf24@1452 491 return -1;
kaf24@1452 492 }
kaf24@1452 493
kaf24@1452 494 void __init init_apic_mappings(void)
kaf24@1452 495 {
iap10@4548 496 unsigned long apic_phys;
kaf24@1452 497
kaf24@1452 498 /*
iap10@4548 499 * If no local APIC can be found then set up a fake all
iap10@4548 500 * zeroes page to simulate the local APIC and another
iap10@4548 501 * one for the IO-APIC.
kaf24@1452 502 */
kaf24@1452 503 if (!smp_found_config && detect_init_APIC()) {
kaf24@1920 504 apic_phys = alloc_xenheap_page();
kaf24@1452 505 apic_phys = __pa(apic_phys);
kaf24@1452 506 } else
kaf24@1452 507 apic_phys = mp_lapic_addr;
kaf24@1452 508
kaf24@1452 509 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@1452 510 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
kaf24@1452 511
kaf24@1452 512 /*
kaf24@1452 513 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 514 * default configuration (or the MP table is broken).
kaf24@1452 515 */
kaf24@1452 516 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 517 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 518
kaf24@1452 519 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 520 {
iap10@4548 521 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 522 int i;
kaf24@1452 523
kaf24@1452 524 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 525 if (smp_found_config) {
kaf24@1452 526 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 527 if (!ioapic_phys) {
iap10@4548 528 printk(KERN_ERR
iap10@4548 529 "WARNING: bogus zero IO-APIC "
iap10@4548 530 "address found in MPTABLE, "
iap10@4548 531 "disabling IO/APIC support!\n");
iap10@4548 532 smp_found_config = 0;
iap10@4548 533 skip_ioapic_setup = 1;
iap10@4548 534 goto fake_ioapic_page;
iap10@4548 535 }
iap10@4548 536 } else {
iap10@4548 537 fake_ioapic_page:
iap10@4548 538 ioapic_phys = alloc_xenheap_page();
iap10@4548 539 ioapic_phys = __pa(ioapic_phys);
iap10@4548 540 }
kaf24@1452 541 set_fixmap_nocache(idx, ioapic_phys);
kaf24@1452 542 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
kaf24@1508 543 fix_to_virt(idx), ioapic_phys);
kaf24@1452 544 idx++;
kaf24@1452 545 }
kaf24@1452 546 }
kaf24@1452 547 #endif
kaf24@1452 548 }
kaf24@1452 549
kaf24@1452 550 /*****************************************************************************
kaf24@1452 551 * APIC calibration
kaf24@1452 552 *
kaf24@1452 553 * The APIC is programmed in bus cycles.
kaf24@1452 554 * Timeout values should specified in real time units.
kaf24@1452 555 * The "cheapest" time source is the cyclecounter.
kaf24@1452 556 *
kaf24@1452 557 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 558 *
kaf24@1452 559 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 560 * timer chip to generate periodic timer interupts.
kaf24@1452 561 *****************************************************************************/
kaf24@1452 562
kaf24@1452 563 /* used for system time scaling */
kaf24@1672 564 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 565 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 566 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 567
kaf24@1452 568 /*
kaf24@1452 569 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 570 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 571 * to calibrate.
kaf24@1452 572 */
kaf24@1452 573 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 574 {
kaf24@1452 575 /*extern spinlock_t i8253_lock;*/
kaf24@1452 576 /*unsigned long flags;*/
iap10@4548 577
kaf24@1452 578 unsigned int count;
iap10@4548 579
kaf24@1452 580 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 581
iap10@4548 582 outb_p(0x00, PIT_MODE);
iap10@4548 583 count = inb_p(PIT_CH0);
iap10@4548 584 count |= inb_p(PIT_CH0) << 8;
iap10@4548 585
kaf24@1452 586 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 587
kaf24@1452 588 return count;
kaf24@1452 589 }
kaf24@1452 590
iap10@4548 591 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 592 static void __init wait_8254_wraparound(void)
kaf24@1452 593 {
kaf24@1452 594 unsigned int curr_count, prev_count=~0;
kaf24@1452 595 int delta;
iap10@4548 596
kaf24@1452 597 curr_count = get_8254_timer_count();
iap10@4548 598
kaf24@1452 599 do {
kaf24@1452 600 prev_count = curr_count;
kaf24@1452 601 curr_count = get_8254_timer_count();
kaf24@1452 602 delta = curr_count-prev_count;
iap10@4548 603
kaf24@1452 604 /*
kaf24@4619 605 * This limit for delta seems arbitrary, but it isn't, it's slightly
kaf24@4619 606 * above the level of error a buggy Mercury/Neptune chipset timer can
kaf24@4619 607 * cause.
kaf24@1452 608 */
kaf24@1452 609 } while (delta < 300);
kaf24@1452 610 }
kaf24@1452 611
kaf24@1452 612 /*
iap10@4548 613 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 614 * we override this later
iap10@4548 615 */
iap10@4548 616 void (*wait_timer_tick)(void) = wait_8254_wraparound;
iap10@4548 617
iap10@4548 618 /*
kaf24@1452 619 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 620 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@1452 621 * this function with a very large value and read the current time after
kaf24@1452 622 * a well defined period of time as expired.
kaf24@1452 623 *
kaf24@1452 624 * Calibration is only performed once, for CPU0!
kaf24@1452 625 *
kaf24@1452 626 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 627 * P5 APIC double write bug.
kaf24@1452 628 */
iap10@4548 629
kaf24@1452 630 #define APIC_DIVISOR 1
iap10@4548 631
kaf24@1452 632 static void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 633 {
iap10@4548 634 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 635
iap10@4548 636 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 637 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 638 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 639 if (!APIC_INTEGRATED(ver))
iap10@4548 640 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 641 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 642
kaf24@1452 643 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 644 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 645
kaf24@1452 646 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 647 }
kaf24@1452 648
kaf24@1452 649 /*
kaf24@1452 650 * this is done for every CPU from setup_APIC_clocks() below.
kaf24@1452 651 * We setup each local APIC with a zero timeout value for now.
kaf24@1452 652 * Unlike Linux, we don't have to wait for slices etc.
kaf24@1452 653 */
kaf24@1452 654 void setup_APIC_timer(void * data)
kaf24@1452 655 {
kaf24@1452 656 unsigned long flags;
kaf24@1452 657 __save_flags(flags);
kaf24@1452 658 __sti();
kaf24@1452 659 __setup_APIC_LVTT(0);
kaf24@1452 660 __restore_flags(flags);
kaf24@1452 661 }
kaf24@1452 662
kaf24@1452 663 /*
kaf24@1452 664 * In this function we calibrate APIC bus clocks to the external timer.
kaf24@1452 665 *
iap10@4548 666 * As a result we have the Bus Speed and CPU speed in Hz.
kaf24@1452 667 *
kaf24@1452 668 * We want to do the calibration only once (for CPU0). CPUs connected by the
kaf24@1452 669 * same APIC bus have the very same bus frequency.
kaf24@1452 670 *
kaf24@1452 671 * This bit is a bit shoddy since we use the very same periodic timer interrupt
kaf24@1452 672 * we try to eliminate to calibrate the APIC.
kaf24@1452 673 */
kaf24@1452 674
kaf24@1452 675 int __init calibrate_APIC_clock(void)
kaf24@1452 676 {
kaf24@1452 677 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 678 long tt1, tt2;
kaf24@1452 679 long result;
kaf24@1452 680 int i;
kaf24@1452 681 const int LOOPS = HZ/10;
kaf24@1452 682
kaf24@1452 683 printk("Calibrating APIC timer for CPU%d...\n", smp_processor_id());
kaf24@1452 684
iap10@4548 685 /*
iap10@4548 686 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 687 * value into the APIC clock, we just want to get the
iap10@4548 688 * counter running for calibration.
iap10@4548 689 */
kaf24@1452 690 __setup_APIC_LVTT(1000000000);
kaf24@1452 691
iap10@4548 692 /*
iap10@4548 693 * The timer chip counts down to zero. Let's wait
kaf24@1452 694 * for a wraparound to start exact measurement:
iap10@4548 695 * (the current tick might have been already half done)
iap10@4548 696 */
iap10@4548 697 wait_timer_tick();
iap10@4548 698
iap10@4548 699 /*
iap10@4548 700 * We wrapped around just now. Let's start:
iap10@4548 701 */
iap10@4548 702 if (cpu_has_tsc)
kaf24@4619 703 rdtscll(t1);
kaf24@1452 704 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 705
iap10@4548 706 /*
iap10@4548 707 * Let's wait LOOPS wraprounds:
iap10@4548 708 */
kaf24@1452 709 for (i = 0; i < LOOPS; i++)
iap10@4548 710 wait_timer_tick();
kaf24@1452 711
kaf24@1452 712 tt2 = apic_read(APIC_TMCCT);
iap10@4548 713 if (cpu_has_tsc)
kaf24@4619 714 rdtscll(t2);
kaf24@1452 715
iap10@4548 716 /*
iap10@4548 717 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 718 * might have overflown, but note that we use signed
kaf24@1452 719 * longs, thus no extra care needed.
kaf24@4619 720 * [underflown to be exact, as the timer counts down ;)]
iap10@4548 721 */
iap10@4548 722
kaf24@1452 723 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 724
iap10@4548 725 if (cpu_has_tsc)
iap10@4548 726 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
iap10@4548 727 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
iap10@4548 728 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 729
iap10@4548 730 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
iap10@4548 731 result/(1000000/HZ),
iap10@4548 732 result%(1000000/HZ));
kaf24@1452 733
kaf24@1452 734 /* set up multipliers for accurate timer code */
kaf24@1452 735 bus_freq = result*HZ;
kaf24@1452 736 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 737 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 738
kaf24@1452 739 printk("..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 740 /* reset APIC to zero timeout value */
kaf24@1452 741 __setup_APIC_LVTT(0);
iap10@4548 742
kaf24@1452 743 return result;
kaf24@1452 744 }
kaf24@1452 745
kaf24@1452 746 /*
kaf24@1452 747 * initialise the APIC timers for all CPUs
kaf24@1452 748 * we start with the first and find out processor frequency and bus speed
kaf24@1452 749 */
kaf24@1452 750 void __init setup_APIC_clocks (void)
kaf24@1452 751 {
kaf24@1452 752 printk("Using local APIC timer interrupts.\n");
kaf24@1452 753 using_apic_timer = 1;
kaf24@1452 754 __cli();
kaf24@1452 755 /* calibrate CPU0 for CPU speed and BUS speed */
kaf24@1452 756 bus_freq = calibrate_APIC_clock();
kaf24@1452 757 /* Now set up the timer for real. */
kaf24@1452 758 setup_APIC_timer((void *)bus_freq);
kaf24@1452 759 __sti();
kaf24@1452 760 /* and update all other cpus */
kaf24@1452 761 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
kaf24@1452 762 }
kaf24@1452 763
kaf24@1452 764 #undef APIC_DIVISOR
kaf24@1452 765
kaf24@1452 766 /*
kaf24@1452 767 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 768 * returns 1 on success
kaf24@1452 769 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 770 */
kaf24@1452 771 int reprogram_ac_timer(s_time_t timeout)
kaf24@1452 772 {
kaf24@1452 773 s_time_t now;
kaf24@1452 774 s_time_t expire;
kaf24@1452 775 u64 apic_tmict;
kaf24@1452 776
kaf24@1452 777 /*
kaf24@1452 778 * We use this value because we don't trust zero (we think it may just
kaf24@1452 779 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 780 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 781 */
kaf24@1452 782 if ( timeout == 0 )
kaf24@1452 783 {
kaf24@1452 784 apic_tmict = 0xffffffff;
kaf24@1452 785 goto reprogram;
kaf24@1452 786 }
kaf24@1452 787
kaf24@1452 788 now = NOW();
kaf24@1452 789 expire = timeout - now; /* value from now */
kaf24@1452 790
kaf24@1452 791 if ( expire <= 0 )
kaf24@1452 792 {
kaf24@1452 793 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 794 smp_processor_id(), (u32)(now>>32),
kaf24@1452 795 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 796 return 0;
kaf24@1452 797 }
kaf24@1452 798
kaf24@1452 799 /*
kaf24@1452 800 * If we don't have local APIC then we just poll the timer list off the
kaf24@1452 801 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
kaf24@1452 802 */
kaf24@1452 803 if ( !cpu_has_apic )
kaf24@1452 804 return 1;
kaf24@1452 805
kaf24@1452 806 /* conversion to bus units */
kaf24@1452 807 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 808
kaf24@1452 809 if ( apic_tmict >= 0xffffffff )
kaf24@1452 810 {
kaf24@1452 811 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 812 apic_tmict = 0xffffffff;
kaf24@1452 813 }
kaf24@1452 814
kaf24@1452 815 if ( apic_tmict == 0 )
kaf24@1452 816 {
kaf24@1452 817 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 818 return 0;
kaf24@1452 819 }
kaf24@1452 820
kaf24@1452 821 reprogram:
kaf24@1452 822 /* Program the timer. */
kaf24@1452 823 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 824
kaf24@1452 825 return 1;
kaf24@1452 826 }
kaf24@1452 827
ach61@2805 828 void smp_apic_timer_interrupt(struct xen_regs * regs)
kaf24@1452 829 {
kaf24@1452 830 ack_APIC_irq();
kaf24@1452 831 perfc_incrc(apic_timer);
kaf24@1506 832 raise_softirq(AC_TIMER_SOFTIRQ);
kaf24@1452 833 }
kaf24@1452 834
kaf24@1452 835 /*
kaf24@1452 836 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 837 */
iap10@4548 838 asmlinkage void smp_spurious_interrupt(struct xen_regs *regs)
kaf24@1452 839 {
kaf24@1452 840 unsigned long v;
kaf24@1452 841
kaf24@1452 842 /*
kaf24@1452 843 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 844 * if it is a vectored one. Just in case...
kaf24@1452 845 * Spurious interrupts should not be ACKed.
kaf24@1452 846 */
kaf24@1452 847 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 848 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 849 ack_APIC_irq();
kaf24@1452 850
kaf24@1452 851 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@1452 852 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 853 smp_processor_id());
kaf24@1452 854 }
kaf24@1452 855
kaf24@1452 856 /*
kaf24@1452 857 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 858 */
kaf24@1452 859
iap10@4548 860 asmlinkage void smp_error_interrupt(struct xen_regs *regs)
kaf24@1452 861 {
kaf24@1452 862 unsigned long v, v1;
kaf24@1452 863
kaf24@1452 864 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 865 v = apic_read(APIC_ESR);
kaf24@1452 866 apic_write(APIC_ESR, 0);
kaf24@1452 867 v1 = apic_read(APIC_ESR);
kaf24@1452 868 ack_APIC_irq();
kaf24@1452 869 atomic_inc(&irq_err_count);
kaf24@1452 870
kaf24@1452 871 /* Here is what the APIC error bits mean:
kaf24@1452 872 0: Send CS error
kaf24@1452 873 1: Receive CS error
kaf24@1452 874 2: Send accept error
kaf24@1452 875 3: Receive accept error
kaf24@1452 876 4: Reserved
kaf24@1452 877 5: Send illegal vector
kaf24@1452 878 6: Received illegal vector
kaf24@1452 879 7: Illegal register address
kaf24@1452 880 */
kaf24@4619 881 printk("APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@4619 882 smp_processor_id(), v, v1);
kaf24@1452 883 }
kaf24@1452 884
kaf24@1452 885 /*
kaf24@1452 886 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 887 * a UP kernel.
kaf24@1452 888 */
kaf24@1452 889 int __init APIC_init_uniprocessor (void)
kaf24@1452 890 {
kaf24@1452 891 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 892 return -1;
kaf24@1452 893
kaf24@1452 894 /*
kaf24@1452 895 * Complain if the BIOS pretends there is one.
kaf24@1452 896 */
iap10@4548 897 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@1452 898 printk("BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 899 boot_cpu_physical_apicid);
kaf24@1452 900 return -1;
kaf24@1452 901 }
kaf24@1452 902
kaf24@1452 903 verify_local_APIC();
kaf24@1452 904
kaf24@1452 905 connect_bsp_APIC();
kaf24@1452 906
kaf24@1452 907 #ifdef CONFIG_SMP
kaf24@1452 908 cpu_online_map = 1;
kaf24@1452 909 #endif
kaf24@1452 910 phys_cpu_present_map = 1;
kaf24@1452 911 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
kaf24@1452 912
kaf24@1452 913 setup_local_APIC();
kaf24@1452 914
kaf24@1452 915 #ifdef CONFIG_X86_IO_APIC
iap10@4548 916 if (smp_found_config)
iap10@4548 917 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 918 setup_IO_APIC();
iap10@4548 919 #endif
kaf24@1452 920 setup_APIC_clocks();
kaf24@1452 921
kaf24@1452 922 return 0;
kaf24@1452 923 }