ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 5211:b2310e7dbfdc

bitkeeper revision 1.1599 (429b828aL4XKwdaPjLGObI37F4hwiw)

By default do not enable local APIC if disabled by the BIOS. This
matches Linux behaviour and ought to improve stability on buggy
hardware/firmware (laptops in particular). As in Linux, you can
forcibly enable the APIC with 'lapic' command-line option, or
forcibly ignore it with 'nolapic'.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon May 30 21:15:54 2005 +0000 (2005-05-30)
parents f1ac5983d4d8
children ca9531e574f4
rev   line source
kaf24@1452 1 /*
kaf24@4888 2 * based on linux-2.6.11/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kaf24@1452 13 * Maciej W. Rozycki : Various updates and fixes.
kaf24@1452 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@4888 41 * Debug level
kaf24@4888 42 */
kaf24@4888 43 int apic_verbosity;
kaf24@4888 44
kaf24@1452 45 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 46 int using_apic_timer = 0;
kaf24@1452 47
kaf24@1452 48 static int enabled_via_apicbase;
kaf24@1452 49
kaf24@4804 50 int get_physical_broadcast(void)
kaf24@4804 51 {
kaf24@4804 52 unsigned int lvr, version;
kaf24@4804 53 lvr = apic_read(APIC_LVR);
kaf24@4804 54 version = GET_APIC_VERSION(lvr);
kaf24@4804 55 if (!APIC_INTEGRATED(version) || version >= 0x14)
kaf24@4804 56 return 0xff;
kaf24@4804 57 else
kaf24@4804 58 return 0xf;
kaf24@4804 59 }
kaf24@4804 60
kaf24@1452 61 int get_maxlvt(void)
kaf24@1452 62 {
kaf24@1452 63 unsigned int v, ver, maxlvt;
kaf24@1452 64
kaf24@1452 65 v = apic_read(APIC_LVR);
kaf24@1452 66 ver = GET_APIC_VERSION(v);
kaf24@1452 67 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 68 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 69 return maxlvt;
kaf24@1452 70 }
kaf24@1452 71
kaf24@1452 72 void clear_local_APIC(void)
kaf24@1452 73 {
kaf24@1452 74 int maxlvt;
kaf24@1452 75 unsigned long v;
kaf24@1452 76
kaf24@1452 77 maxlvt = get_maxlvt();
kaf24@1452 78
kaf24@1452 79 /*
kaf24@1452 80 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 81 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 82 */
kaf24@1452 83 if (maxlvt >= 3) {
kaf24@1452 84 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 85 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 86 }
kaf24@1452 87 /*
kaf24@1452 88 * Careful: we have to set masks only first to deassert
kaf24@1452 89 * any level-triggered sources.
kaf24@1452 90 */
kaf24@1452 91 v = apic_read(APIC_LVTT);
kaf24@1452 92 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 93 v = apic_read(APIC_LVT0);
kaf24@1452 94 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 95 v = apic_read(APIC_LVT1);
kaf24@1452 96 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 97 if (maxlvt >= 4) {
kaf24@1452 98 v = apic_read(APIC_LVTPC);
kaf24@1452 99 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 100 }
kaf24@1452 101
kaf24@5211 102 /* lets not touch this if we didn't frob it */
kaf24@5211 103 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 104 if (maxlvt >= 5) {
kaf24@5211 105 v = apic_read(APIC_LVTTHMR);
kaf24@5211 106 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
kaf24@5211 107 }
kaf24@5211 108 #endif
kaf24@1452 109 /*
kaf24@1452 110 * Clean APIC state for other OSs:
kaf24@1452 111 */
kaf24@1452 112 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 113 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 114 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 115 if (maxlvt >= 3)
kaf24@1452 116 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 117 if (maxlvt >= 4)
kaf24@1452 118 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 119
kaf24@5211 120 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 121 if (maxlvt >= 5)
kaf24@5211 122 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
kaf24@5211 123 #endif
kaf24@1452 124 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@1452 125 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 126 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 127 apic_write(APIC_ESR, 0);
kaf24@1452 128 apic_read(APIC_ESR);
kaf24@1452 129 }
kaf24@1452 130 }
kaf24@1452 131
kaf24@1452 132 void __init connect_bsp_APIC(void)
kaf24@1452 133 {
kaf24@1452 134 if (pic_mode) {
kaf24@1452 135 /*
kaf24@1452 136 * Do not trust the local APIC being empty at bootup.
kaf24@1452 137 */
kaf24@1452 138 clear_local_APIC();
kaf24@1452 139 /*
kaf24@1452 140 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 141 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 142 */
kaf24@4888 143 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 144 "enabling APIC mode.\n");
kaf24@1452 145 outb(0x70, 0x22);
kaf24@1452 146 outb(0x01, 0x23);
kaf24@1452 147 }
kaf24@5211 148 enable_apic_mode();
kaf24@1452 149 }
kaf24@1452 150
kaf24@1452 151 void disconnect_bsp_APIC(void)
kaf24@1452 152 {
kaf24@1452 153 if (pic_mode) {
kaf24@1452 154 /*
kaf24@1452 155 * Put the board back into PIC mode (has an effect
kaf24@1452 156 * only on certain older boards). Note that APIC
kaf24@1452 157 * interrupts, including IPIs, won't work beyond
kaf24@1452 158 * this point! The only exception are INIT IPIs.
kaf24@1452 159 */
kaf24@4888 160 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 161 "entering PIC mode.\n");
kaf24@1452 162 outb(0x70, 0x22);
kaf24@1452 163 outb(0x00, 0x23);
kaf24@1452 164 }
kaf24@1452 165 }
kaf24@1452 166
kaf24@1452 167 void disable_local_APIC(void)
kaf24@1452 168 {
kaf24@1452 169 unsigned long value;
kaf24@1452 170
kaf24@1452 171 clear_local_APIC();
kaf24@1452 172
kaf24@1452 173 /*
kaf24@1452 174 * Disable APIC (implies clearing of registers
kaf24@1452 175 * for 82489DX!).
kaf24@1452 176 */
kaf24@1452 177 value = apic_read(APIC_SPIV);
kaf24@1452 178 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 179 apic_write_around(APIC_SPIV, value);
kaf24@1452 180
kaf24@1452 181 if (enabled_via_apicbase) {
kaf24@1452 182 unsigned int l, h;
kaf24@1452 183 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 184 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 185 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 186 }
kaf24@1452 187 }
kaf24@1452 188
kaf24@1452 189 /*
kaf24@1452 190 * This is to verify that we're looking at a real local APIC.
kaf24@1452 191 * Check these against your board if the CPUs aren't getting
kaf24@1452 192 * started for no apparent reason.
kaf24@1452 193 */
kaf24@1452 194 int __init verify_local_APIC(void)
kaf24@1452 195 {
kaf24@1452 196 unsigned int reg0, reg1;
kaf24@1452 197
kaf24@1452 198 /*
kaf24@1452 199 * The version register is read-only in a real APIC.
kaf24@1452 200 */
kaf24@1452 201 reg0 = apic_read(APIC_LVR);
kaf24@4888 202 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
kaf24@1452 203 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 204 reg1 = apic_read(APIC_LVR);
kaf24@4888 205 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 206
kaf24@1452 207 /*
kaf24@1452 208 * The two version reads above should print the same
kaf24@1452 209 * numbers. If the second one is different, then we
kaf24@1452 210 * poke at a non-APIC.
kaf24@1452 211 */
kaf24@1452 212 if (reg1 != reg0)
kaf24@1452 213 return 0;
kaf24@1452 214
kaf24@1452 215 /*
kaf24@1452 216 * Check if the version looks reasonably.
kaf24@1452 217 */
kaf24@1452 218 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 219 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 220 return 0;
kaf24@1452 221 reg1 = get_maxlvt();
kaf24@1452 222 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 223 return 0;
kaf24@1452 224
kaf24@1452 225 /*
kaf24@1452 226 * The ID register is read/write in a real APIC.
kaf24@1452 227 */
kaf24@1452 228 reg0 = apic_read(APIC_ID);
kaf24@4888 229 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 230
kaf24@1452 231 /*
kaf24@1452 232 * The next two are just to see if we have sane values.
kaf24@1452 233 * They're only really relevant if we're in Virtual Wire
kaf24@1452 234 * compatibility mode, but most boxes are anymore.
kaf24@1452 235 */
kaf24@1452 236 reg0 = apic_read(APIC_LVT0);
kaf24@4888 237 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 238 reg1 = apic_read(APIC_LVT1);
kaf24@4888 239 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 240
kaf24@1452 241 return 1;
kaf24@1452 242 }
kaf24@1452 243
kaf24@1452 244 void __init sync_Arb_IDs(void)
kaf24@1452 245 {
iap10@4548 246 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
iap10@4548 247 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
iap10@4548 248 if (ver >= 0x14) /* P4 or higher */
iap10@4548 249 return;
kaf24@1452 250 /*
kaf24@1452 251 * Wait for idle.
kaf24@1452 252 */
kaf24@1452 253 apic_wait_icr_idle();
kaf24@1452 254
kaf24@4888 255 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 256 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 257 | APIC_DM_INIT);
kaf24@1452 258 }
kaf24@1452 259
kaf24@1452 260 extern void __error_in_apic_c (void);
kaf24@1452 261
kaf24@4888 262 /*
kaf24@4888 263 * An initial setup of the virtual wire mode.
kaf24@4888 264 */
kaf24@1452 265 void __init init_bsp_APIC(void)
kaf24@1452 266 {
kaf24@4620 267 unsigned long value, ver;
kaf24@4620 268
kaf24@4620 269 /*
kaf24@4888 270 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 271 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 272 */
kaf24@4620 273 if (smp_found_config || !cpu_has_apic)
kaf24@4620 274 return;
kaf24@4620 275
kaf24@4620 276 value = apic_read(APIC_LVR);
kaf24@4620 277 ver = GET_APIC_VERSION(value);
kaf24@4620 278
kaf24@4620 279 /*
kaf24@4620 280 * Do not trust the local APIC being empty at bootup.
kaf24@4620 281 */
kaf24@4620 282 clear_local_APIC();
kaf24@4620 283
kaf24@4620 284 /*
kaf24@4620 285 * Enable APIC.
kaf24@4620 286 */
kaf24@4620 287 value = apic_read(APIC_SPIV);
kaf24@4620 288 value &= ~APIC_VECTOR_MASK;
kaf24@4620 289 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 290
kaf24@4620 291 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 292 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 293 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 294 else
kaf24@4620 295 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 296 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 297 apic_write_around(APIC_SPIV, value);
kaf24@4620 298
kaf24@4620 299 /*
kaf24@4620 300 * Set up the virtual wire mode.
kaf24@4620 301 */
kaf24@4620 302 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 303 value = APIC_DM_NMI;
kaf24@4620 304 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 305 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 306 apic_write_around(APIC_LVT1, value);
kaf24@1452 307 }
kaf24@1452 308
kaf24@1452 309 void __init setup_local_APIC (void)
kaf24@1452 310 {
iap10@4548 311 unsigned long oldvalue, value, ver, maxlvt;
iap10@4548 312
iap10@4548 313 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 314 if (esr_disable) {
iap10@4548 315 apic_write(APIC_ESR, 0);
iap10@4548 316 apic_write(APIC_ESR, 0);
iap10@4548 317 apic_write(APIC_ESR, 0);
iap10@4548 318 apic_write(APIC_ESR, 0);
iap10@4548 319 }
kaf24@1452 320
kaf24@1452 321 value = apic_read(APIC_LVR);
kaf24@1452 322 ver = GET_APIC_VERSION(value);
kaf24@1452 323
kaf24@1452 324 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 325 __error_in_apic_c();
kaf24@1452 326
iap10@4548 327 /*
iap10@4548 328 * Double-check whether this APIC is really registered.
iap10@4548 329 */
iap10@4548 330 if (!apic_id_registered())
kaf24@1452 331 BUG();
kaf24@1452 332
kaf24@1452 333 /*
kaf24@1452 334 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 335 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 336 * document number 292116). So here it goes...
kaf24@1452 337 */
iap10@4548 338 init_apic_ldr();
kaf24@1452 339
kaf24@1452 340 /*
kaf24@1452 341 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 342 * later on.
kaf24@1452 343 */
kaf24@1452 344 value = apic_read(APIC_TASKPRI);
kaf24@1452 345 value &= ~APIC_TPRI_MASK;
kaf24@1452 346 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 347
kaf24@1452 348 /*
kaf24@1452 349 * Now that we are all set up, enable the APIC
kaf24@1452 350 */
kaf24@1452 351 value = apic_read(APIC_SPIV);
kaf24@1452 352 value &= ~APIC_VECTOR_MASK;
kaf24@1452 353 /*
kaf24@1452 354 * Enable APIC
kaf24@1452 355 */
kaf24@1452 356 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 357
iap10@4548 358 /*
iap10@4548 359 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 360 * certain networking cards. If high frequency interrupts are
iap10@4548 361 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 362 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 363 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 364 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 365 * away, oh well :-(
iap10@4548 366 *
iap10@4548 367 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 368 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 369 * BX chipset. ]
iap10@4548 370 */
iap10@4548 371 /*
iap10@4548 372 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 373 * frequent as it makes the interrupt distributon model be more
iap10@4548 374 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 375 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 376 */
iap10@4548 377 #if 1
kaf24@1452 378 /* Enable focus processor (bit==0) */
kaf24@1452 379 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 380 #else
iap10@4548 381 /* Disable focus processor (bit==1) */
iap10@4548 382 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 383 #endif
iap10@4548 384 /*
iap10@4548 385 * Set spurious IRQ vector
iap10@4548 386 */
kaf24@1452 387 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 388 apic_write_around(APIC_SPIV, value);
kaf24@1452 389
kaf24@1452 390 /*
kaf24@1452 391 * Set up LVT0, LVT1:
kaf24@1452 392 *
kaf24@1452 393 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 394 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 395 * we delegate interrupts to the 8259A.
kaf24@1452 396 */
kaf24@1452 397 /*
kaf24@1452 398 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 399 */
kaf24@1452 400 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 401 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 402 value = APIC_DM_EXTINT;
kaf24@4888 403 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 404 smp_processor_id());
kaf24@1452 405 } else {
kaf24@1452 406 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 407 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 408 smp_processor_id());
kaf24@1452 409 }
kaf24@1452 410 apic_write_around(APIC_LVT0, value);
kaf24@1452 411
kaf24@1452 412 /*
kaf24@1452 413 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 414 */
kaf24@1452 415 if (!smp_processor_id())
kaf24@1452 416 value = APIC_DM_NMI;
kaf24@1452 417 else
kaf24@1452 418 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 419 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 420 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 421 apic_write_around(APIC_LVT1, value);
kaf24@1452 422
iap10@4548 423 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 424 maxlvt = get_maxlvt();
kaf24@1452 425 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 426 apic_write(APIC_ESR, 0);
iap10@4548 427 oldvalue = apic_read(APIC_ESR);
kaf24@1452 428
iap10@4548 429 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 430 apic_write_around(APIC_LVTERR, value);
iap10@4548 431 /*
iap10@4548 432 * spec says clear errors after enabling vector.
iap10@4548 433 */
kaf24@1452 434 if (maxlvt > 3)
kaf24@1452 435 apic_write(APIC_ESR, 0);
kaf24@1452 436 value = apic_read(APIC_ESR);
iap10@4548 437 if (value != oldvalue)
kaf24@4888 438 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 439 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 440 oldvalue, value);
kaf24@1452 441 } else {
iap10@4548 442 if (esr_disable)
iap10@4548 443 /*
iap10@4548 444 * Something untraceble is creating bad interrupts on
iap10@4548 445 * secondary quads ... for the moment, just leave the
iap10@4548 446 * ESR disabled - we can't do anything useful with the
iap10@4548 447 * errors anyway - mbligh
iap10@4548 448 */
iap10@4548 449 printk("Leaving ESR disabled.\n");
kaf24@4888 450 else
kaf24@4888 451 printk("No ESR for 82489DX.\n");
kaf24@1452 452 }
kaf24@1452 453
iap10@4548 454 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@1452 455 setup_apic_nmi_watchdog();
kaf24@1452 456 }
kaf24@1452 457
kaf24@1452 458 /*
kaf24@1452 459 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 460 * Original code written by Keir Fraser.
kaf24@1452 461 */
kaf24@1452 462
kaf24@5211 463 /*
kaf24@5211 464 * Knob to control our willingness to enable the local APIC.
kaf24@5211 465 */
kaf24@5211 466 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
kaf24@5211 467
kaf24@5211 468 static void __init lapic_disable(char *str)
kaf24@5211 469 {
kaf24@5211 470 enable_local_apic = -1;
kaf24@5211 471 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 472 }
kaf24@5211 473 custom_param("nolapic", lapic_disable);
kaf24@5211 474
kaf24@5211 475 static void __init lapic_enable(char *str)
kaf24@5211 476 {
kaf24@5211 477 enable_local_apic = 1;
kaf24@5211 478 }
kaf24@5211 479 custom_param("lapic", lapic_enable);
kaf24@5211 480
kaf24@4888 481 static void __init apic_set_verbosity(char *str)
kaf24@4888 482 {
kaf24@4888 483 if (strcmp("debug", str) == 0)
kaf24@4888 484 apic_verbosity = APIC_DEBUG;
kaf24@4888 485 else if (strcmp("verbose", str) == 0)
kaf24@4888 486 apic_verbosity = APIC_VERBOSE;
kaf24@5211 487 else
kaf24@5211 488 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@5211 489 " use apic_verbosity=verbose or apic_verbosity=debug", str);
kaf24@4888 490 }
kaf24@5211 491 custom_param("apic_verbosity", apic_set_verbosity);
kaf24@4888 492
kaf24@1452 493 static int __init detect_init_APIC (void)
kaf24@1452 494 {
kaf24@1452 495 u32 h, l, features;
kaf24@1452 496 extern void get_cpu_vendor(struct cpuinfo_x86*);
kaf24@1452 497
kaf24@5211 498 /* Disabled by kernel option? */
kaf24@5211 499 if (enable_local_apic < 0)
kaf24@5211 500 return -1;
kaf24@5211 501
kaf24@1452 502 /* Workaround for us being called before identify_cpu(). */
kaf24@1452 503 get_cpu_vendor(&boot_cpu_data);
kaf24@1452 504
kaf24@1452 505 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 506 case X86_VENDOR_AMD:
iap10@4548 507 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 508 (boot_cpu_data.x86 == 15))
kaf24@1452 509 break;
kaf24@1452 510 goto no_apic;
kaf24@1452 511 case X86_VENDOR_INTEL:
iap10@4548 512 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 513 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 514 break;
kaf24@1452 515 goto no_apic;
kaf24@1452 516 default:
kaf24@1452 517 goto no_apic;
kaf24@1452 518 }
kaf24@1452 519
kaf24@1452 520 if (!cpu_has_apic) {
kaf24@1452 521 /*
kaf24@5211 522 * Over-ride BIOS and try to enable the local
kaf24@5211 523 * APIC only if "lapic" specified.
kaf24@5211 524 */
kaf24@5211 525 if (enable_local_apic <= 0) {
kaf24@5211 526 printk("Local APIC disabled by BIOS -- "
kaf24@5211 527 "you can enable it with \"lapic\"\n");
kaf24@5211 528 return -1;
kaf24@5211 529 }
kaf24@5211 530 /*
kaf24@1452 531 * Some BIOSes disable the local APIC in the
kaf24@1452 532 * APIC_BASE MSR. This can only be done in
iap10@4548 533 * software for Intel P6 or later and AMD K7
iap10@4548 534 * (Model > 1) or later.
kaf24@1452 535 */
kaf24@1452 536 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 537 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 538 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 539 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 540 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 541 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 542 enabled_via_apicbase = 1;
kaf24@1452 543 }
kaf24@1452 544 }
kaf24@4888 545 /*
kaf24@4888 546 * The APIC feature bit should now be enabled
kaf24@4888 547 * in `cpuid'
kaf24@4888 548 */
kaf24@1452 549 features = cpuid_edx(1);
kaf24@1452 550 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 551 printk("Could not enable APIC!\n");
kaf24@1452 552 return -1;
kaf24@1452 553 }
kaf24@4619 554
iap10@4548 555 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 556 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 557
kaf24@1452 558 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 559 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 560 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 561 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 562
kaf24@4619 563 if (nmi_watchdog != NMI_NONE)
kaf24@4619 564 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 565
kaf24@1452 566 printk("Found and enabled local APIC!\n");
iap10@4548 567
kaf24@1452 568 return 0;
kaf24@1452 569
iap10@4548 570 no_apic:
kaf24@1452 571 printk("No local APIC present or hardware disabled\n");
kaf24@1452 572 return -1;
kaf24@1452 573 }
kaf24@1452 574
kaf24@1452 575 void __init init_apic_mappings(void)
kaf24@1452 576 {
iap10@4548 577 unsigned long apic_phys;
kaf24@1452 578
kaf24@1452 579 /*
iap10@4548 580 * If no local APIC can be found then set up a fake all
iap10@4548 581 * zeroes page to simulate the local APIC and another
iap10@4548 582 * one for the IO-APIC.
kaf24@1452 583 */
kaf24@1452 584 if (!smp_found_config && detect_init_APIC()) {
kaf24@1920 585 apic_phys = alloc_xenheap_page();
kaf24@1452 586 apic_phys = __pa(apic_phys);
kaf24@1452 587 } else
kaf24@1452 588 apic_phys = mp_lapic_addr;
kaf24@1452 589
kaf24@1452 590 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 591 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 592 apic_phys);
kaf24@1452 593
kaf24@1452 594 /*
kaf24@1452 595 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 596 * default configuration (or the MP table is broken).
kaf24@1452 597 */
kaf24@1452 598 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 599 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 600
kaf24@1452 601 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 602 {
iap10@4548 603 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 604 int i;
kaf24@1452 605
kaf24@1452 606 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 607 if (smp_found_config) {
kaf24@1452 608 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 609 if (!ioapic_phys) {
iap10@4548 610 printk(KERN_ERR
iap10@4548 611 "WARNING: bogus zero IO-APIC "
iap10@4548 612 "address found in MPTABLE, "
iap10@4548 613 "disabling IO/APIC support!\n");
iap10@4548 614 smp_found_config = 0;
iap10@4548 615 skip_ioapic_setup = 1;
iap10@4548 616 goto fake_ioapic_page;
iap10@4548 617 }
iap10@4548 618 } else {
iap10@4548 619 fake_ioapic_page:
iap10@4548 620 ioapic_phys = alloc_xenheap_page();
iap10@4548 621 ioapic_phys = __pa(ioapic_phys);
iap10@4548 622 }
kaf24@1452 623 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 624 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 625 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 626 idx++;
kaf24@1452 627 }
kaf24@1452 628 }
kaf24@1452 629 #endif
kaf24@1452 630 }
kaf24@1452 631
kaf24@1452 632 /*****************************************************************************
kaf24@1452 633 * APIC calibration
kaf24@1452 634 *
kaf24@1452 635 * The APIC is programmed in bus cycles.
kaf24@1452 636 * Timeout values should specified in real time units.
kaf24@1452 637 * The "cheapest" time source is the cyclecounter.
kaf24@1452 638 *
kaf24@1452 639 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 640 *
kaf24@1452 641 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 642 * timer chip to generate periodic timer interupts.
kaf24@1452 643 *****************************************************************************/
kaf24@1452 644
kaf24@1452 645 /* used for system time scaling */
kaf24@1672 646 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 647 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 648 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 649
kaf24@1452 650 /*
kaf24@1452 651 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 652 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 653 * to calibrate.
kaf24@1452 654 */
kaf24@1452 655 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 656 {
kaf24@1452 657 /*extern spinlock_t i8253_lock;*/
kaf24@1452 658 /*unsigned long flags;*/
iap10@4548 659
kaf24@1452 660 unsigned int count;
iap10@4548 661
kaf24@1452 662 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 663
iap10@4548 664 outb_p(0x00, PIT_MODE);
iap10@4548 665 count = inb_p(PIT_CH0);
iap10@4548 666 count |= inb_p(PIT_CH0) << 8;
iap10@4548 667
kaf24@1452 668 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 669
kaf24@1452 670 return count;
kaf24@1452 671 }
kaf24@1452 672
iap10@4548 673 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 674 static void __init wait_8254_wraparound(void)
kaf24@1452 675 {
kaf24@4888 676 unsigned int curr_count, prev_count;
kaf24@4888 677
kaf24@1452 678 curr_count = get_8254_timer_count();
kaf24@1452 679 do {
kaf24@1452 680 prev_count = curr_count;
kaf24@1452 681 curr_count = get_8254_timer_count();
iap10@4548 682
kaf24@4888 683 /* workaround for broken Mercury/Neptune */
kaf24@4888 684 if (prev_count >= curr_count + 0x100)
kaf24@4888 685 curr_count = get_8254_timer_count();
kaf24@4888 686
kaf24@4888 687 } while (prev_count >= curr_count);
kaf24@1452 688 }
kaf24@1452 689
kaf24@1452 690 /*
iap10@4548 691 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 692 * we override this later
iap10@4548 693 */
kaf24@4888 694 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 695
iap10@4548 696 /*
kaf24@1452 697 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 698 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 699 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 700 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 701 * call this function only once, with the real, calibrated value.
kaf24@1452 702 *
kaf24@1452 703 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 704 * P5 APIC double write bug.
kaf24@1452 705 */
iap10@4548 706
kaf24@1452 707 #define APIC_DIVISOR 1
iap10@4548 708
kaf24@5146 709 void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 710 {
iap10@4548 711 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 712
iap10@4548 713 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 714 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 715 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 716 if (!APIC_INTEGRATED(ver))
iap10@4548 717 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 718 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 719
kaf24@1452 720 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 721 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 722
kaf24@1452 723 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 724 }
kaf24@1452 725
kaf24@5146 726 static void __init setup_APIC_timer(unsigned int clocks)
kaf24@1452 727 {
kaf24@1452 728 unsigned long flags;
kaf24@5146 729
kaf24@5146 730 local_irq_save(flags);
kaf24@5146 731
kaf24@5146 732 /*
kaf24@5146 733 * Wait for IRQ0's slice:
kaf24@5146 734 */
kaf24@5146 735 wait_timer_tick();
kaf24@5146 736
kaf24@5146 737 __setup_APIC_LVTT(clocks);
kaf24@5146 738
kaf24@5146 739 local_irq_restore(flags);
kaf24@1452 740 }
kaf24@1452 741
kaf24@1452 742 /*
kaf24@5146 743 * In this function we calibrate APIC bus clocks to the external
kaf24@5146 744 * timer. Unfortunately we cannot use jiffies and the timer irq
kaf24@5146 745 * to calibrate, since some later bootup code depends on getting
kaf24@5146 746 * the first irq? Ugh.
kaf24@1452 747 *
kaf24@5146 748 * We want to do the calibration only once since we
kaf24@5146 749 * want to have local timer irqs syncron. CPUs connected
kaf24@5146 750 * by the same APIC bus have the very same bus frequency.
kaf24@5146 751 * And we want to have irqs off anyways, no accidental
kaf24@5146 752 * APIC irq that way.
kaf24@1452 753 */
kaf24@1452 754
kaf24@1452 755 int __init calibrate_APIC_clock(void)
kaf24@1452 756 {
kaf24@1452 757 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 758 long tt1, tt2;
kaf24@1452 759 long result;
kaf24@1452 760 int i;
kaf24@1452 761 const int LOOPS = HZ/10;
kaf24@1452 762
kaf24@4888 763 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 764
iap10@4548 765 /*
iap10@4548 766 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 767 * value into the APIC clock, we just want to get the
iap10@4548 768 * counter running for calibration.
iap10@4548 769 */
kaf24@1452 770 __setup_APIC_LVTT(1000000000);
kaf24@1452 771
iap10@4548 772 /*
iap10@4548 773 * The timer chip counts down to zero. Let's wait
kaf24@1452 774 * for a wraparound to start exact measurement:
iap10@4548 775 * (the current tick might have been already half done)
iap10@4548 776 */
iap10@4548 777 wait_timer_tick();
iap10@4548 778
iap10@4548 779 /*
iap10@4548 780 * We wrapped around just now. Let's start:
iap10@4548 781 */
iap10@4548 782 if (cpu_has_tsc)
kaf24@4619 783 rdtscll(t1);
kaf24@1452 784 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 785
iap10@4548 786 /*
iap10@4548 787 * Let's wait LOOPS wraprounds:
iap10@4548 788 */
kaf24@1452 789 for (i = 0; i < LOOPS; i++)
iap10@4548 790 wait_timer_tick();
kaf24@1452 791
kaf24@1452 792 tt2 = apic_read(APIC_TMCCT);
iap10@4548 793 if (cpu_has_tsc)
kaf24@4619 794 rdtscll(t2);
kaf24@1452 795
iap10@4548 796 /*
iap10@4548 797 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 798 * might have overflown, but note that we use signed
kaf24@1452 799 * longs, thus no extra care needed.
kaf24@4888 800 *
kaf24@4888 801 * underflown to be exact, as the timer counts down ;)
iap10@4548 802 */
iap10@4548 803
kaf24@1452 804 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 805
iap10@4548 806 if (cpu_has_tsc)
kaf24@4888 807 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 808 "%ld.%04ld MHz.\n",
kaf24@4888 809 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 810 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 811
kaf24@4888 812 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kaf24@4888 813 "%ld.%04ld MHz.\n",
kaf24@4888 814 result/(1000000/HZ),
kaf24@4888 815 result%(1000000/HZ));
kaf24@1452 816
kaf24@1452 817 /* set up multipliers for accurate timer code */
kaf24@1452 818 bus_freq = result*HZ;
kaf24@1452 819 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 820 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 821
kaf24@4888 822 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 823 /* reset APIC to zero timeout value */
kaf24@1452 824 __setup_APIC_LVTT(0);
iap10@4548 825
kaf24@1452 826 return result;
kaf24@1452 827 }
kaf24@1452 828
kaf24@5146 829
kaf24@5146 830 static unsigned int calibration_result;
kaf24@5146 831
kaf24@5146 832 void __init setup_boot_APIC_clock(void)
kaf24@1452 833 {
kaf24@5146 834 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
kaf24@1452 835 using_apic_timer = 1;
kaf24@5146 836
kaf24@5146 837 local_irq_disable();
kaf24@5146 838
kaf24@5146 839 calibration_result = calibrate_APIC_clock();
kaf24@5146 840 /*
kaf24@5146 841 * Now set up the timer for real.
kaf24@5146 842 */
kaf24@5146 843 setup_APIC_timer(calibration_result);
kaf24@5146 844
kaf24@5146 845 local_irq_enable();
kaf24@5146 846 }
kaf24@5146 847
kaf24@5146 848 void __init setup_secondary_APIC_clock(void)
kaf24@5146 849 {
kaf24@5146 850 setup_APIC_timer(calibration_result);
kaf24@5146 851 }
kaf24@5146 852
kaf24@5146 853 void __init disable_APIC_timer(void)
kaf24@5146 854 {
kaf24@5146 855 if (using_apic_timer) {
kaf24@5146 856 unsigned long v;
kaf24@5146 857
kaf24@5146 858 v = apic_read(APIC_LVTT);
kaf24@5146 859 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@5146 860 }
kaf24@5146 861 }
kaf24@5146 862
kaf24@5146 863 void enable_APIC_timer(void)
kaf24@5146 864 {
kaf24@5146 865 if (using_apic_timer) {
kaf24@5146 866 unsigned long v;
kaf24@5146 867
kaf24@5146 868 v = apic_read(APIC_LVTT);
kaf24@5146 869 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
kaf24@5146 870 }
kaf24@1452 871 }
kaf24@1452 872
kaf24@1452 873 #undef APIC_DIVISOR
kaf24@1452 874
kaf24@1452 875 /*
kaf24@1452 876 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 877 * returns 1 on success
kaf24@1452 878 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 879 */
kaf24@1452 880 int reprogram_ac_timer(s_time_t timeout)
kaf24@1452 881 {
kaf24@1452 882 s_time_t now;
kaf24@1452 883 s_time_t expire;
kaf24@1452 884 u64 apic_tmict;
kaf24@1452 885
kaf24@1452 886 /*
kaf24@1452 887 * We use this value because we don't trust zero (we think it may just
kaf24@1452 888 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 889 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 890 */
kaf24@1452 891 if ( timeout == 0 )
kaf24@1452 892 {
kaf24@1452 893 apic_tmict = 0xffffffff;
kaf24@1452 894 goto reprogram;
kaf24@1452 895 }
kaf24@1452 896
kaf24@1452 897 now = NOW();
kaf24@1452 898 expire = timeout - now; /* value from now */
kaf24@1452 899
kaf24@1452 900 if ( expire <= 0 )
kaf24@1452 901 {
kaf24@1452 902 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 903 smp_processor_id(), (u32)(now>>32),
kaf24@1452 904 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 905 return 0;
kaf24@1452 906 }
kaf24@1452 907
kaf24@1452 908 /*
kaf24@1452 909 * If we don't have local APIC then we just poll the timer list off the
kaf24@1452 910 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
kaf24@1452 911 */
kaf24@1452 912 if ( !cpu_has_apic )
kaf24@1452 913 return 1;
kaf24@1452 914
kaf24@1452 915 /* conversion to bus units */
kaf24@1452 916 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 917
kaf24@1452 918 if ( apic_tmict >= 0xffffffff )
kaf24@1452 919 {
kaf24@1452 920 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 921 apic_tmict = 0xffffffff;
kaf24@1452 922 }
kaf24@1452 923
kaf24@1452 924 if ( apic_tmict == 0 )
kaf24@1452 925 {
kaf24@1452 926 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 927 return 0;
kaf24@1452 928 }
kaf24@1452 929
kaf24@1452 930 reprogram:
kaf24@1452 931 /* Program the timer. */
kaf24@1452 932 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 933
kaf24@1452 934 return 1;
kaf24@1452 935 }
kaf24@1452 936
kaf24@4683 937 void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 938 {
kaf24@1452 939 ack_APIC_irq();
kaf24@1452 940 perfc_incrc(apic_timer);
kaf24@1506 941 raise_softirq(AC_TIMER_SOFTIRQ);
kaf24@1452 942 }
kaf24@1452 943
kaf24@1452 944 /*
kaf24@1452 945 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 946 */
kaf24@4683 947 asmlinkage void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 948 {
kaf24@1452 949 unsigned long v;
kaf24@1452 950
kaf24@1452 951 /*
kaf24@1452 952 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 953 * if it is a vectored one. Just in case...
kaf24@1452 954 * Spurious interrupts should not be ACKed.
kaf24@1452 955 */
kaf24@1452 956 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 957 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 958 ack_APIC_irq();
kaf24@1452 959
kaf24@1452 960 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@5146 961 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 962 smp_processor_id());
kaf24@1452 963 }
kaf24@1452 964
kaf24@1452 965 /*
kaf24@1452 966 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 967 */
kaf24@1452 968
kaf24@4683 969 asmlinkage void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 970 {
kaf24@1452 971 unsigned long v, v1;
kaf24@1452 972
kaf24@1452 973 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 974 v = apic_read(APIC_ESR);
kaf24@1452 975 apic_write(APIC_ESR, 0);
kaf24@1452 976 v1 = apic_read(APIC_ESR);
kaf24@1452 977 ack_APIC_irq();
kaf24@1452 978 atomic_inc(&irq_err_count);
kaf24@1452 979
kaf24@1452 980 /* Here is what the APIC error bits mean:
kaf24@1452 981 0: Send CS error
kaf24@1452 982 1: Receive CS error
kaf24@1452 983 2: Send accept error
kaf24@1452 984 3: Receive accept error
kaf24@1452 985 4: Reserved
kaf24@1452 986 5: Send illegal vector
kaf24@1452 987 6: Received illegal vector
kaf24@1452 988 7: Illegal register address
kaf24@1452 989 */
kaf24@5146 990 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@5146 991 smp_processor_id(), v , v1);
kaf24@1452 992 }
kaf24@1452 993
kaf24@1452 994 /*
kaf24@1452 995 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 996 * a UP kernel.
kaf24@1452 997 */
kaf24@1452 998 int __init APIC_init_uniprocessor (void)
kaf24@1452 999 {
kaf24@5211 1000 if (enable_local_apic < 0)
kaf24@5211 1001 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 1002
kaf24@1452 1003 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 1004 return -1;
kaf24@1452 1005
kaf24@1452 1006 /*
kaf24@1452 1007 * Complain if the BIOS pretends there is one.
kaf24@1452 1008 */
iap10@4548 1009 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 1010 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 1011 boot_cpu_physical_apicid);
kaf24@1452 1012 return -1;
kaf24@1452 1013 }
kaf24@1452 1014
kaf24@1452 1015 verify_local_APIC();
kaf24@1452 1016
kaf24@1452 1017 connect_bsp_APIC();
kaf24@1452 1018
kaf24@4804 1019 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 1020
kaf24@1452 1021 setup_local_APIC();
kaf24@1452 1022
kaf24@5146 1023 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@5146 1024 check_nmi_watchdog();
kaf24@1452 1025 #ifdef CONFIG_X86_IO_APIC
iap10@4548 1026 if (smp_found_config)
iap10@4548 1027 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 1028 setup_IO_APIC();
iap10@4548 1029 #endif
kaf24@5146 1030 setup_boot_APIC_clock();
kaf24@1452 1031
kaf24@1452 1032 return 0;
kaf24@1452 1033 }