ia64/xen-unstable

annotate xen/include/asm-ia64/xenkregs.h @ 16785:af3550f53874

[IA64] domheap: Don't pin xenheap down. Now it's unnecessary.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents 6f7e6608cb74
children
rev   line source
djm@6457 1 #ifndef _ASM_IA64_XENKREGS_H
djm@6457 2 #define _ASM_IA64_XENKREGS_H
djm@6457 3
djm@6457 4 /*
djm@6457 5 * Translation registers:
djm@6457 6 */
alex@16785 7 #define IA64_TR_MAPPED_REGS 3 /* dtr3: vcpu mapped regs */
alex@16773 8 #define IA64_TR_SHARED_INFO 4 /* dtr4: page shared with domain */
alex@16785 9 #define IA64_TR_VHPT 5 /* dtr5: vhpt */
alex@16773 10
alex@16781 11 #define IA64_TR_VPD 2 /* itr2: vpd */
alex@16781 12
alex@16217 13 #define IA64_DTR_GUEST_KERNEL 7
awilliam@9011 14 #define IA64_ITR_GUEST_KERNEL 2
djm@6457 15 /* Processor status register bits: */
djm@6457 16 #define IA64_PSR_VM_BIT 46
djm@6457 17 #define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
djm@6457 18
awilliam@13840 19 #define IA64_DEFAULT_DCR_BITS (IA64_DCR_PP | IA64_DCR_LC | IA64_DCR_DM | \
awilliam@13840 20 IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
awilliam@13840 21 IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
awilliam@13840 22
alex@15903 23 // note IA64_PSR_PK removed from following, why is this necessary?
alex@15903 24 #define DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
alex@15903 25 IA64_PSR_DT | IA64_PSR_RT | \
alex@15903 26 IA64_PSR_IT | IA64_PSR_BN)
alex@15903 27
alex@15903 28 #define DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL| IA64_PSR_DFH| \
alex@15903 29 IA64_PSR_SP | IA64_PSR_DI | IA64_PSR_SI | \
alex@15903 30 IA64_PSR_DB | IA64_PSR_LP | IA64_PSR_TB | \
alex@15903 31 IA64_PSR_CPL| IA64_PSR_MC | IA64_PSR_IS | \
alex@15903 32 IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
alex@15903 33 IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
alex@15903 34
alex@15903 35 // NO PSR_CLR IS DIFFERENT! (CPL)
alex@15903 36 #define IA64_PSR_CPL1 (__IA64_UL(1) << IA64_PSR_CPL1_BIT)
alex@15903 37 #define IA64_PSR_CPL0 (__IA64_UL(1) << IA64_PSR_CPL0_BIT)
alex@15903 38
djm@6457 39 /* Interruption Function State */
djm@6457 40 #define IA64_IFS_V_BIT 63
djm@6457 41 #define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
djm@6457 42
alex@15418 43 /* Interruption Status Register. */
alex@15418 44 #define IA64_ISR_NI_BIT 39 /* Nested interrupt. */
alex@15418 45
djm@6457 46 /* Page Table Address */
djm@6457 47 #define IA64_PTA_VE_BIT 0
djm@6457 48 #define IA64_PTA_SIZE_BIT 2
alex@15694 49 #define IA64_PTA_SIZE_LEN 6
djm@6457 50 #define IA64_PTA_VF_BIT 8
djm@6457 51 #define IA64_PTA_BASE_BIT 15
djm@6457 52
djm@6457 53 #define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
alex@15694 54 #define IA64_PTA_SIZE (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) << \
alex@15694 55 IA64_PTA_SIZE_BIT)
djm@6457 56 #define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
djm@6457 57 #define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
djm@6457 58
alex@15474 59 /* Some cr.itir declarations. */
alex@15474 60 #define IA64_ITIR_PS 2
alex@15474 61 #define IA64_ITIR_PS_LEN 6
alex@15661 62 #define IA64_ITIR_PS_MASK (((__IA64_UL(1) << IA64_ITIR_PS_LEN) - 1) \
alex@15661 63 << IA64_ITIR_PS)
alex@15474 64 #define IA64_ITIR_KEY 8
alex@15474 65 #define IA64_ITIR_KEY_LEN 24
alex@15474 66 #define IA64_ITIR_KEY_MASK (((__IA64_UL(1) << IA64_ITIR_KEY_LEN) - 1) \
alex@15474 67 << IA64_ITIR_KEY)
alex@15661 68 #define IA64_ITIR_PS_KEY(_ps, _key) (((_ps) << IA64_ITIR_PS) | \
alex@15661 69 (((_key) << IA64_ITIR_KEY)))
alex@15661 70
alex@15694 71 /* Region Register Bits */
alex@15694 72 #define IA64_RR_PS 2
alex@15694 73 #define IA64_RR_PS_LEN 6
alex@15694 74 #define IA64_RR_RID 8
alex@15694 75 #define IA64_RR_RID_LEN 24
alex@15694 76 #define IA64_RR_RID_MASK (((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
alex@15694 77 IA64_RR_RID
alex@15694 78
alex@15661 79 /* Define Protection Key Register (PKR) */
alex@15661 80 #define IA64_PKR_V 0
alex@15661 81 #define IA64_PKR_WD 1
alex@15661 82 #define IA64_PKR_RD 2
alex@15661 83 #define IA64_PKR_XD 3
alex@15661 84 #define IA64_PKR_MBZ0 4
alex@15661 85 #define IA64_PKR_KEY 8
alex@15661 86 #define IA64_PKR_KEY_LEN 24
alex@15661 87 #define IA64_PKR_MBZ1 32
alex@15661 88
alex@15661 89 #define IA64_PKR_VALID (1 << IA64_PKR_V)
alex@15661 90 #define IA64_PKR_KEY_MASK (((__IA64_UL(1) << IA64_PKR_KEY_LEN) - 1) \
alex@15661 91 << IA64_PKR_KEY)
alex@15661 92
alex@15661 93 #define XEN_IA64_NPKRS 15 /* Number of pkr's in PV */
alex@15474 94
alex@15664 95 /* A pkr val for the hypervisor: key = 0, valid = 1. */
alex@15664 96 #define XEN_IA64_PKR_VAL ((0 << IA64_PKR_KEY) | IA64_PKR_VALID)
alex@15664 97
djm@6457 98 #endif /* _ASM_IA64_XENKREGS_H */