ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 17552:9fd00ff95068

x86: Support x2APIC mode.
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu May 01 11:34:56 2008 +0100 (2008-05-01)
parents 6ea3db7ae24d
children 4d5203f95498
rev   line source
kaf24@1452 1 /*
kfraser@11541 2 * based on linux-2.6.17.13/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kfraser@11204 13 * Maciej W. Rozycki : Various updates and fixes.
kfraser@11204 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@8847 41 * Knob to control our willingness to enable the local APIC.
kaf24@8847 42 */
kaf24@8847 43 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
kaf24@8847 44
kaf24@8847 45 /*
kaf24@4888 46 * Debug level
kaf24@4888 47 */
kaf24@4888 48 int apic_verbosity;
kaf24@4888 49
keir@17552 50 int x2apic_enabled __read_mostly = 0;
keir@17552 51
kaf24@8847 52
kaf24@8847 53 static void apic_pm_activate(void);
kaf24@8847 54
kfraser@11541 55 int modern_apic(void)
kfraser@11541 56 {
kfraser@11541 57 unsigned int lvr, version;
kfraser@11541 58 /* AMD systems use old APIC versions, so check the CPU */
kfraser@11541 59 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
kfraser@11541 60 boot_cpu_data.x86 >= 0xf)
kfraser@11541 61 return 1;
kfraser@11541 62 lvr = apic_read(APIC_LVR);
kfraser@11541 63 version = GET_APIC_VERSION(lvr);
kfraser@11541 64 return version >= 0x14;
kfraser@11541 65 }
kfraser@11541 66
kaf24@8847 67 /*
kaf24@8847 68 * 'what should we do if we get a hw irq event on an illegal vector'.
kaf24@8847 69 * each architecture has to answer this themselves.
kaf24@8847 70 */
kaf24@8847 71 void ack_bad_irq(unsigned int irq)
kaf24@8847 72 {
kaf24@8847 73 printk("unexpected IRQ trap at vector %02x\n", irq);
kaf24@8847 74 /*
kaf24@8847 75 * Currently unexpected vectors happen only on SMP and APIC.
kaf24@8847 76 * We _must_ ack these because every local APIC has only N
kaf24@8847 77 * irq slots per priority level, and a 'hanging, unacked' IRQ
kaf24@8847 78 * holds up an irq slot - in excessive cases (when multiple
kaf24@8847 79 * unexpected vectors occur) that might lock up the APIC
kaf24@8847 80 * completely.
kfraser@11541 81 * But only ack when the APIC is enabled -AK
kaf24@8847 82 */
kfraser@11541 83 if (cpu_has_apic)
kfraser@11541 84 ack_APIC_irq();
kaf24@8847 85 }
kaf24@8847 86
kaf24@8847 87 void __init apic_intr_init(void)
kaf24@8847 88 {
kaf24@8847 89 #ifdef CONFIG_SMP
kaf24@8847 90 smp_intr_init();
kaf24@8847 91 #endif
kaf24@8847 92 /* self generated IPI for local APIC timer */
kaf24@8847 93 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
kaf24@8847 94
kaf24@8847 95 /* IPI vectors for APIC spurious and error interrupts */
kaf24@8847 96 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
kaf24@8847 97 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
kaf24@8847 98
keir@16940 99 /* Performance Counters Interrupt */
keir@16940 100 set_intr_gate(PMU_APIC_VECTOR, pmu_apic_interrupt);
keir@16940 101
kaf24@8847 102 /* thermal monitor LVT interrupt */
kaf24@8847 103 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@8847 104 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
kaf24@8847 105 #endif
kaf24@8847 106 }
kaf24@8847 107
kaf24@1452 108 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 109 int using_apic_timer = 0;
kaf24@1452 110
kaf24@1452 111 static int enabled_via_apicbase;
kaf24@1452 112
kfraser@11541 113 void enable_NMI_through_LVT0 (void * dummy)
kfraser@11541 114 {
kfraser@11541 115 unsigned int v, ver;
kfraser@11541 116
kfraser@11541 117 ver = apic_read(APIC_LVR);
kfraser@11541 118 ver = GET_APIC_VERSION(ver);
kfraser@11541 119 v = APIC_DM_NMI; /* unmask and set to NMI */
kfraser@11541 120 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kfraser@11541 121 v |= APIC_LVT_LEVEL_TRIGGER;
kfraser@11541 122 apic_write_around(APIC_LVT0, v);
kfraser@11541 123 }
kfraser@11541 124
kaf24@4804 125 int get_physical_broadcast(void)
kaf24@4804 126 {
kfraser@11541 127 if (modern_apic())
kaf24@4804 128 return 0xff;
kaf24@4804 129 else
kaf24@4804 130 return 0xf;
kaf24@4804 131 }
kaf24@4804 132
kaf24@1452 133 int get_maxlvt(void)
kaf24@1452 134 {
kaf24@1452 135 unsigned int v, ver, maxlvt;
kaf24@1452 136
kaf24@1452 137 v = apic_read(APIC_LVR);
kaf24@1452 138 ver = GET_APIC_VERSION(v);
kaf24@1452 139 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 140 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 141 return maxlvt;
kaf24@1452 142 }
kaf24@1452 143
kaf24@1452 144 void clear_local_APIC(void)
kaf24@1452 145 {
kaf24@1452 146 int maxlvt;
kaf24@1452 147 unsigned long v;
kaf24@1452 148
kaf24@1452 149 maxlvt = get_maxlvt();
kaf24@1452 150
kaf24@1452 151 /*
kaf24@1452 152 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 153 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 154 */
kaf24@1452 155 if (maxlvt >= 3) {
kaf24@1452 156 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 157 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 158 }
kaf24@1452 159 /*
kaf24@1452 160 * Careful: we have to set masks only first to deassert
kaf24@1452 161 * any level-triggered sources.
kaf24@1452 162 */
kaf24@1452 163 v = apic_read(APIC_LVTT);
kaf24@1452 164 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 165 v = apic_read(APIC_LVT0);
kaf24@1452 166 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 167 v = apic_read(APIC_LVT1);
kaf24@1452 168 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 169 if (maxlvt >= 4) {
kaf24@1452 170 v = apic_read(APIC_LVTPC);
kaf24@1452 171 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 172 }
kaf24@1452 173
kaf24@5211 174 /* lets not touch this if we didn't frob it */
kaf24@5211 175 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 176 if (maxlvt >= 5) {
kaf24@5211 177 v = apic_read(APIC_LVTTHMR);
kaf24@5211 178 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
kaf24@5211 179 }
kaf24@5211 180 #endif
kaf24@1452 181 /*
kaf24@1452 182 * Clean APIC state for other OSs:
kaf24@1452 183 */
kaf24@1452 184 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 185 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 186 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 187 if (maxlvt >= 3)
kaf24@1452 188 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 189 if (maxlvt >= 4)
kaf24@1452 190 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 191
kaf24@5211 192 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 193 if (maxlvt >= 5)
kaf24@5211 194 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
kaf24@5211 195 #endif
kaf24@1452 196 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kfraser@11204 197 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 198 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 199 apic_write(APIC_ESR, 0);
kaf24@1452 200 apic_read(APIC_ESR);
kaf24@1452 201 }
kaf24@1452 202 }
kaf24@1452 203
kaf24@1452 204 void __init connect_bsp_APIC(void)
kaf24@1452 205 {
kaf24@1452 206 if (pic_mode) {
kaf24@1452 207 /*
kaf24@1452 208 * Do not trust the local APIC being empty at bootup.
kaf24@1452 209 */
kaf24@1452 210 clear_local_APIC();
kaf24@1452 211 /*
kaf24@1452 212 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 213 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 214 */
kaf24@4888 215 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 216 "enabling APIC mode.\n");
kaf24@1452 217 outb(0x70, 0x22);
kaf24@1452 218 outb(0x01, 0x23);
kaf24@1452 219 }
kaf24@5211 220 enable_apic_mode();
kaf24@1452 221 }
kaf24@1452 222
kaf24@8847 223 void disconnect_bsp_APIC(int virt_wire_setup)
kaf24@1452 224 {
kaf24@1452 225 if (pic_mode) {
kaf24@1452 226 /*
kaf24@1452 227 * Put the board back into PIC mode (has an effect
kaf24@1452 228 * only on certain older boards). Note that APIC
kaf24@1452 229 * interrupts, including IPIs, won't work beyond
kaf24@1452 230 * this point! The only exception are INIT IPIs.
kaf24@1452 231 */
kaf24@4888 232 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 233 "entering PIC mode.\n");
kaf24@1452 234 outb(0x70, 0x22);
kaf24@1452 235 outb(0x00, 0x23);
kaf24@1452 236 }
kaf24@8847 237 else {
kaf24@8847 238 /* Go back to Virtual Wire compatibility mode */
kaf24@8847 239 unsigned long value;
kaf24@8847 240
kaf24@8847 241 /* For the spurious interrupt use vector F, and enable it */
kaf24@8847 242 value = apic_read(APIC_SPIV);
kaf24@8847 243 value &= ~APIC_VECTOR_MASK;
kaf24@8847 244 value |= APIC_SPIV_APIC_ENABLED;
kaf24@8847 245 value |= 0xf;
kaf24@8847 246 apic_write_around(APIC_SPIV, value);
kaf24@8847 247
kaf24@8847 248 if (!virt_wire_setup) {
kaf24@8847 249 /* For LVT0 make it edge triggered, active high, external and enabled */
kaf24@8847 250 value = apic_read(APIC_LVT0);
kaf24@8847 251 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 252 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 253 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
kaf24@8847 254 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 255 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
kaf24@8847 256 apic_write_around(APIC_LVT0, value);
kaf24@8847 257 }
kaf24@8847 258 else {
kaf24@8847 259 /* Disable LVT0 */
kaf24@8847 260 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@8847 261 }
kaf24@8847 262
kaf24@8847 263 /* For LVT1 make it edge triggered, active high, nmi and enabled */
kaf24@8847 264 value = apic_read(APIC_LVT1);
kaf24@8847 265 value &= ~(
kaf24@8847 266 APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 267 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 268 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
kaf24@8847 269 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 270 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
kaf24@8847 271 apic_write_around(APIC_LVT1, value);
kaf24@8847 272 }
kaf24@1452 273 }
kaf24@1452 274
kaf24@1452 275 void disable_local_APIC(void)
kaf24@1452 276 {
kaf24@1452 277 unsigned long value;
kaf24@1452 278
kaf24@1452 279 clear_local_APIC();
kaf24@1452 280
kaf24@1452 281 /*
kaf24@1452 282 * Disable APIC (implies clearing of registers
kaf24@1452 283 * for 82489DX!).
kaf24@1452 284 */
kaf24@1452 285 value = apic_read(APIC_SPIV);
kaf24@1452 286 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 287 apic_write_around(APIC_SPIV, value);
kaf24@1452 288
kaf24@1452 289 if (enabled_via_apicbase) {
kaf24@1452 290 unsigned int l, h;
kaf24@1452 291 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 292 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 293 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 294 }
kaf24@1452 295 }
kaf24@1452 296
kaf24@1452 297 /*
kaf24@1452 298 * This is to verify that we're looking at a real local APIC.
kaf24@1452 299 * Check these against your board if the CPUs aren't getting
kaf24@1452 300 * started for no apparent reason.
kaf24@1452 301 */
kaf24@1452 302 int __init verify_local_APIC(void)
kaf24@1452 303 {
kaf24@1452 304 unsigned int reg0, reg1;
kaf24@1452 305
kaf24@1452 306 /*
kaf24@1452 307 * The version register is read-only in a real APIC.
kaf24@1452 308 */
kaf24@1452 309 reg0 = apic_read(APIC_LVR);
kaf24@4888 310 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
keir@17552 311
keir@17552 312 /* We don't try writing LVR in x2APIC mode since that incurs #GP. */
keir@17552 313 if ( !x2apic_enabled )
keir@17552 314 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 315 reg1 = apic_read(APIC_LVR);
kaf24@4888 316 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 317
kaf24@1452 318 /*
kaf24@1452 319 * The two version reads above should print the same
kaf24@1452 320 * numbers. If the second one is different, then we
kaf24@1452 321 * poke at a non-APIC.
kaf24@1452 322 */
kaf24@1452 323 if (reg1 != reg0)
kaf24@1452 324 return 0;
kaf24@1452 325
kaf24@1452 326 /*
kaf24@1452 327 * Check if the version looks reasonably.
kaf24@1452 328 */
kaf24@1452 329 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 330 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 331 return 0;
kaf24@1452 332 reg1 = get_maxlvt();
kaf24@1452 333 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 334 return 0;
kaf24@1452 335
kaf24@1452 336 /*
kaf24@1452 337 * The ID register is read/write in a real APIC.
kaf24@1452 338 */
kaf24@1452 339 reg0 = apic_read(APIC_ID);
kaf24@4888 340 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 341
kaf24@1452 342 /*
kaf24@1452 343 * The next two are just to see if we have sane values.
kaf24@1452 344 * They're only really relevant if we're in Virtual Wire
kaf24@1452 345 * compatibility mode, but most boxes are anymore.
kaf24@1452 346 */
kaf24@1452 347 reg0 = apic_read(APIC_LVT0);
kaf24@4888 348 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 349 reg1 = apic_read(APIC_LVT1);
kaf24@4888 350 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 351
kaf24@1452 352 return 1;
kaf24@1452 353 }
kaf24@1452 354
kaf24@1452 355 void __init sync_Arb_IDs(void)
kaf24@1452 356 {
kfraser@11541 357 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
kfraser@11541 358 And not needed on AMD */
kfraser@11541 359 if (modern_apic())
iap10@4548 360 return;
kaf24@1452 361 /*
kaf24@1452 362 * Wait for idle.
kaf24@1452 363 */
kaf24@1452 364 apic_wait_icr_idle();
kaf24@1452 365
kaf24@4888 366 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 367 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 368 | APIC_DM_INIT);
kaf24@1452 369 }
kaf24@1452 370
kaf24@1452 371 extern void __error_in_apic_c (void);
kaf24@1452 372
kaf24@4888 373 /*
kaf24@4888 374 * An initial setup of the virtual wire mode.
kaf24@4888 375 */
kaf24@1452 376 void __init init_bsp_APIC(void)
kaf24@1452 377 {
kaf24@4620 378 unsigned long value, ver;
kaf24@4620 379
kaf24@4620 380 /*
kaf24@4888 381 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 382 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 383 */
kaf24@4620 384 if (smp_found_config || !cpu_has_apic)
kaf24@4620 385 return;
kaf24@4620 386
kaf24@4620 387 value = apic_read(APIC_LVR);
kaf24@4620 388 ver = GET_APIC_VERSION(value);
kaf24@4620 389
kaf24@4620 390 /*
kaf24@4620 391 * Do not trust the local APIC being empty at bootup.
kaf24@4620 392 */
kaf24@4620 393 clear_local_APIC();
kaf24@4620 394
kaf24@4620 395 /*
kaf24@4620 396 * Enable APIC.
kaf24@4620 397 */
kaf24@4620 398 value = apic_read(APIC_SPIV);
kaf24@4620 399 value &= ~APIC_VECTOR_MASK;
kaf24@4620 400 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 401
kaf24@4620 402 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 403 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 404 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 405 else
kaf24@4620 406 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 407 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 408 apic_write_around(APIC_SPIV, value);
kaf24@4620 409
kaf24@4620 410 /*
kaf24@4620 411 * Set up the virtual wire mode.
kaf24@4620 412 */
kaf24@4620 413 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 414 value = APIC_DM_NMI;
kaf24@4620 415 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 416 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 417 apic_write_around(APIC_LVT1, value);
kaf24@1452 418 }
kaf24@1452 419
kaf24@8847 420 void __devinit setup_local_APIC(void)
kaf24@1452 421 {
iap10@4548 422 unsigned long oldvalue, value, ver, maxlvt;
kfraser@11541 423 int i, j;
iap10@4548 424
iap10@4548 425 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 426 if (esr_disable) {
iap10@4548 427 apic_write(APIC_ESR, 0);
iap10@4548 428 apic_write(APIC_ESR, 0);
iap10@4548 429 apic_write(APIC_ESR, 0);
iap10@4548 430 apic_write(APIC_ESR, 0);
iap10@4548 431 }
kaf24@1452 432
kaf24@1452 433 value = apic_read(APIC_LVR);
kaf24@1452 434 ver = GET_APIC_VERSION(value);
kaf24@1452 435
kaf24@1452 436 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 437 __error_in_apic_c();
kaf24@1452 438
iap10@4548 439 /*
iap10@4548 440 * Double-check whether this APIC is really registered.
iap10@4548 441 */
iap10@4548 442 if (!apic_id_registered())
kaf24@1452 443 BUG();
kaf24@1452 444
kaf24@1452 445 /*
kaf24@1452 446 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 447 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 448 * document number 292116). So here it goes...
kaf24@1452 449 */
iap10@4548 450 init_apic_ldr();
kaf24@1452 451
kaf24@1452 452 /*
kaf24@1452 453 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 454 * later on.
kaf24@1452 455 */
kaf24@1452 456 value = apic_read(APIC_TASKPRI);
kaf24@1452 457 value &= ~APIC_TPRI_MASK;
kaf24@1452 458 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 459
kaf24@1452 460 /*
kfraser@11541 461 * After a crash, we no longer service the interrupts and a pending
kfraser@11541 462 * interrupt from previous kernel might still have ISR bit set.
kfraser@11541 463 *
kfraser@11541 464 * Most probably by now CPU has serviced that pending interrupt and
kfraser@11541 465 * it might not have done the ack_APIC_irq() because it thought,
kfraser@11541 466 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
kfraser@11541 467 * does not clear the ISR bit and cpu thinks it has already serivced
kfraser@11541 468 * the interrupt. Hence a vector might get locked. It was noticed
kfraser@11541 469 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
kfraser@11541 470 */
kfraser@11541 471 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
kfraser@11541 472 value = apic_read(APIC_ISR + i*0x10);
kfraser@11541 473 for (j = 31; j >= 0; j--) {
kfraser@11541 474 if (value & (1<<j))
kfraser@11541 475 ack_APIC_irq();
kfraser@11541 476 }
kfraser@11541 477 }
kfraser@11541 478
kfraser@11541 479 /*
kaf24@1452 480 * Now that we are all set up, enable the APIC
kaf24@1452 481 */
kaf24@1452 482 value = apic_read(APIC_SPIV);
kaf24@1452 483 value &= ~APIC_VECTOR_MASK;
kaf24@1452 484 /*
kaf24@1452 485 * Enable APIC
kaf24@1452 486 */
kaf24@1452 487 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 488
iap10@4548 489 /*
iap10@4548 490 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 491 * certain networking cards. If high frequency interrupts are
iap10@4548 492 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 493 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 494 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 495 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 496 * away, oh well :-(
iap10@4548 497 *
iap10@4548 498 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 499 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 500 * BX chipset. ]
iap10@4548 501 */
iap10@4548 502 /*
iap10@4548 503 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 504 * frequent as it makes the interrupt distributon model be more
iap10@4548 505 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 506 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 507 */
iap10@4548 508 #if 1
kaf24@1452 509 /* Enable focus processor (bit==0) */
kaf24@1452 510 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 511 #else
iap10@4548 512 /* Disable focus processor (bit==1) */
iap10@4548 513 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 514 #endif
iap10@4548 515 /*
iap10@4548 516 * Set spurious IRQ vector
iap10@4548 517 */
kaf24@1452 518 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 519 apic_write_around(APIC_SPIV, value);
kaf24@1452 520
kaf24@1452 521 /*
kaf24@1452 522 * Set up LVT0, LVT1:
kaf24@1452 523 *
kaf24@1452 524 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 525 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 526 * we delegate interrupts to the 8259A.
kaf24@1452 527 */
kaf24@1452 528 /*
kaf24@1452 529 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 530 */
kaf24@1452 531 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 532 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 533 value = APIC_DM_EXTINT;
kaf24@4888 534 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 535 smp_processor_id());
kaf24@1452 536 } else {
kaf24@1452 537 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 538 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 539 smp_processor_id());
kaf24@1452 540 }
kaf24@1452 541 apic_write_around(APIC_LVT0, value);
kaf24@1452 542
kaf24@1452 543 /*
kaf24@1452 544 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 545 */
kaf24@1452 546 if (!smp_processor_id())
kaf24@1452 547 value = APIC_DM_NMI;
kaf24@1452 548 else
kaf24@1452 549 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 550 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 551 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 552 apic_write_around(APIC_LVT1, value);
kaf24@1452 553
iap10@4548 554 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 555 maxlvt = get_maxlvt();
kaf24@1452 556 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 557 apic_write(APIC_ESR, 0);
iap10@4548 558 oldvalue = apic_read(APIC_ESR);
kaf24@1452 559
iap10@4548 560 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 561 apic_write_around(APIC_LVTERR, value);
iap10@4548 562 /*
iap10@4548 563 * spec says clear errors after enabling vector.
iap10@4548 564 */
kaf24@1452 565 if (maxlvt > 3)
kaf24@1452 566 apic_write(APIC_ESR, 0);
kaf24@1452 567 value = apic_read(APIC_ESR);
iap10@4548 568 if (value != oldvalue)
kaf24@4888 569 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 570 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 571 oldvalue, value);
kaf24@1452 572 } else {
iap10@4548 573 if (esr_disable)
iap10@4548 574 /*
iap10@4548 575 * Something untraceble is creating bad interrupts on
iap10@4548 576 * secondary quads ... for the moment, just leave the
iap10@4548 577 * ESR disabled - we can't do anything useful with the
iap10@4548 578 * errors anyway - mbligh
iap10@4548 579 */
iap10@4548 580 printk("Leaving ESR disabled.\n");
kaf24@4888 581 else
kaf24@4888 582 printk("No ESR for 82489DX.\n");
kaf24@1452 583 }
kaf24@1452 584
kaf24@8594 585 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@8594 586 setup_apic_nmi_watchdog();
kaf24@8847 587 apic_pm_activate();
kaf24@1452 588 }
kaf24@1452 589
kfraser@15314 590 static struct {
kfraser@15314 591 int active;
kfraser@15314 592 /* r/w apic fields */
kfraser@15314 593 unsigned int apic_id;
kfraser@15314 594 unsigned int apic_taskpri;
kfraser@15314 595 unsigned int apic_ldr;
kfraser@15314 596 unsigned int apic_dfr;
kfraser@15314 597 unsigned int apic_spiv;
kfraser@15314 598 unsigned int apic_lvtt;
kfraser@15314 599 unsigned int apic_lvtpc;
kfraser@15314 600 unsigned int apic_lvt0;
kfraser@15314 601 unsigned int apic_lvt1;
kfraser@15314 602 unsigned int apic_lvterr;
kfraser@15314 603 unsigned int apic_tmict;
kfraser@15314 604 unsigned int apic_tdcr;
kfraser@15314 605 unsigned int apic_thmr;
kfraser@15314 606 } apic_pm_state;
kfraser@15314 607
kfraser@15314 608 int lapic_suspend(void)
kfraser@15314 609 {
kfraser@15314 610 unsigned long flags;
kfraser@15314 611
kfraser@15314 612 if (!apic_pm_state.active)
kfraser@15314 613 return 0;
kfraser@15314 614
kfraser@15314 615 apic_pm_state.apic_id = apic_read(APIC_ID);
kfraser@15314 616 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
kfraser@15314 617 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
keir@17552 618 if ( !x2apic_enabled )
keir@17552 619 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
kfraser@15314 620 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
kfraser@15314 621 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
kfraser@15314 622 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
kfraser@15314 623 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
kfraser@15314 624 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
kfraser@15314 625 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
kfraser@15314 626 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
kfraser@15314 627 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
kfraser@15314 628 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
kfraser@15314 629
kfraser@15314 630 local_irq_save(flags);
kfraser@15314 631 disable_local_APIC();
kfraser@15314 632 local_irq_restore(flags);
kfraser@15314 633 return 0;
kfraser@15314 634 }
kfraser@15314 635
kfraser@15314 636 int lapic_resume(void)
kfraser@15314 637 {
kfraser@15314 638 unsigned int l, h;
kfraser@15314 639 unsigned long flags;
kfraser@15314 640
kfraser@15314 641 if (!apic_pm_state.active)
kfraser@15314 642 return 0;
kfraser@15314 643
kfraser@15314 644 local_irq_save(flags);
kfraser@15314 645
kfraser@15314 646 /*
kfraser@15314 647 * Make sure the APICBASE points to the right address
kfraser@15314 648 *
kfraser@15314 649 * FIXME! This will be wrong if we ever support suspend on
kfraser@15314 650 * SMP! We'll need to do this as part of the CPU restore!
kfraser@15314 651 */
keir@17552 652 if ( !x2apic_enabled )
keir@17552 653 {
keir@17552 654 rdmsr(MSR_IA32_APICBASE, l, h);
keir@17552 655 l &= ~MSR_IA32_APICBASE_BASE;
keir@17552 656 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
keir@17552 657 wrmsr(MSR_IA32_APICBASE, l, h);
keir@17552 658 }
keir@17552 659 else
keir@17552 660 enable_x2apic();
kfraser@15314 661
kfraser@15314 662 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
kfraser@15314 663 apic_write(APIC_ID, apic_pm_state.apic_id);
keir@17552 664 if ( !x2apic_enabled )
keir@17552 665 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
kfraser@15314 666 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
kfraser@15314 667 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
kfraser@15314 668 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
kfraser@15314 669 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
kfraser@15314 670 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
kfraser@15314 671 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
kfraser@15314 672 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
kfraser@15314 673 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
kfraser@15314 674 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
kfraser@15314 675 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
kfraser@15314 676 apic_write(APIC_ESR, 0);
kfraser@15314 677 apic_read(APIC_ESR);
kfraser@15314 678 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
kfraser@15314 679 apic_write(APIC_ESR, 0);
kfraser@15314 680 apic_read(APIC_ESR);
kfraser@15314 681 local_irq_restore(flags);
kfraser@15314 682 return 0;
kfraser@15314 683 }
kfraser@15314 684
kfraser@15314 685
kfraser@11541 686 /*
kfraser@11541 687 * If Linux enabled the LAPIC against the BIOS default
kfraser@11541 688 * disable it down before re-entering the BIOS on shutdown.
kfraser@11541 689 * Otherwise the BIOS may get confused and not power-off.
kfraser@11541 690 * Additionally clear all LVT entries before disable_local_APIC
kfraser@11541 691 * for the case where Linux didn't enable the LAPIC.
kfraser@11541 692 */
kfraser@11541 693 void lapic_shutdown(void)
kfraser@11541 694 {
kfraser@11541 695 unsigned long flags;
kfraser@11541 696
kfraser@11541 697 if (!cpu_has_apic)
kfraser@11541 698 return;
kfraser@11541 699
kfraser@11541 700 local_irq_save(flags);
kfraser@11541 701 clear_local_APIC();
kfraser@11541 702
kfraser@11541 703 if (enabled_via_apicbase)
kfraser@11541 704 disable_local_APIC();
kfraser@11541 705
kfraser@11541 706 local_irq_restore(flags);
kfraser@11541 707 }
kfraser@11541 708
kfraser@15314 709 static void apic_pm_activate(void)
kfraser@15314 710 {
kfraser@15314 711 apic_pm_state.active = 1;
kfraser@15314 712 }
kaf24@8847 713
kaf24@1452 714 /*
kaf24@1452 715 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 716 * Original code written by Keir Fraser.
kaf24@1452 717 */
kaf24@1452 718
kaf24@5211 719 static void __init lapic_disable(char *str)
kaf24@5211 720 {
kaf24@5211 721 enable_local_apic = -1;
kaf24@5211 722 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 723 }
kaf24@5211 724 custom_param("nolapic", lapic_disable);
kaf24@5211 725
kaf24@5211 726 static void __init lapic_enable(char *str)
kaf24@5211 727 {
kaf24@5211 728 enable_local_apic = 1;
kaf24@5211 729 }
kaf24@5211 730 custom_param("lapic", lapic_enable);
kaf24@5211 731
kaf24@4888 732 static void __init apic_set_verbosity(char *str)
kaf24@4888 733 {
kaf24@4888 734 if (strcmp("debug", str) == 0)
kaf24@4888 735 apic_verbosity = APIC_DEBUG;
kaf24@4888 736 else if (strcmp("verbose", str) == 0)
kaf24@4888 737 apic_verbosity = APIC_VERBOSE;
kaf24@5211 738 else
kaf24@5211 739 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@5211 740 " use apic_verbosity=verbose or apic_verbosity=debug", str);
kaf24@4888 741 }
kaf24@5211 742 custom_param("apic_verbosity", apic_set_verbosity);
kaf24@4888 743
kaf24@1452 744 static int __init detect_init_APIC (void)
kaf24@1452 745 {
kaf24@1452 746 u32 h, l, features;
kaf24@1452 747
kaf24@5211 748 /* Disabled by kernel option? */
kaf24@5211 749 if (enable_local_apic < 0)
kaf24@5211 750 return -1;
kaf24@5211 751
kaf24@1452 752 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 753 case X86_VENDOR_AMD:
iap10@4548 754 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
keir@16093 755 (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
kaf24@1452 756 break;
kaf24@1452 757 goto no_apic;
kaf24@1452 758 case X86_VENDOR_INTEL:
iap10@4548 759 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 760 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 761 break;
kaf24@1452 762 goto no_apic;
kaf24@1452 763 default:
kaf24@1452 764 goto no_apic;
kaf24@1452 765 }
kaf24@1452 766
kaf24@1452 767 if (!cpu_has_apic) {
kaf24@1452 768 /*
kaf24@5211 769 * Over-ride BIOS and try to enable the local
kaf24@5211 770 * APIC only if "lapic" specified.
kaf24@5211 771 */
kaf24@5211 772 if (enable_local_apic <= 0) {
kaf24@5211 773 printk("Local APIC disabled by BIOS -- "
kaf24@5211 774 "you can enable it with \"lapic\"\n");
kaf24@5211 775 return -1;
kaf24@5211 776 }
kaf24@5211 777 /*
kaf24@1452 778 * Some BIOSes disable the local APIC in the
kaf24@1452 779 * APIC_BASE MSR. This can only be done in
iap10@4548 780 * software for Intel P6 or later and AMD K7
iap10@4548 781 * (Model > 1) or later.
kaf24@1452 782 */
kaf24@1452 783 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 784 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 785 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 786 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 787 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 788 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 789 enabled_via_apicbase = 1;
kaf24@1452 790 }
kaf24@1452 791 }
kaf24@4888 792 /*
kaf24@4888 793 * The APIC feature bit should now be enabled
kaf24@4888 794 * in `cpuid'
kaf24@4888 795 */
kaf24@1452 796 features = cpuid_edx(1);
kaf24@1452 797 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 798 printk("Could not enable APIC!\n");
kaf24@1452 799 return -1;
kaf24@1452 800 }
kaf24@4619 801
iap10@4548 802 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 803 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 804
kaf24@1452 805 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 806 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 807 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 808 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 809
kaf24@4619 810 if (nmi_watchdog != NMI_NONE)
kaf24@4619 811 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 812
kaf24@1452 813 printk("Found and enabled local APIC!\n");
iap10@4548 814
kaf24@8847 815 apic_pm_activate();
kaf24@8847 816
kaf24@1452 817 return 0;
kaf24@1452 818
iap10@4548 819 no_apic:
kaf24@1452 820 printk("No local APIC present or hardware disabled\n");
kaf24@1452 821 return -1;
kaf24@1452 822 }
kaf24@1452 823
keir@17552 824 void enable_x2apic(void)
keir@17552 825 {
keir@17552 826 u32 lo, hi;
keir@17552 827
keir@17552 828 rdmsr(MSR_IA32_APICBASE, lo, hi);
keir@17552 829 if ( !(lo & MSR_IA32_APICBASE_EXTD) )
keir@17552 830 {
keir@17552 831 lo |= MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD;
keir@17552 832 wrmsr(MSR_IA32_APICBASE, lo, 0);
keir@17552 833 printk("x2APIC mode enabled.\n");
keir@17552 834 }
keir@17552 835 else
keir@17552 836 printk("x2APIC mode enabled by BIOS.\n");
keir@17552 837
keir@17552 838 x2apic_enabled = 1;
keir@17552 839 }
keir@17552 840
kaf24@1452 841 void __init init_apic_mappings(void)
kaf24@1452 842 {
iap10@4548 843 unsigned long apic_phys;
kaf24@1452 844
keir@17552 845 if ( x2apic_enabled )
keir@17552 846 goto __next;
kaf24@1452 847 /*
iap10@4548 848 * If no local APIC can be found then set up a fake all
iap10@4548 849 * zeroes page to simulate the local APIC and another
iap10@4548 850 * one for the IO-APIC.
kaf24@1452 851 */
kaf24@9582 852 if (!smp_found_config && detect_init_APIC()) {
kaf24@5398 853 apic_phys = __pa(alloc_xenheap_page());
kfraser@15405 854 clear_page(__va(apic_phys));
kaf24@9582 855 } else
kaf24@1452 856 apic_phys = mp_lapic_addr;
kaf24@1452 857
kaf24@1452 858 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 859 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 860 apic_phys);
kaf24@1452 861
keir@17552 862 __next:
kaf24@1452 863 /*
kaf24@1452 864 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 865 * default configuration (or the MP table is broken).
kaf24@1452 866 */
kaf24@1452 867 if (boot_cpu_physical_apicid == -1U)
keir@17552 868 boot_cpu_physical_apicid = get_apic_id();
kaf24@1452 869
kaf24@1452 870 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 871 {
iap10@4548 872 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 873 int i;
kaf24@1452 874
kaf24@1452 875 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 876 if (smp_found_config) {
kaf24@1452 877 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 878 if (!ioapic_phys) {
iap10@4548 879 printk(KERN_ERR
iap10@4548 880 "WARNING: bogus zero IO-APIC "
iap10@4548 881 "address found in MPTABLE, "
iap10@4548 882 "disabling IO/APIC support!\n");
iap10@4548 883 smp_found_config = 0;
iap10@4548 884 skip_ioapic_setup = 1;
iap10@4548 885 goto fake_ioapic_page;
iap10@4548 886 }
iap10@4548 887 } else {
iap10@4548 888 fake_ioapic_page:
kaf24@5398 889 ioapic_phys = __pa(alloc_xenheap_page());
kfraser@15405 890 clear_page(__va(ioapic_phys));
iap10@4548 891 }
kaf24@1452 892 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 893 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 894 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 895 idx++;
kaf24@1452 896 }
kaf24@1452 897 }
kaf24@1452 898 #endif
kaf24@1452 899 }
kaf24@1452 900
kaf24@1452 901 /*****************************************************************************
kaf24@1452 902 * APIC calibration
kaf24@1452 903 *
kaf24@1452 904 * The APIC is programmed in bus cycles.
kaf24@1452 905 * Timeout values should specified in real time units.
kaf24@1452 906 * The "cheapest" time source is the cyclecounter.
kaf24@1452 907 *
kaf24@1452 908 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 909 *
kaf24@1452 910 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 911 * timer chip to generate periodic timer interupts.
kaf24@1452 912 *****************************************************************************/
kaf24@1452 913
kaf24@1452 914 /* used for system time scaling */
kaf24@1672 915 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 916 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 917 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 918
kaf24@1452 919 /*
kaf24@1452 920 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 921 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 922 * to calibrate.
kaf24@1452 923 */
kaf24@1452 924 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 925 {
kaf24@1452 926 /*extern spinlock_t i8253_lock;*/
kaf24@1452 927 /*unsigned long flags;*/
iap10@4548 928
kaf24@1452 929 unsigned int count;
iap10@4548 930
kaf24@1452 931 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 932
iap10@4548 933 outb_p(0x00, PIT_MODE);
iap10@4548 934 count = inb_p(PIT_CH0);
iap10@4548 935 count |= inb_p(PIT_CH0) << 8;
iap10@4548 936
kaf24@1452 937 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 938
kaf24@1452 939 return count;
kaf24@1452 940 }
kaf24@1452 941
iap10@4548 942 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 943 static void __init wait_8254_wraparound(void)
kaf24@1452 944 {
kaf24@4888 945 unsigned int curr_count, prev_count;
kaf24@4888 946
kaf24@1452 947 curr_count = get_8254_timer_count();
kaf24@1452 948 do {
kaf24@1452 949 prev_count = curr_count;
kaf24@1452 950 curr_count = get_8254_timer_count();
iap10@4548 951
kaf24@4888 952 /* workaround for broken Mercury/Neptune */
kaf24@4888 953 if (prev_count >= curr_count + 0x100)
kaf24@4888 954 curr_count = get_8254_timer_count();
kaf24@4888 955
kaf24@4888 956 } while (prev_count >= curr_count);
kaf24@1452 957 }
kaf24@1452 958
kaf24@1452 959 /*
iap10@4548 960 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 961 * we override this later
iap10@4548 962 */
kaf24@4888 963 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 964
iap10@4548 965 /*
kaf24@1452 966 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 967 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 968 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 969 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 970 * call this function only once, with the real, calibrated value.
kaf24@1452 971 *
kaf24@1452 972 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 973 * P5 APIC double write bug.
kaf24@1452 974 */
iap10@4548 975
kaf24@1452 976 #define APIC_DIVISOR 1
iap10@4548 977
kaf24@5146 978 void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 979 {
iap10@4548 980 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 981
iap10@4548 982 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 983 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 984 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 985 if (!APIC_INTEGRATED(ver))
iap10@4548 986 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 987 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 988
kaf24@1452 989 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 990 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 991
kaf24@1452 992 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 993 }
kaf24@1452 994
kfraser@15586 995 static void __devinit setup_APIC_timer(unsigned int clocks)
kaf24@1452 996 {
kaf24@1452 997 unsigned long flags;
kaf24@5146 998 local_irq_save(flags);
kaf24@5146 999 __setup_APIC_LVTT(clocks);
kaf24@5146 1000 local_irq_restore(flags);
kaf24@1452 1001 }
kaf24@1452 1002
kaf24@1452 1003 /*
kaf24@5146 1004 * In this function we calibrate APIC bus clocks to the external
kaf24@5146 1005 * timer. Unfortunately we cannot use jiffies and the timer irq
kaf24@5146 1006 * to calibrate, since some later bootup code depends on getting
kaf24@5146 1007 * the first irq? Ugh.
kaf24@1452 1008 *
kaf24@5146 1009 * We want to do the calibration only once since we
kaf24@5146 1010 * want to have local timer irqs syncron. CPUs connected
kaf24@5146 1011 * by the same APIC bus have the very same bus frequency.
kaf24@5146 1012 * And we want to have irqs off anyways, no accidental
kaf24@5146 1013 * APIC irq that way.
kaf24@1452 1014 */
kaf24@1452 1015
kaf24@1452 1016 int __init calibrate_APIC_clock(void)
kaf24@1452 1017 {
kaf24@1452 1018 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 1019 long tt1, tt2;
kaf24@1452 1020 long result;
kaf24@1452 1021 int i;
kaf24@1452 1022 const int LOOPS = HZ/10;
kaf24@1452 1023
kaf24@4888 1024 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 1025
iap10@4548 1026 /*
iap10@4548 1027 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 1028 * value into the APIC clock, we just want to get the
iap10@4548 1029 * counter running for calibration.
iap10@4548 1030 */
kaf24@1452 1031 __setup_APIC_LVTT(1000000000);
kaf24@1452 1032
iap10@4548 1033 /*
iap10@4548 1034 * The timer chip counts down to zero. Let's wait
kaf24@1452 1035 * for a wraparound to start exact measurement:
iap10@4548 1036 * (the current tick might have been already half done)
iap10@4548 1037 */
iap10@4548 1038 wait_timer_tick();
iap10@4548 1039
iap10@4548 1040 /*
iap10@4548 1041 * We wrapped around just now. Let's start:
iap10@4548 1042 */
iap10@4548 1043 if (cpu_has_tsc)
kaf24@4619 1044 rdtscll(t1);
kaf24@1452 1045 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 1046
iap10@4548 1047 /*
iap10@4548 1048 * Let's wait LOOPS wraprounds:
iap10@4548 1049 */
kaf24@1452 1050 for (i = 0; i < LOOPS; i++)
iap10@4548 1051 wait_timer_tick();
kaf24@1452 1052
kaf24@1452 1053 tt2 = apic_read(APIC_TMCCT);
iap10@4548 1054 if (cpu_has_tsc)
kaf24@4619 1055 rdtscll(t2);
kaf24@1452 1056
iap10@4548 1057 /*
iap10@4548 1058 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 1059 * might have overflown, but note that we use signed
kaf24@1452 1060 * longs, thus no extra care needed.
kaf24@4888 1061 *
kaf24@4888 1062 * underflown to be exact, as the timer counts down ;)
iap10@4548 1063 */
iap10@4548 1064
kaf24@1452 1065 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 1066
iap10@4548 1067 if (cpu_has_tsc)
kaf24@4888 1068 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 1069 "%ld.%04ld MHz.\n",
kaf24@4888 1070 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 1071 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 1072
kaf24@4888 1073 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kfraser@11204 1074 "%ld.%04ld MHz.\n",
kfraser@11204 1075 result/(1000000/HZ),
kfraser@11204 1076 result%(1000000/HZ));
kaf24@1452 1077
kaf24@1452 1078 /* set up multipliers for accurate timer code */
kaf24@1452 1079 bus_freq = result*HZ;
kaf24@1452 1080 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 1081 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 1082
kaf24@4888 1083 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 1084 /* reset APIC to zero timeout value */
kaf24@1452 1085 __setup_APIC_LVTT(0);
iap10@4548 1086
kaf24@1452 1087 return result;
kaf24@1452 1088 }
kaf24@1452 1089
kaf24@9184 1090 u32 get_apic_bus_cycle(void)
kaf24@7546 1091 {
kaf24@9184 1092 return bus_cycle;
kaf24@7546 1093 }
kaf24@5146 1094
kaf24@5146 1095 static unsigned int calibration_result;
kaf24@5146 1096
kaf24@5146 1097 void __init setup_boot_APIC_clock(void)
kaf24@1452 1098 {
kaf24@8847 1099 unsigned long flags;
kaf24@5146 1100 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
kaf24@1452 1101 using_apic_timer = 1;
kaf24@5146 1102
kaf24@8847 1103 local_irq_save(flags);
kaf24@8847 1104
kaf24@5146 1105 calibration_result = calibrate_APIC_clock();
kaf24@5146 1106 /*
kaf24@5146 1107 * Now set up the timer for real.
kaf24@5146 1108 */
kaf24@5146 1109 setup_APIC_timer(calibration_result);
kaf24@5146 1110
kaf24@8847 1111 local_irq_restore(flags);
kaf24@5146 1112 }
kaf24@5146 1113
kaf24@8847 1114 void __devinit setup_secondary_APIC_clock(void)
kaf24@5146 1115 {
kaf24@5146 1116 setup_APIC_timer(calibration_result);
kaf24@5146 1117 }
kaf24@5146 1118
kaf24@8847 1119 void disable_APIC_timer(void)
kaf24@5146 1120 {
kaf24@5146 1121 if (using_apic_timer) {
kaf24@5146 1122 unsigned long v;
kaf24@5146 1123
kaf24@5146 1124 v = apic_read(APIC_LVTT);
kaf24@5146 1125 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@5146 1126 }
kaf24@5146 1127 }
kaf24@5146 1128
kaf24@5146 1129 void enable_APIC_timer(void)
kaf24@5146 1130 {
kaf24@5146 1131 if (using_apic_timer) {
kaf24@5146 1132 unsigned long v;
kaf24@5146 1133
kaf24@5146 1134 v = apic_read(APIC_LVTT);
kaf24@5146 1135 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
kaf24@5146 1136 }
kaf24@1452 1137 }
kaf24@1452 1138
kaf24@1452 1139 #undef APIC_DIVISOR
kaf24@1452 1140
kaf24@1452 1141 /*
kaf24@1452 1142 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 1143 * returns 1 on success
kaf24@1452 1144 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 1145 */
kaf24@8586 1146 int reprogram_timer(s_time_t timeout)
kaf24@1452 1147 {
kaf24@1452 1148 s_time_t now;
kaf24@1452 1149 s_time_t expire;
kaf24@1452 1150 u64 apic_tmict;
kaf24@1452 1151
kaf24@1452 1152 /*
kfraser@14340 1153 * If we don't have local APIC then we just poll the timer list off the
kfraser@14340 1154 * PIT interrupt.
kfraser@14340 1155 */
kfraser@14340 1156 if ( !cpu_has_apic )
kfraser@14340 1157 return 1;
kfraser@14340 1158
kfraser@14340 1159 /*
kaf24@1452 1160 * We use this value because we don't trust zero (we think it may just
kaf24@1452 1161 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 1162 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 1163 */
kaf24@1452 1164 if ( timeout == 0 )
kaf24@1452 1165 {
kaf24@1452 1166 apic_tmict = 0xffffffff;
kaf24@1452 1167 goto reprogram;
kaf24@1452 1168 }
kaf24@1452 1169
kaf24@1452 1170 now = NOW();
kaf24@1452 1171 expire = timeout - now; /* value from now */
kaf24@1452 1172
kaf24@1452 1173 if ( expire <= 0 )
kaf24@1452 1174 {
kaf24@1452 1175 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 1176 smp_processor_id(), (u32)(now>>32),
kaf24@1452 1177 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 1178 return 0;
kaf24@1452 1179 }
kaf24@1452 1180
kaf24@1452 1181 /* conversion to bus units */
kaf24@1452 1182 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 1183
kaf24@1452 1184 if ( apic_tmict >= 0xffffffff )
kaf24@1452 1185 {
kaf24@1452 1186 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 1187 apic_tmict = 0xffffffff;
kaf24@1452 1188 }
kaf24@1452 1189
kaf24@1452 1190 if ( apic_tmict == 0 )
kaf24@1452 1191 {
kaf24@1452 1192 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 1193 return 0;
kaf24@1452 1194 }
kaf24@1452 1195
kaf24@1452 1196 reprogram:
kaf24@1452 1197 /* Program the timer. */
kaf24@1452 1198 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 1199
kaf24@1452 1200 return 1;
kaf24@1452 1201 }
kaf24@1452 1202
kaf24@8846 1203 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 1204 {
kaf24@1452 1205 ack_APIC_irq();
kfraser@14595 1206 perfc_incr(apic_timer);
kaf24@8586 1207 raise_softirq(TIMER_SOFTIRQ);
kaf24@1452 1208 }
kaf24@1452 1209
kaf24@1452 1210 /*
kaf24@1452 1211 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 1212 */
kaf24@8846 1213 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1214 {
kaf24@1452 1215 unsigned long v;
kaf24@1452 1216
kaf24@8847 1217 irq_enter();
kaf24@1452 1218 /*
kaf24@1452 1219 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 1220 * if it is a vectored one. Just in case...
kaf24@1452 1221 * Spurious interrupts should not be ACKed.
kaf24@1452 1222 */
kaf24@1452 1223 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 1224 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 1225 ack_APIC_irq();
kaf24@1452 1226
kaf24@1452 1227 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@5146 1228 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 1229 smp_processor_id());
kaf24@8847 1230 irq_exit();
kaf24@1452 1231 }
kaf24@1452 1232
kaf24@1452 1233 /*
kaf24@1452 1234 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 1235 */
kaf24@1452 1236
kaf24@8846 1237 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1238 {
kaf24@1452 1239 unsigned long v, v1;
kaf24@1452 1240
kaf24@8847 1241 irq_enter();
kaf24@1452 1242 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 1243 v = apic_read(APIC_ESR);
kaf24@1452 1244 apic_write(APIC_ESR, 0);
kaf24@1452 1245 v1 = apic_read(APIC_ESR);
kaf24@1452 1246 ack_APIC_irq();
kaf24@1452 1247 atomic_inc(&irq_err_count);
kaf24@1452 1248
kaf24@1452 1249 /* Here is what the APIC error bits mean:
kaf24@1452 1250 0: Send CS error
kaf24@1452 1251 1: Receive CS error
kaf24@1452 1252 2: Send accept error
kaf24@1452 1253 3: Receive accept error
kaf24@1452 1254 4: Reserved
kaf24@1452 1255 5: Send illegal vector
kaf24@1452 1256 6: Received illegal vector
kaf24@1452 1257 7: Illegal register address
kaf24@1452 1258 */
kaf24@5146 1259 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@5146 1260 smp_processor_id(), v , v1);
kaf24@8847 1261 irq_exit();
kaf24@1452 1262 }
kaf24@1452 1263
kaf24@1452 1264 /*
keir@16940 1265 * This interrupt handles performance counters interrupt
keir@16940 1266 */
keir@16940 1267
keir@16940 1268 fastcall void smp_pmu_apic_interrupt(struct cpu_user_regs *regs)
keir@16940 1269 {
keir@16940 1270 ack_APIC_irq();
keir@16940 1271 hvm_do_pmu_interrupt(regs);
keir@16940 1272 }
keir@16940 1273
keir@16940 1274 /*
kaf24@1452 1275 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 1276 * a UP kernel.
kaf24@1452 1277 */
kaf24@1452 1278 int __init APIC_init_uniprocessor (void)
kaf24@1452 1279 {
kaf24@5211 1280 if (enable_local_apic < 0)
kaf24@5211 1281 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 1282
kaf24@1452 1283 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 1284 return -1;
kaf24@1452 1285
kaf24@1452 1286 /*
kaf24@1452 1287 * Complain if the BIOS pretends there is one.
kaf24@1452 1288 */
iap10@4548 1289 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 1290 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 1291 boot_cpu_physical_apicid);
kfraser@11541 1292 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 1293 return -1;
kaf24@1452 1294 }
kaf24@1452 1295
kaf24@1452 1296 verify_local_APIC();
kaf24@1452 1297
kaf24@1452 1298 connect_bsp_APIC();
kaf24@1452 1299
kfraser@11541 1300 /*
kfraser@11541 1301 * Hack: In case of kdump, after a crash, kernel might be booting
kfraser@11541 1302 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
kfraser@11541 1303 * might be zero if read from MP tables. Get it from LAPIC.
kfraser@11541 1304 */
kfraser@11541 1305 #ifdef CONFIG_CRASH_DUMP
keir@17552 1306 boot_cpu_physical_apicid = get_apic_id();
kfraser@11541 1307 #endif
kaf24@4804 1308 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 1309
kaf24@1452 1310 setup_local_APIC();
kaf24@1452 1311
kaf24@5146 1312 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@5146 1313 check_nmi_watchdog();
kaf24@1452 1314 #ifdef CONFIG_X86_IO_APIC
iap10@4548 1315 if (smp_found_config)
iap10@4548 1316 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 1317 setup_IO_APIC();
iap10@4548 1318 #endif
kaf24@5146 1319 setup_boot_APIC_clock();
kaf24@1452 1320
kaf24@1452 1321 return 0;
kaf24@1452 1322 }