ia64/xen-unstable

annotate xen/arch/x86/setup.c @ 1452:92b8e1efa784

bitkeeper revision 1.952 (40c8935a3XSRdQfnx5RoO7XgaggvOQ)

Towards x86_64 support. Merged a bunch of the existing x86_64 stuff
back into a generic 'x86' architecture. Aim is to share as much
as possible between 32- and 64-bit worlds.
author kaf24@scramble.cl.cam.ac.uk
date Thu Jun 10 16:59:06 2004 +0000 (2004-06-10)
parents
children fc5d9f57f546
rev   line source
kaf24@1452 1
kaf24@1452 2 #include <xen/config.h>
kaf24@1452 3 #include <xen/init.h>
kaf24@1452 4 #include <xen/interrupt.h>
kaf24@1452 5 #include <xen/lib.h>
kaf24@1452 6 #include <xen/sched.h>
kaf24@1452 7 #include <xen/pci.h>
kaf24@1452 8 #include <xen/serial.h>
kaf24@1452 9 #include <xen/acpi.h>
kaf24@1452 10 #include <xen/module.h>
kaf24@1452 11 #include <asm/bitops.h>
kaf24@1452 12 #include <asm/smp.h>
kaf24@1452 13 #include <asm/processor.h>
kaf24@1452 14 #include <asm/mpspec.h>
kaf24@1452 15 #include <asm/apic.h>
kaf24@1452 16 #include <asm/desc.h>
kaf24@1452 17 #include <asm/domain_page.h>
kaf24@1452 18 #include <asm/pdb.h>
kaf24@1452 19
kaf24@1452 20 char ignore_irq13; /* set if exception 16 works */
kaf24@1452 21 struct cpuinfo_x86 boot_cpu_data = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
kaf24@1452 22
kaf24@1452 23 /* Lots of nice things, since we only target PPro+. */
kaf24@1452 24 unsigned long mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE;
kaf24@1452 25 EXPORT_SYMBOL(mmu_cr4_features);
kaf24@1452 26
kaf24@1452 27 unsigned long wait_init_idle;
kaf24@1452 28
kaf24@1452 29 struct task_struct *idle_task[NR_CPUS] = { &idle0_task };
kaf24@1452 30
kaf24@1452 31 #ifdef CONFIG_ACPI_INTERPRETER
kaf24@1452 32 int acpi_disabled = 0;
kaf24@1452 33 #else
kaf24@1452 34 int acpi_disabled = 1;
kaf24@1452 35 #endif
kaf24@1452 36 EXPORT_SYMBOL(acpi_disabled);
kaf24@1452 37
kaf24@1452 38 #ifdef CONFIG_ACPI_BOOT
kaf24@1452 39 extern int __initdata acpi_ht;
kaf24@1452 40 int acpi_force __initdata = 0;
kaf24@1452 41 #endif
kaf24@1452 42
kaf24@1452 43 int phys_proc_id[NR_CPUS];
kaf24@1452 44 int logical_proc_id[NR_CPUS];
kaf24@1452 45
kaf24@1452 46 /* Standard macro to see if a specific flag is changeable */
kaf24@1452 47 static inline int flag_is_changeable_p(u32 flag)
kaf24@1452 48 {
kaf24@1452 49 u32 f1, f2;
kaf24@1452 50
kaf24@1452 51 asm("pushfl\n\t"
kaf24@1452 52 "pushfl\n\t"
kaf24@1452 53 "popl %0\n\t"
kaf24@1452 54 "movl %0,%1\n\t"
kaf24@1452 55 "xorl %2,%0\n\t"
kaf24@1452 56 "pushl %0\n\t"
kaf24@1452 57 "popfl\n\t"
kaf24@1452 58 "pushfl\n\t"
kaf24@1452 59 "popl %0\n\t"
kaf24@1452 60 "popfl\n\t"
kaf24@1452 61 : "=&r" (f1), "=&r" (f2)
kaf24@1452 62 : "ir" (flag));
kaf24@1452 63
kaf24@1452 64 return ((f1^f2) & flag) != 0;
kaf24@1452 65 }
kaf24@1452 66
kaf24@1452 67 /* Probe for the CPUID instruction */
kaf24@1452 68 static int __init have_cpuid_p(void)
kaf24@1452 69 {
kaf24@1452 70 return flag_is_changeable_p(X86_EFLAGS_ID);
kaf24@1452 71 }
kaf24@1452 72
kaf24@1452 73 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
kaf24@1452 74 {
kaf24@1452 75 char *v = c->x86_vendor_id;
kaf24@1452 76
kaf24@1452 77 if (!strcmp(v, "GenuineIntel"))
kaf24@1452 78 c->x86_vendor = X86_VENDOR_INTEL;
kaf24@1452 79 else if (!strcmp(v, "AuthenticAMD"))
kaf24@1452 80 c->x86_vendor = X86_VENDOR_AMD;
kaf24@1452 81 else if (!strcmp(v, "CyrixInstead"))
kaf24@1452 82 c->x86_vendor = X86_VENDOR_CYRIX;
kaf24@1452 83 else if (!strcmp(v, "UMC UMC UMC "))
kaf24@1452 84 c->x86_vendor = X86_VENDOR_UMC;
kaf24@1452 85 else if (!strcmp(v, "CentaurHauls"))
kaf24@1452 86 c->x86_vendor = X86_VENDOR_CENTAUR;
kaf24@1452 87 else if (!strcmp(v, "NexGenDriven"))
kaf24@1452 88 c->x86_vendor = X86_VENDOR_NEXGEN;
kaf24@1452 89 else if (!strcmp(v, "RiseRiseRise"))
kaf24@1452 90 c->x86_vendor = X86_VENDOR_RISE;
kaf24@1452 91 else if (!strcmp(v, "GenuineTMx86") ||
kaf24@1452 92 !strcmp(v, "TransmetaCPU"))
kaf24@1452 93 c->x86_vendor = X86_VENDOR_TRANSMETA;
kaf24@1452 94 else
kaf24@1452 95 c->x86_vendor = X86_VENDOR_UNKNOWN;
kaf24@1452 96 }
kaf24@1452 97
kaf24@1452 98 static void __init init_intel(struct cpuinfo_x86 *c)
kaf24@1452 99 {
kaf24@1452 100 extern int opt_noht, opt_noacpi;
kaf24@1452 101
kaf24@1452 102 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it */
kaf24@1452 103 if ( c->x86 == 6 && c->x86_model < 3 && c->x86_mask < 3 )
kaf24@1452 104 clear_bit(X86_FEATURE_SEP, &c->x86_capability);
kaf24@1452 105
kaf24@1452 106 if ( opt_noht )
kaf24@1452 107 {
kaf24@1452 108 opt_noacpi = 1; /* Virtual CPUs only appear in ACPI tables. */
kaf24@1452 109 clear_bit(X86_FEATURE_HT, &c->x86_capability[0]);
kaf24@1452 110 }
kaf24@1452 111
kaf24@1452 112 #ifdef CONFIG_SMP
kaf24@1452 113 if ( test_bit(X86_FEATURE_HT, &c->x86_capability) )
kaf24@1452 114 {
kaf24@1452 115 u32 eax, ebx, ecx, edx;
kaf24@1452 116 int initial_apic_id, siblings, cpu = smp_processor_id();
kaf24@1452 117
kaf24@1452 118 cpuid(1, &eax, &ebx, &ecx, &edx);
kaf24@1452 119 siblings = (ebx & 0xff0000) >> 16;
kaf24@1452 120
kaf24@1452 121 if ( siblings <= 1 )
kaf24@1452 122 {
kaf24@1452 123 printk(KERN_INFO "CPU#%d: Hyper-Threading is disabled\n", cpu);
kaf24@1452 124 }
kaf24@1452 125 else if ( siblings > 2 )
kaf24@1452 126 {
kaf24@1452 127 panic("We don't support more than two logical CPUs per package!");
kaf24@1452 128 }
kaf24@1452 129 else
kaf24@1452 130 {
kaf24@1452 131 initial_apic_id = ebx >> 24 & 0xff;
kaf24@1452 132 phys_proc_id[cpu] = initial_apic_id >> 1;
kaf24@1452 133 logical_proc_id[cpu] = initial_apic_id & 1;
kaf24@1452 134 printk(KERN_INFO "CPU#%d: Physical ID: %d, Logical ID: %d\n",
kaf24@1452 135 cpu, phys_proc_id[cpu], logical_proc_id[cpu]);
kaf24@1452 136 }
kaf24@1452 137 }
kaf24@1452 138 #endif
kaf24@1452 139 }
kaf24@1452 140
kaf24@1452 141 static void __init init_amd(struct cpuinfo_x86 *c)
kaf24@1452 142 {
kaf24@1452 143 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
kaf24@1452 144 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
kaf24@1452 145 clear_bit(0*32+31, &c->x86_capability);
kaf24@1452 146
kaf24@1452 147 switch(c->x86)
kaf24@1452 148 {
kaf24@1452 149 case 5:
kaf24@1452 150 panic("AMD K6 is not supported.\n");
kaf24@1452 151 case 6: /* An Athlon/Duron. We can trust the BIOS probably */
kaf24@1452 152 break;
kaf24@1452 153 }
kaf24@1452 154 }
kaf24@1452 155
kaf24@1452 156 /*
kaf24@1452 157 * This does the hard work of actually picking apart the CPU stuff...
kaf24@1452 158 */
kaf24@1452 159 void __init identify_cpu(struct cpuinfo_x86 *c)
kaf24@1452 160 {
kaf24@1452 161 int junk, i, cpu = smp_processor_id();
kaf24@1452 162 u32 xlvl, tfms;
kaf24@1452 163
kaf24@1452 164 phys_proc_id[cpu] = cpu;
kaf24@1452 165 logical_proc_id[cpu] = 0;
kaf24@1452 166
kaf24@1452 167 c->x86_vendor = X86_VENDOR_UNKNOWN;
kaf24@1452 168 c->cpuid_level = -1; /* CPUID not detected */
kaf24@1452 169 c->x86_model = c->x86_mask = 0; /* So far unknown... */
kaf24@1452 170 c->x86_vendor_id[0] = '\0'; /* Unset */
kaf24@1452 171 memset(&c->x86_capability, 0, sizeof c->x86_capability);
kaf24@1452 172
kaf24@1452 173 if ( !have_cpuid_p() )
kaf24@1452 174 panic("Ancient processors not supported\n");
kaf24@1452 175
kaf24@1452 176 /* Get vendor name */
kaf24@1452 177 cpuid(0x00000000, &c->cpuid_level,
kaf24@1452 178 (int *)&c->x86_vendor_id[0],
kaf24@1452 179 (int *)&c->x86_vendor_id[8],
kaf24@1452 180 (int *)&c->x86_vendor_id[4]);
kaf24@1452 181
kaf24@1452 182 get_cpu_vendor(c);
kaf24@1452 183
kaf24@1452 184 if ( c->cpuid_level == 0 )
kaf24@1452 185 panic("Decrepit CPUID not supported\n");
kaf24@1452 186
kaf24@1452 187 cpuid(0x00000001, &tfms, &junk, &junk,
kaf24@1452 188 &c->x86_capability[0]);
kaf24@1452 189 c->x86 = (tfms >> 8) & 15;
kaf24@1452 190 c->x86_model = (tfms >> 4) & 15;
kaf24@1452 191 c->x86_mask = tfms & 15;
kaf24@1452 192
kaf24@1452 193 /* AMD-defined flags: level 0x80000001 */
kaf24@1452 194 xlvl = cpuid_eax(0x80000000);
kaf24@1452 195 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
kaf24@1452 196 if ( xlvl >= 0x80000001 )
kaf24@1452 197 c->x86_capability[1] = cpuid_edx(0x80000001);
kaf24@1452 198 }
kaf24@1452 199
kaf24@1452 200 /* Transmeta-defined flags: level 0x80860001 */
kaf24@1452 201 xlvl = cpuid_eax(0x80860000);
kaf24@1452 202 if ( (xlvl & 0xffff0000) == 0x80860000 ) {
kaf24@1452 203 if ( xlvl >= 0x80860001 )
kaf24@1452 204 c->x86_capability[2] = cpuid_edx(0x80860001);
kaf24@1452 205 }
kaf24@1452 206
kaf24@1452 207 printk("CPU%d: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
kaf24@1452 208 smp_processor_id(),
kaf24@1452 209 c->x86_capability[0],
kaf24@1452 210 c->x86_capability[1],
kaf24@1452 211 c->x86_capability[2],
kaf24@1452 212 c->x86_vendor);
kaf24@1452 213
kaf24@1452 214 switch ( c->x86_vendor ) {
kaf24@1452 215 case X86_VENDOR_INTEL:
kaf24@1452 216 init_intel(c);
kaf24@1452 217 break;
kaf24@1452 218 case X86_VENDOR_AMD:
kaf24@1452 219 init_amd(c);
kaf24@1452 220 break;
kaf24@1452 221 case X86_VENDOR_UNKNOWN: /* Connectix Virtual PC reports this */
kaf24@1452 222 break;
kaf24@1452 223 case X86_VENDOR_CENTAUR:
kaf24@1452 224 break;
kaf24@1452 225 default:
kaf24@1452 226 printk("Unknown CPU identifier (%d): continuing anyway, "
kaf24@1452 227 "but might fail.\n", c->x86_vendor);
kaf24@1452 228 }
kaf24@1452 229
kaf24@1452 230 printk("CPU caps: %08x %08x %08x %08x\n",
kaf24@1452 231 c->x86_capability[0],
kaf24@1452 232 c->x86_capability[1],
kaf24@1452 233 c->x86_capability[2],
kaf24@1452 234 c->x86_capability[3]);
kaf24@1452 235
kaf24@1452 236 /*
kaf24@1452 237 * On SMP, boot_cpu_data holds the common feature set between
kaf24@1452 238 * all CPUs; so make sure that we indicate which features are
kaf24@1452 239 * common between the CPUs. The first time this routine gets
kaf24@1452 240 * executed, c == &boot_cpu_data.
kaf24@1452 241 */
kaf24@1452 242 if ( c != &boot_cpu_data ) {
kaf24@1452 243 /* AND the already accumulated flags with these */
kaf24@1452 244 for ( i = 0 ; i < NCAPINTS ; i++ )
kaf24@1452 245 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
kaf24@1452 246 }
kaf24@1452 247 }
kaf24@1452 248
kaf24@1452 249
kaf24@1452 250 unsigned long cpu_initialized;
kaf24@1452 251 void __init cpu_init(void)
kaf24@1452 252 {
kaf24@1452 253 int nr = smp_processor_id();
kaf24@1452 254 struct tss_struct * t = &init_tss[nr];
kaf24@1452 255
kaf24@1452 256 if ( test_and_set_bit(nr, &cpu_initialized) )
kaf24@1452 257 panic("CPU#%d already initialized!!!\n", nr);
kaf24@1452 258 printk("Initializing CPU#%d\n", nr);
kaf24@1452 259
kaf24@1452 260 /* Set up GDT and IDT. */
kaf24@1452 261 SET_GDT_ENTRIES(current, DEFAULT_GDT_ENTRIES);
kaf24@1452 262 SET_GDT_ADDRESS(current, DEFAULT_GDT_ADDRESS);
kaf24@1452 263 __asm__ __volatile__("lgdt %0": "=m" (*current->mm.gdt));
kaf24@1452 264 __asm__ __volatile__("lidt %0": "=m" (idt_descr));
kaf24@1452 265
kaf24@1452 266 /* No nested task. */
kaf24@1452 267 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
kaf24@1452 268
kaf24@1452 269 /* Ensure FPU gets initialised for each domain. */
kaf24@1452 270 stts();
kaf24@1452 271
kaf24@1452 272 /* Set up and load the per-CPU TSS and LDT. */
kaf24@1452 273 t->ss0 = __HYPERVISOR_DS;
kaf24@1452 274 t->esp0 = get_stack_top();
kaf24@1452 275 set_tss_desc(nr,t);
kaf24@1452 276 load_TR(nr);
kaf24@1452 277 __asm__ __volatile__("lldt %%ax"::"a" (0));
kaf24@1452 278
kaf24@1452 279 /* Clear all 6 debug registers. */
kaf24@1452 280 #define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
kaf24@1452 281 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
kaf24@1452 282 #undef CD
kaf24@1452 283
kaf24@1452 284 /* Install correct page table. */
kaf24@1452 285 write_ptbase(&current->mm);
kaf24@1452 286
kaf24@1452 287 init_idle_task();
kaf24@1452 288 }
kaf24@1452 289
kaf24@1452 290 static void __init do_initcalls(void)
kaf24@1452 291 {
kaf24@1452 292 initcall_t *call;
kaf24@1452 293 for ( call = &__initcall_start; call < &__initcall_end; call++ )
kaf24@1452 294 (*call)();
kaf24@1452 295 }
kaf24@1452 296
kaf24@1452 297 /*
kaf24@1452 298 * IBM-compatible BIOSes place drive info tables at initial interrupt
kaf24@1452 299 * vectors 0x41 and 0x46. These are in the for of 16-bit-mode far ptrs.
kaf24@1452 300 */
kaf24@1452 301 struct drive_info_struct { unsigned char dummy[32]; } drive_info;
kaf24@1452 302 void get_bios_driveinfo(void)
kaf24@1452 303 {
kaf24@1452 304 unsigned long seg, off, tab1, tab2;
kaf24@1452 305
kaf24@1452 306 off = (unsigned long)*(unsigned short *)(4*0x41+0);
kaf24@1452 307 seg = (unsigned long)*(unsigned short *)(4*0x41+2);
kaf24@1452 308 tab1 = (seg<<4) + off;
kaf24@1452 309
kaf24@1452 310 off = (unsigned long)*(unsigned short *)(4*0x46+0);
kaf24@1452 311 seg = (unsigned long)*(unsigned short *)(4*0x46+2);
kaf24@1452 312 tab2 = (seg<<4) + off;
kaf24@1452 313
kaf24@1452 314 printk("Reading BIOS drive-info tables at 0x%05lx and 0x%05lx\n",
kaf24@1452 315 tab1, tab2);
kaf24@1452 316
kaf24@1452 317 memcpy(drive_info.dummy+ 0, (char *)tab1, 16);
kaf24@1452 318 memcpy(drive_info.dummy+16, (char *)tab2, 16);
kaf24@1452 319 }
kaf24@1452 320
kaf24@1452 321
kaf24@1452 322 unsigned long pci_mem_start = 0x10000000;
kaf24@1452 323
kaf24@1452 324 void __init start_of_day(void)
kaf24@1452 325 {
kaf24@1452 326 extern void trap_init(void);
kaf24@1452 327 extern void init_IRQ(void);
kaf24@1452 328 extern void time_init(void);
kaf24@1452 329 extern void timer_bh(void);
kaf24@1452 330 extern void init_timervecs(void);
kaf24@1452 331 extern void ac_timer_init(void);
kaf24@1452 332 extern void initialize_keytable();
kaf24@1452 333 extern void initialize_keyboard(void);
kaf24@1452 334 extern int opt_nosmp, opt_watchdog, opt_noacpi, opt_ignorebiostables;
kaf24@1452 335 extern int do_timer_lists_from_pit;
kaf24@1452 336 unsigned long low_mem_size;
kaf24@1452 337
kaf24@1452 338 #ifdef MEMORY_GUARD
kaf24@1452 339 /* Unmap the first page of CPU0's stack. */
kaf24@1452 340 extern unsigned long cpu0_stack[];
kaf24@1452 341 memguard_guard_range(cpu0_stack, PAGE_SIZE);
kaf24@1452 342 #endif
kaf24@1452 343
kaf24@1452 344 open_softirq(NEW_TLBFLUSH_CLOCK_PERIOD_SOFTIRQ,
kaf24@1452 345 (void *)new_tlbflush_clock_period,
kaf24@1452 346 NULL);
kaf24@1452 347
kaf24@1452 348 if ( opt_watchdog )
kaf24@1452 349 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 350
kaf24@1452 351 /*
kaf24@1452 352 * We do this early, but tables are in the lowest 1MB (usually
kaf24@1452 353 * 0xfe000-0xfffff). Therefore they're unlikely to ever get clobbered.
kaf24@1452 354 */
kaf24@1452 355 get_bios_driveinfo();
kaf24@1452 356
kaf24@1452 357 /* Tell the PCI layer not to allocate too close to the RAM area.. */
kaf24@1452 358 low_mem_size = ((max_page << PAGE_SHIFT) + 0xfffff) & ~0xfffff;
kaf24@1452 359 if ( low_mem_size > pci_mem_start ) pci_mem_start = low_mem_size;
kaf24@1452 360
kaf24@1452 361 identify_cpu(&boot_cpu_data); /* get CPU type info */
kaf24@1452 362 if ( cpu_has_fxsr ) set_in_cr4(X86_CR4_OSFXSR);
kaf24@1452 363 if ( cpu_has_xmm ) set_in_cr4(X86_CR4_OSXMMEXCPT);
kaf24@1452 364 #ifdef CONFIG_SMP
kaf24@1452 365 if ( opt_ignorebiostables )
kaf24@1452 366 {
kaf24@1452 367 opt_nosmp = 1; /* No SMP without configuration */
kaf24@1452 368 opt_noacpi = 1; /* ACPI will just confuse matters also */
kaf24@1452 369 }
kaf24@1452 370 else
kaf24@1452 371 {
kaf24@1452 372 find_smp_config();
kaf24@1452 373 smp_alloc_memory(); /* trampoline which other CPUs jump at */
kaf24@1452 374 }
kaf24@1452 375 #endif
kaf24@1452 376 paging_init(); /* not much here now, but sets up fixmap */
kaf24@1452 377 if ( !opt_noacpi )
kaf24@1452 378 acpi_boot_init();
kaf24@1452 379 #ifdef CONFIG_SMP
kaf24@1452 380 if ( smp_found_config )
kaf24@1452 381 get_smp_config();
kaf24@1452 382 #endif
kaf24@1452 383 domain_init();
kaf24@1452 384 scheduler_init();
kaf24@1452 385 trap_init();
kaf24@1452 386 init_IRQ(); /* installs simple interrupt wrappers. Starts HZ clock. */
kaf24@1452 387 time_init(); /* installs software handler for HZ clock. */
kaf24@1452 388 softirq_init();
kaf24@1452 389 init_timervecs();
kaf24@1452 390 init_bh(TIMER_BH, timer_bh);
kaf24@1452 391 init_apic_mappings(); /* make APICs addressable in our pagetables. */
kaf24@1452 392
kaf24@1452 393 #ifndef CONFIG_SMP
kaf24@1452 394 APIC_init_uniprocessor();
kaf24@1452 395 #else
kaf24@1452 396 if ( opt_nosmp )
kaf24@1452 397 APIC_init_uniprocessor();
kaf24@1452 398 else
kaf24@1452 399 smp_boot_cpus();
kaf24@1452 400 /*
kaf24@1452 401 * Does loads of stuff, including kicking the local
kaf24@1452 402 * APIC, and the IO APIC after other CPUs are booted.
kaf24@1452 403 * Each IRQ is preferably handled by IO-APIC, but
kaf24@1452 404 * fall thru to 8259A if we have to (but slower).
kaf24@1452 405 */
kaf24@1452 406 #endif
kaf24@1452 407
kaf24@1452 408 __sti();
kaf24@1452 409
kaf24@1452 410 initialize_keytable(); /* call back handling for key codes */
kaf24@1452 411
kaf24@1452 412 serial_init_stage2();
kaf24@1452 413 initialize_keyboard(); /* setup keyboard (also for debugging) */
kaf24@1452 414
kaf24@1452 415 #ifdef XEN_DEBUGGER
kaf24@1452 416 initialize_pdb(); /* pervasive debugger */
kaf24@1452 417 #endif
kaf24@1452 418
kaf24@1452 419 if ( !cpu_has_apic )
kaf24@1452 420 {
kaf24@1452 421 do_timer_lists_from_pit = 1;
kaf24@1452 422 if ( smp_num_cpus != 1 )
kaf24@1452 423 panic("We need local APICs on SMP machines!");
kaf24@1452 424 }
kaf24@1452 425
kaf24@1452 426 ac_timer_init(); /* init accurate timers */
kaf24@1452 427 init_xen_time(); /* initialise the time */
kaf24@1452 428 schedulers_start(); /* start scheduler for each CPU */
kaf24@1452 429
kaf24@1452 430 check_nmi_watchdog();
kaf24@1452 431
kaf24@1452 432 #ifdef CONFIG_PCI
kaf24@1452 433 pci_init();
kaf24@1452 434 #endif
kaf24@1452 435 do_initcalls();
kaf24@1452 436
kaf24@1452 437 #ifdef CONFIG_SMP
kaf24@1452 438 wait_init_idle = cpu_online_map;
kaf24@1452 439 clear_bit(smp_processor_id(), &wait_init_idle);
kaf24@1452 440 smp_threads_ready = 1;
kaf24@1452 441 smp_commence(); /* Tell other CPUs that state of the world is stable. */
kaf24@1452 442 while (wait_init_idle)
kaf24@1452 443 {
kaf24@1452 444 cpu_relax();
kaf24@1452 445 barrier();
kaf24@1452 446 }
kaf24@1452 447 #endif
kaf24@1452 448
kaf24@1452 449 watchdog_on = 1;
kaf24@1452 450 }