ia64/xen-unstable

annotate xen/include/asm-x86/debugreg.h @ 15812:86a154e1ef5d

[HVM] Shadow: don't shadow the p2m table.
For HVM vcpus with paging disabled, we used to shadow the p2m table,
and skip the p2m lookup to go from gfn to mfn. Instead, we now
provide a simple pagetable that gives a one-to-one mapping of 4GB, and
shadow that, making the translations from gfn to mfn via the p2m.
This removes the paging-disabled special-case code from the shadow
fault handler, and allows us to expand the p2m interface, since all HVM
translations now go through the same p2m lookups.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Fri Aug 31 11:06:22 2007 +0100 (2007-08-31)
parents 92b8e1efa784
children 69b56d3289f5
rev   line source
kaf24@1452 1 #ifndef _X86_DEBUGREG_H
kaf24@1452 2 #define _X86_DEBUGREG_H
kaf24@1452 3
kaf24@1452 4
kaf24@1452 5 /* Indicate the register numbers for a number of the specific
kaf24@1452 6 debug registers. Registers 0-3 contain the addresses we wish to trap on */
kaf24@1452 7 #define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
kaf24@1452 8 #define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
kaf24@1452 9
kaf24@1452 10 #define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
kaf24@1452 11 #define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
kaf24@1452 12
kaf24@1452 13 /* Define a few things for the status register. We can use this to determine
kaf24@1452 14 which debugging register was responsible for the trap. The other bits
kaf24@1452 15 are either reserved or not of interest to us. */
kaf24@1452 16
kaf24@1452 17 #define DR_TRAP0 (0x1) /* db0 */
kaf24@1452 18 #define DR_TRAP1 (0x2) /* db1 */
kaf24@1452 19 #define DR_TRAP2 (0x4) /* db2 */
kaf24@1452 20 #define DR_TRAP3 (0x8) /* db3 */
kaf24@1452 21
kaf24@1452 22 #define DR_STEP (0x4000) /* single-step */
kaf24@1452 23 #define DR_SWITCH (0x8000) /* task switch */
kaf24@1452 24
kaf24@1452 25 /* Now define a bunch of things for manipulating the control register.
kaf24@1452 26 The top two bytes of the control register consist of 4 fields of 4
kaf24@1452 27 bits - each field corresponds to one of the four debug registers,
kaf24@1452 28 and indicates what types of access we trap on, and how large the data
kaf24@1452 29 field is that we are looking at */
kaf24@1452 30
kaf24@1452 31 #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
kaf24@1452 32 #define DR_CONTROL_SIZE 4 /* 4 control bits per register */
kaf24@1452 33
kaf24@1452 34 #define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
kaf24@1452 35 #define DR_RW_WRITE (0x1)
kaf24@1452 36 #define DR_RW_READ (0x3)
kaf24@1452 37
kaf24@1452 38 #define DR_LEN_1 (0x0) /* Settings for data length to trap on */
kaf24@1452 39 #define DR_LEN_2 (0x4)
kaf24@1452 40 #define DR_LEN_4 (0xC)
kaf24@1452 41
kaf24@1452 42 /* The low byte to the control register determine which registers are
kaf24@1452 43 enabled. There are 4 fields of two bits. One bit is "local", meaning
kaf24@1452 44 that the processor will reset the bit after a task switch and the other
kaf24@1452 45 is global meaning that we have to explicitly reset the bit. With linux,
kaf24@1452 46 you can use either one, since we explicitly zero the register when we enter
kaf24@1452 47 kernel mode. */
kaf24@1452 48
kaf24@1452 49 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
kaf24@1452 50 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
kaf24@1452 51 #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
kaf24@1452 52
kaf24@1452 53 #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
kaf24@1452 54 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
kaf24@1452 55
kaf24@1452 56 /* The second byte to the control register has a few special things.
kaf24@1452 57 We can slow the instruction pipeline for instructions coming via the
kaf24@1452 58 gdt or the ldt if we want to. I am not sure why this is an advantage */
kaf24@1452 59
kaf24@1452 60 #define DR_CONTROL_RESERVED (~0xFFFF03FFUL) /* Reserved by Intel */
kaf24@1452 61 #define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
kaf24@1452 62 #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
kaf24@1452 63
kaf24@1452 64 #endif /* _X86_DEBUGREG_H */