ia64/xen-unstable

annotate xen/include/asm-ia64/vmx_vcpu.h @ 9765:7c7bcf173f8b

[IA64] cleanup vtlb code

This patch is to clean up vtlb code.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Tue Apr 25 20:53:38 2006 -0600 (2006-04-25)
parents 1abf3783975d
children 6e979aa0e6d2
rev   line source
adsharma@4993 1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
adsharma@4993 2 /*
adsharma@4993 3 * vmx_vcpu.h:
adsharma@4993 4 * Copyright (c) 2005, Intel Corporation.
adsharma@4993 5 *
adsharma@4993 6 * This program is free software; you can redistribute it and/or modify it
adsharma@4993 7 * under the terms and conditions of the GNU General Public License,
adsharma@4993 8 * version 2, as published by the Free Software Foundation.
adsharma@4993 9 *
adsharma@4993 10 * This program is distributed in the hope it will be useful, but WITHOUT
adsharma@4993 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
adsharma@4993 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
adsharma@4993 13 * more details.
adsharma@4993 14 *
adsharma@4993 15 * You should have received a copy of the GNU General Public License along with
adsharma@4993 16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
adsharma@4993 17 * Place - Suite 330, Boston, MA 02111-1307 USA.
adsharma@4993 18 *
adsharma@4993 19 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
adsharma@4993 20 * Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
adsharma@4993 21 */
adsharma@4993 22
adsharma@4993 23 #ifndef _XEN_IA64_VMX_VCPU_H
adsharma@4993 24 #define _XEN_IA64_VMX_VCPU_H
adsharma@4993 25
adsharma@4993 26
adsharma@4993 27 #include <xen/sched.h>
adsharma@4993 28 #include <asm/ia64_int.h>
adsharma@4993 29 #include <asm/vmx_vpd.h>
adsharma@4993 30 #include <asm/ptrace.h>
adsharma@4993 31 #include <asm/regs.h>
adsharma@4993 32 #include <asm/regionreg.h>
adsharma@4993 33 #include <asm/types.h>
adsharma@4993 34 #include <asm/vcpu.h>
adsharma@4993 35
adsharma@4993 36 #define VRN_SHIFT 61
adsharma@4993 37 #define VRN0 0x0UL
adsharma@4993 38 #define VRN1 0x1UL
adsharma@4993 39 #define VRN2 0x2UL
adsharma@4993 40 #define VRN3 0x3UL
adsharma@4993 41 #define VRN4 0x4UL
adsharma@4993 42 #define VRN5 0x5UL
adsharma@4993 43 #define VRN6 0x6UL
adsharma@4993 44 #define VRN7 0x7UL
djm@6801 45 // for vlsapic
djm@6801 46 #define VLSAPIC_INSVC(vcpu, i) ((vcpu)->arch.insvc[i])
djm@6801 47 //#define VMX_VPD(x,y) ((x)->arch.arch_vmx.vpd->y)
adsharma@4993 48
adsharma@4993 49 #define VMX(x,y) ((x)->arch.arch_vmx.y)
adsharma@4993 50
adsharma@4993 51
adsharma@4993 52 #define VMM_RR_SHIFT 20
adsharma@4993 53 #define VMM_RR_MASK ((1UL<<VMM_RR_SHIFT)-1)
awilliam@8917 54
adsharma@4993 55 extern u64 indirect_reg_igfld_MASK ( int type, int index, u64 value);
adsharma@4993 56 extern u64 cr_igfld_mask (int index, u64 value);
adsharma@4993 57 extern int check_indirect_reg_rsv_fields ( int type, int index, u64 value );
adsharma@4993 58 extern u64 set_isr_ei_ni (VCPU *vcpu);
adsharma@4993 59 extern u64 set_isr_for_na_inst(VCPU *vcpu, int op);
adsharma@4993 60
adsharma@4993 61
djm@6878 62 /* next all for VTI domain APIs definition */
adsharma@4993 63 extern void vmx_vcpu_set_psr(VCPU *vcpu, unsigned long value);
adsharma@4993 64 extern UINT64 vmx_vcpu_sync_mpsr(UINT64 mipsr, UINT64 value);
adsharma@4993 65 extern void vmx_vcpu_set_psr_sync_mpsr(VCPU * vcpu, UINT64 value);
adsharma@4993 66 extern IA64FAULT vmx_vcpu_cover(VCPU *vcpu);
adsharma@4993 67 extern IA64FAULT vmx_vcpu_set_rr(VCPU *vcpu, UINT64 reg, UINT64 val);
adsharma@4993 68 extern IA64FAULT vmx_vcpu_get_pkr(VCPU *vcpu, UINT64 reg, UINT64 *pval);
adsharma@4993 69 IA64FAULT vmx_vcpu_set_pkr(VCPU *vcpu, UINT64 reg, UINT64 val);
adsharma@4993 70 extern IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa);
adsharma@4993 71 extern IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa);
awilliam@9164 72 extern IA64FAULT vmx_vcpu_itr_i(VCPU *vcpu, UINT64 slot, UINT64 pte, UINT64 itir, UINT64 ifa);
awilliam@9164 73 extern IA64FAULT vmx_vcpu_itr_d(VCPU *vcpu, UINT64 slot, UINT64 pte, UINT64 itir, UINT64 ifa);
adsharma@4993 74 extern IA64FAULT vmx_vcpu_ptr_d(VCPU *vcpu,UINT64 vadr,UINT64 ps);
adsharma@4993 75 extern IA64FAULT vmx_vcpu_ptr_i(VCPU *vcpu,UINT64 vadr,UINT64 ps);
adsharma@4993 76 extern IA64FAULT vmx_vcpu_ptc_l(VCPU *vcpu, UINT64 vadr, UINT64 ps);
adsharma@4993 77 extern IA64FAULT vmx_vcpu_ptc_e(VCPU *vcpu, UINT64 vadr);
adsharma@4993 78 extern IA64FAULT vmx_vcpu_ptc_g(VCPU *vcpu, UINT64 vadr, UINT64 ps);
adsharma@4993 79 extern IA64FAULT vmx_vcpu_ptc_ga(VCPU *vcpu,UINT64 vadr,UINT64 ps);
adsharma@4993 80 extern IA64FAULT vmx_vcpu_thash(VCPU *vcpu, UINT64 vadr, UINT64 *pval);
adsharma@4993 81 extern u64 vmx_vcpu_get_itir_on_fault(VCPU *vcpu, u64 ifa);
adsharma@4993 82 extern IA64FAULT vmx_vcpu_ttag(VCPU *vcpu, UINT64 vadr, UINT64 *pval);
adsharma@4993 83 extern IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, UINT64 vadr, UINT64 *padr);
adsharma@4993 84 extern IA64FAULT vmx_vcpu_tak(VCPU *vcpu, UINT64 vadr, UINT64 *key);
adsharma@4993 85 extern IA64FAULT vmx_vcpu_rfi(VCPU *vcpu);
adsharma@4993 86 extern UINT64 vmx_vcpu_get_psr(VCPU *vcpu);
adsharma@4993 87 extern IA64FAULT vmx_vcpu_get_bgr(VCPU *vcpu, unsigned int reg, UINT64 *val);
adsharma@4993 88 extern IA64FAULT vmx_vcpu_set_bgr(VCPU *vcpu, unsigned int reg, u64 val,int nat);
djm@6867 89 #if 0
adsharma@4993 90 extern IA64FAULT vmx_vcpu_get_gr(VCPU *vcpu, unsigned reg, UINT64 * val);
adsharma@4993 91 extern IA64FAULT vmx_vcpu_set_gr(VCPU *vcpu, unsigned reg, u64 value, int nat);
djm@6867 92 #endif
adsharma@4993 93 extern IA64FAULT vmx_vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm24);
adsharma@4993 94 extern IA64FAULT vmx_vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24);
adsharma@4993 95 extern IA64FAULT vmx_vcpu_set_psr_l(VCPU *vcpu, UINT64 val);
adsharma@4993 96 extern void vtm_init(VCPU *vcpu);
adsharma@4993 97 extern uint64_t vtm_get_itc(VCPU *vcpu);
adsharma@4993 98 extern void vtm_set_itc(VCPU *vcpu, uint64_t new_itc);
awilliam@9157 99 extern void vtm_set_itv(VCPU *vcpu, uint64_t val);
awilliam@9157 100 extern void vtm_set_itm(VCPU *vcpu, uint64_t val);
adsharma@4993 101 extern void vtm_interruption_update(VCPU *vcpu, vtime_t* vtm);
awilliam@9157 102 //extern void vtm_domain_out(VCPU *vcpu);
awilliam@9157 103 //extern void vtm_domain_in(VCPU *vcpu);
adsharma@4993 104 extern void vlsapic_reset(VCPU *vcpu);
adsharma@4993 105 extern int vmx_check_pending_irq(VCPU *vcpu);
adsharma@4993 106 extern void guest_write_eoi(VCPU *vcpu);
adsharma@4993 107 extern uint64_t guest_read_vivr(VCPU *vcpu);
adsharma@4993 108 extern void vmx_inject_vhpi(VCPU *vcpu, u8 vec);
kaf24@8386 109 extern int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector);
kaf24@8708 110 extern struct virtual_platform_def *vmx_vcpu_get_plat(VCPU *vcpu);
djm@5797 111 extern void memread_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
djm@5797 112 extern void memread_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s);
djm@5797 113 extern void memwrite_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s);
djm@5797 114 extern void memwrite_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
awilliam@8917 115 extern void vcpu_load_kernel_regs(VCPU *vcpu);
awilliam@8917 116 extern IA64FAULT vmx_vcpu_increment_iip(VCPU *vcpu);
awilliam@8917 117 extern void vmx_switch_rr7(unsigned long ,shared_info_t*,void *,void *,void *);
awilliam@9012 118
awilliam@9012 119 extern void dtlb_fault (VCPU *vcpu, u64 vadr);
awilliam@9012 120 extern void nested_dtlb (VCPU *vcpu);
awilliam@9012 121 extern void alt_dtlb (VCPU *vcpu, u64 vadr);
awilliam@9012 122 extern void dvhpt_fault (VCPU *vcpu, u64 vadr);
awilliam@9012 123 extern void dnat_page_consumption (VCPU *vcpu, uint64_t vadr);
awilliam@9012 124 extern void page_not_present(VCPU *vcpu, u64 vadr);
awilliam@9012 125
adsharma@4993 126 /**************************************************************************
adsharma@4993 127 VCPU control register access routines
adsharma@4993 128 **************************************************************************/
adsharma@4993 129
adsharma@4993 130 static inline
adsharma@4993 131 IA64FAULT vmx_vcpu_get_dcr(VCPU *vcpu, UINT64 *pval)
adsharma@4993 132 {
djm@6801 133 *pval = VCPU(vcpu,dcr);
adsharma@4993 134 return (IA64_NO_FAULT);
adsharma@4993 135 }
adsharma@4993 136
adsharma@4993 137 static inline
adsharma@4993 138 IA64FAULT vmx_vcpu_get_itm(VCPU *vcpu, UINT64 *pval)
adsharma@4993 139 {
djm@6801 140 *pval = VCPU(vcpu,itm);
adsharma@4993 141 return (IA64_NO_FAULT);
adsharma@4993 142 }
adsharma@4993 143
adsharma@4993 144 static inline
adsharma@4993 145 IA64FAULT vmx_vcpu_get_iva(VCPU *vcpu, UINT64 *pval)
adsharma@4993 146 {
djm@6801 147 *pval = VCPU(vcpu,iva);
adsharma@4993 148 return (IA64_NO_FAULT);
adsharma@4993 149 }
adsharma@4993 150 static inline
adsharma@4993 151 IA64FAULT vmx_vcpu_get_pta(VCPU *vcpu, UINT64 *pval)
adsharma@4993 152 {
djm@6801 153 *pval = VCPU(vcpu,pta);
adsharma@4993 154 return (IA64_NO_FAULT);
adsharma@4993 155 }
adsharma@4993 156
adsharma@4993 157 static inline
adsharma@4993 158 IA64FAULT vmx_vcpu_get_lid(VCPU *vcpu, UINT64 *pval)
adsharma@4993 159 {
djm@6801 160 *pval = VCPU(vcpu,lid);
adsharma@4993 161 return (IA64_NO_FAULT);
adsharma@4993 162 }
adsharma@4993 163 static inline
adsharma@4993 164 IA64FAULT vmx_vcpu_get_ivr(VCPU *vcpu, UINT64 *pval)
adsharma@4993 165 {
adsharma@4993 166 *pval = guest_read_vivr(vcpu);
adsharma@4993 167 return (IA64_NO_FAULT);
adsharma@4993 168 }
adsharma@4993 169 static inline
adsharma@4993 170 IA64FAULT vmx_vcpu_get_tpr(VCPU *vcpu, UINT64 *pval)
adsharma@4993 171 {
djm@6801 172 *pval = VCPU(vcpu,tpr);
adsharma@4993 173 return (IA64_NO_FAULT);
adsharma@4993 174 }
adsharma@4993 175 static inline
adsharma@4993 176 IA64FAULT vmx_vcpu_get_eoi(VCPU *vcpu, UINT64 *pval)
adsharma@4993 177 {
adsharma@4993 178 *pval = 0L; // reads of eoi always return 0
adsharma@4993 179 return (IA64_NO_FAULT);
adsharma@4993 180 }
adsharma@4993 181 static inline
adsharma@4993 182 IA64FAULT vmx_vcpu_get_irr0(VCPU *vcpu, UINT64 *pval)
adsharma@4993 183 {
djm@6801 184 *pval = VCPU(vcpu,irr[0]);
adsharma@4993 185 return (IA64_NO_FAULT);
adsharma@4993 186 }
adsharma@4993 187 static inline
adsharma@4993 188 IA64FAULT vmx_vcpu_get_irr1(VCPU *vcpu, UINT64 *pval)
adsharma@4993 189 {
djm@6801 190 *pval = VCPU(vcpu,irr[1]);
adsharma@4993 191 return (IA64_NO_FAULT);
adsharma@4993 192 }
adsharma@4993 193 static inline
adsharma@4993 194 IA64FAULT vmx_vcpu_get_irr2(VCPU *vcpu, UINT64 *pval)
adsharma@4993 195 {
djm@6801 196 *pval = VCPU(vcpu,irr[2]);
adsharma@4993 197 return (IA64_NO_FAULT);
adsharma@4993 198 }
adsharma@4993 199 static inline
adsharma@4993 200 IA64FAULT vmx_vcpu_get_irr3(VCPU *vcpu, UINT64 *pval)
adsharma@4993 201 {
djm@6801 202 *pval = VCPU(vcpu,irr[3]);
adsharma@4993 203 return (IA64_NO_FAULT);
adsharma@4993 204 }
adsharma@4993 205 static inline
adsharma@4993 206 IA64FAULT vmx_vcpu_get_itv(VCPU *vcpu, UINT64 *pval)
adsharma@4993 207 {
djm@6801 208 *pval = VCPU(vcpu,itv);
adsharma@4993 209 return (IA64_NO_FAULT);
adsharma@4993 210 }
adsharma@4993 211 static inline
adsharma@4993 212 IA64FAULT vmx_vcpu_get_pmv(VCPU *vcpu, UINT64 *pval)
adsharma@4993 213 {
djm@6801 214 *pval = VCPU(vcpu,pmv);
adsharma@4993 215 return (IA64_NO_FAULT);
adsharma@4993 216 }
adsharma@4993 217 static inline
adsharma@4993 218 IA64FAULT vmx_vcpu_get_cmcv(VCPU *vcpu, UINT64 *pval)
adsharma@4993 219 {
djm@6801 220 *pval = VCPU(vcpu,cmcv);
adsharma@4993 221 return (IA64_NO_FAULT);
adsharma@4993 222 }
adsharma@4993 223 static inline
adsharma@4993 224 IA64FAULT vmx_vcpu_get_lrr0(VCPU *vcpu, UINT64 *pval)
adsharma@4993 225 {
djm@6801 226 *pval = VCPU(vcpu,lrr0);
adsharma@4993 227 return (IA64_NO_FAULT);
adsharma@4993 228 }
adsharma@4993 229 static inline
adsharma@4993 230 IA64FAULT vmx_vcpu_get_lrr1(VCPU *vcpu, UINT64 *pval)
djm@6801 231 { *pval = VCPU(vcpu,lrr1);
adsharma@4993 232 return (IA64_NO_FAULT);
adsharma@4993 233 }
adsharma@4993 234 static inline
adsharma@4993 235 IA64FAULT
adsharma@4993 236 vmx_vcpu_set_dcr(VCPU *vcpu, u64 val)
adsharma@4993 237 {
adsharma@4993 238 u64 mdcr, mask;
djm@6801 239 VCPU(vcpu,dcr)=val;
adsharma@4993 240 /* All vDCR bits will go to mDCR, except for be/pp bit */
adsharma@4993 241 mdcr = ia64_get_dcr();
adsharma@4993 242 mask = IA64_DCR_BE | IA64_DCR_PP;
adsharma@4993 243 mdcr = ( mdcr & mask ) | ( val & (~mask) );
adsharma@4993 244 ia64_set_dcr( mdcr);
adsharma@4993 245
adsharma@4993 246 return IA64_NO_FAULT;
adsharma@4993 247 }
adsharma@4993 248
adsharma@4993 249 static inline
adsharma@4993 250 IA64FAULT
adsharma@4993 251 vmx_vcpu_set_itm(VCPU *vcpu, u64 val)
adsharma@4993 252 {
awilliam@9157 253 vtm_set_itm(vcpu, val);
adsharma@4993 254 return IA64_NO_FAULT;
adsharma@4993 255 }
adsharma@4993 256 static inline
adsharma@4993 257 IA64FAULT
adsharma@4993 258 vmx_vcpu_set_iva(VCPU *vcpu, u64 val)
adsharma@4993 259 {
djm@6801 260 VCPU(vcpu,iva)=val;
adsharma@4993 261 return IA64_NO_FAULT;
adsharma@4993 262 }
adsharma@4993 263
adsharma@4993 264 static inline
adsharma@4993 265 IA64FAULT
adsharma@4993 266 vmx_vcpu_set_pta(VCPU *vcpu, u64 val)
adsharma@4993 267 {
djm@6801 268 VCPU(vcpu,pta)=val;
adsharma@4993 269 return IA64_NO_FAULT;
adsharma@4993 270 }
adsharma@4993 271
adsharma@4993 272 static inline
adsharma@4993 273 IA64FAULT
adsharma@4993 274 vmx_vcpu_set_lid(VCPU *vcpu, u64 val)
adsharma@4993 275 {
djm@6801 276 VCPU(vcpu,lid)=val;
adsharma@4993 277 return IA64_NO_FAULT;
adsharma@4993 278 }
djm@5797 279 extern IA64FAULT vmx_vcpu_set_tpr(VCPU *vcpu, u64 val);
djm@5797 280
adsharma@4993 281 static inline
adsharma@4993 282 IA64FAULT
adsharma@4993 283 vmx_vcpu_set_eoi(VCPU *vcpu, u64 val)
adsharma@4993 284 {
adsharma@4993 285 guest_write_eoi(vcpu);
adsharma@4993 286 return IA64_NO_FAULT;
adsharma@4993 287 }
adsharma@4993 288
adsharma@4993 289 static inline
adsharma@4993 290 IA64FAULT
adsharma@4993 291 vmx_vcpu_set_itv(VCPU *vcpu, u64 val)
adsharma@4993 292 {
adsharma@4993 293
awilliam@9157 294 vtm_set_itv(vcpu, val);
adsharma@4993 295 return IA64_NO_FAULT;
adsharma@4993 296 }
adsharma@4993 297 static inline
adsharma@4993 298 IA64FAULT
adsharma@4993 299 vmx_vcpu_set_pmv(VCPU *vcpu, u64 val)
adsharma@4993 300 {
djm@6801 301 VCPU(vcpu,pmv)=val;
adsharma@4993 302 return IA64_NO_FAULT;
adsharma@4993 303 }
adsharma@4993 304 static inline
adsharma@4993 305 IA64FAULT
adsharma@4993 306 vmx_vcpu_set_cmcv(VCPU *vcpu, u64 val)
adsharma@4993 307 {
djm@6801 308 VCPU(vcpu,cmcv)=val;
adsharma@4993 309 return IA64_NO_FAULT;
adsharma@4993 310 }
adsharma@4993 311 static inline
adsharma@4993 312 IA64FAULT
adsharma@4993 313 vmx_vcpu_set_lrr0(VCPU *vcpu, u64 val)
adsharma@4993 314 {
djm@6801 315 VCPU(vcpu,lrr0)=val;
adsharma@4993 316 return IA64_NO_FAULT;
adsharma@4993 317 }
adsharma@4993 318 static inline
adsharma@4993 319 IA64FAULT
adsharma@4993 320 vmx_vcpu_set_lrr1(VCPU *vcpu, u64 val)
adsharma@4993 321 {
djm@6801 322 VCPU(vcpu,lrr1)=val;
adsharma@4993 323 return IA64_NO_FAULT;
adsharma@4993 324 }
adsharma@4993 325
adsharma@4993 326
adsharma@4993 327
adsharma@4993 328
adsharma@4993 329 /**************************************************************************
adsharma@4993 330 VCPU privileged application register access routines
adsharma@4993 331 **************************************************************************/
adsharma@4993 332 static inline
adsharma@4993 333 IA64FAULT vmx_vcpu_set_itc(VCPU *vcpu, UINT64 val)
adsharma@4993 334 {
adsharma@4993 335 vtm_set_itc(vcpu, val);
adsharma@4993 336 return IA64_NO_FAULT;
adsharma@4993 337 }
adsharma@4993 338 static inline
adsharma@4993 339 IA64FAULT vmx_vcpu_get_itc(VCPU *vcpu,UINT64 *val)
adsharma@4993 340 {
adsharma@4993 341 *val = vtm_get_itc(vcpu);
adsharma@4993 342 return IA64_NO_FAULT;
adsharma@4993 343 }
awilliam@9164 344 /*
adsharma@4993 345 static inline
adsharma@4993 346 IA64FAULT vmx_vcpu_get_rr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
adsharma@4993 347 {
adsharma@4993 348 *pval = VMX(vcpu,vrr[reg>>61]);
adsharma@4993 349 return (IA64_NO_FAULT);
adsharma@4993 350 }
awilliam@9164 351 */
adsharma@4993 352 /**************************************************************************
adsharma@4993 353 VCPU debug breakpoint register access routines
adsharma@4993 354 **************************************************************************/
adsharma@4993 355
adsharma@4993 356 static inline
adsharma@4993 357 IA64FAULT vmx_vcpu_get_cpuid(VCPU *vcpu, UINT64 reg, UINT64 *pval)
adsharma@4993 358 {
adsharma@4993 359 // TODO: unimplemented DBRs return a reserved register fault
adsharma@4993 360 // TODO: Should set Logical CPU state, not just physical
adsharma@4993 361 if(reg > 4){
adsharma@4993 362 panic("there are only five cpuid registers");
adsharma@4993 363 }
djm@6801 364 *pval=VCPU(vcpu,vcpuid[reg]);
adsharma@4993 365 return (IA64_NO_FAULT);
adsharma@4993 366 }
adsharma@4993 367
adsharma@4993 368
adsharma@4993 369 static inline
adsharma@4993 370 IA64FAULT vmx_vcpu_set_dbr(VCPU *vcpu, UINT64 reg, UINT64 val)
adsharma@4993 371 {
adsharma@4993 372 // TODO: unimplemented DBRs return a reserved register fault
adsharma@4993 373 // TODO: Should set Logical CPU state, not just physical
adsharma@4993 374 ia64_set_dbr(reg,val);
adsharma@4993 375 return (IA64_NO_FAULT);
adsharma@4993 376 }
adsharma@4993 377 static inline
adsharma@4993 378 IA64FAULT vmx_vcpu_set_ibr(VCPU *vcpu, UINT64 reg, UINT64 val)
adsharma@4993 379 {
adsharma@4993 380 // TODO: unimplemented IBRs return a reserved register fault
adsharma@4993 381 // TODO: Should set Logical CPU state, not just physical
adsharma@4993 382 ia64_set_ibr(reg,val);
adsharma@4993 383 return (IA64_NO_FAULT);
adsharma@4993 384 }
adsharma@4993 385 static inline
adsharma@4993 386 IA64FAULT vmx_vcpu_get_dbr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
adsharma@4993 387 {
adsharma@4993 388 // TODO: unimplemented DBRs return a reserved register fault
adsharma@4993 389 UINT64 val = ia64_get_dbr(reg);
adsharma@4993 390 *pval = val;
adsharma@4993 391 return (IA64_NO_FAULT);
adsharma@4993 392 }
adsharma@4993 393 static inline
adsharma@4993 394 IA64FAULT vmx_vcpu_get_ibr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
adsharma@4993 395 {
adsharma@4993 396 // TODO: unimplemented IBRs return a reserved register fault
adsharma@4993 397 UINT64 val = ia64_get_ibr(reg);
adsharma@4993 398 *pval = val;
adsharma@4993 399 return (IA64_NO_FAULT);
adsharma@4993 400 }
adsharma@4993 401
adsharma@4993 402 /**************************************************************************
adsharma@4993 403 VCPU performance monitor register access routines
adsharma@4993 404 **************************************************************************/
adsharma@4993 405 static inline
adsharma@4993 406 IA64FAULT vmx_vcpu_set_pmc(VCPU *vcpu, UINT64 reg, UINT64 val)
adsharma@4993 407 {
adsharma@4993 408 // TODO: Should set Logical CPU state, not just physical
adsharma@4993 409 // NOTE: Writes to unimplemented PMC registers are discarded
adsharma@4993 410 ia64_set_pmc(reg,val);
adsharma@4993 411 return (IA64_NO_FAULT);
adsharma@4993 412 }
adsharma@4993 413 static inline
adsharma@4993 414 IA64FAULT vmx_vcpu_set_pmd(VCPU *vcpu, UINT64 reg, UINT64 val)
adsharma@4993 415 {
adsharma@4993 416 // TODO: Should set Logical CPU state, not just physical
adsharma@4993 417 // NOTE: Writes to unimplemented PMD registers are discarded
adsharma@4993 418 ia64_set_pmd(reg,val);
adsharma@4993 419 return (IA64_NO_FAULT);
adsharma@4993 420 }
adsharma@4993 421 static inline
adsharma@4993 422 IA64FAULT vmx_vcpu_get_pmc(VCPU *vcpu, UINT64 reg, UINT64 *pval)
adsharma@4993 423 {
adsharma@4993 424 // NOTE: Reads from unimplemented PMC registers return zero
adsharma@4993 425 UINT64 val = (UINT64)ia64_get_pmc(reg);
adsharma@4993 426 *pval = val;
adsharma@4993 427 return (IA64_NO_FAULT);
adsharma@4993 428 }
adsharma@4993 429 static inline
adsharma@4993 430 IA64FAULT vmx_vcpu_get_pmd(VCPU *vcpu, UINT64 reg, UINT64 *pval)
adsharma@4993 431 {
adsharma@4993 432 // NOTE: Reads from unimplemented PMD registers return zero
adsharma@4993 433 UINT64 val = (UINT64)ia64_get_pmd(reg);
adsharma@4993 434 *pval = val;
adsharma@4993 435 return (IA64_NO_FAULT);
adsharma@4993 436 }
adsharma@4993 437
adsharma@4993 438 /**************************************************************************
adsharma@4993 439 VCPU banked general register access routines
adsharma@4993 440 **************************************************************************/
djm@6867 441 #if 0
adsharma@4993 442 static inline
adsharma@4993 443 IA64FAULT vmx_vcpu_bsw0(VCPU *vcpu)
adsharma@4993 444 {
adsharma@4993 445
djm@6801 446 VCPU(vcpu,vpsr) &= ~IA64_PSR_BN;
adsharma@4993 447 return (IA64_NO_FAULT);
adsharma@4993 448 }
adsharma@4993 449 static inline
adsharma@4993 450 IA64FAULT vmx_vcpu_bsw1(VCPU *vcpu)
adsharma@4993 451 {
adsharma@4993 452
djm@6801 453 VCPU(vcpu,vpsr) |= IA64_PSR_BN;
adsharma@4993 454 return (IA64_NO_FAULT);
adsharma@4993 455 }
djm@6867 456 #endif
djm@6469 457 #if 0
fred@5986 458 /* Another hash performance algorithm */
adsharma@4993 459 #define redistribute_rid(rid) (((rid) & ~0xffff) | (((rid) << 8) & 0xff00) | (((rid) >> 8) & 0xff))
djm@6469 460 #endif
adsharma@4993 461 static inline unsigned long
awilliam@9765 462 vrrtomrr(VCPU *v, unsigned long val)
adsharma@4993 463 {
adsharma@4993 464 ia64_rr rr;
fred@5986 465
adsharma@4993 466 rr.rrval=val;
djm@6469 467 rr.rid = rr.rid + v->arch.starting_rid;
awilliam@9011 468 rr.ps = PAGE_SHIFT;
djm@6469 469 rr.ve = 1;
djm@6469 470 return vmMangleRID(rr.rrval);
fred@5986 471 /* Disable this rid allocation algorithm for now */
fred@5986 472 #if 0
adsharma@5086 473 rid=(((u64)vcpu->domain->domain_id)<<DOMAIN_RID_SHIFT) + rr.rid;
adsharma@4993 474 rr.rid = redistribute_rid(rid);
fred@5986 475 #endif
fred@5986 476
adsharma@4993 477 }
awilliam@9765 478 static inline thash_cb_t *
awilliam@9765 479 vmx_vcpu_get_vtlb(VCPU *vcpu)
awilliam@9765 480 {
awilliam@9765 481 return &vcpu->arch.vtlb;
awilliam@9765 482 }
awilliam@9765 483
awilliam@9765 484 static inline thash_cb_t *
awilliam@9765 485 vcpu_get_vhpt(VCPU *vcpu)
awilliam@9765 486 {
awilliam@9765 487 return &vcpu->arch.vhpt;
awilliam@9765 488 }
kaf24@8386 489
kaf24@8386 490 #define check_work_pending(v) \
kaf24@8386 491 (event_pending((v)) || ((v)->arch.irq_new_pending))
adsharma@4993 492 #endif