ia64/xen-unstable

annotate tools/firmware/hvmloader/hvmloader.c @ 18921:7802a247e6f9

hvmloader: enable bus mastering of PCI device

Without this, init routine in some PCI option ROM doesn't work well.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Dec 11 13:26:02 2008 +0000 (2008-12-11)
parents 6595393a3d28
children 883d01b2fd72
rev   line source
kaf24@8708 1 /*
keir@16992 2 * hvmloader.c: HVM bootloader.
kaf24@8708 3 *
kaf24@8708 4 * Leendert van Doorn, leendert@watson.ibm.com
kaf24@8708 5 * Copyright (c) 2005, International Business Machines Corporation.
kaf24@8708 6 *
kfraser@12554 7 * Copyright (c) 2006, Keir Fraser, XenSource Inc.
kfraser@12554 8 *
kaf24@8708 9 * This program is free software; you can redistribute it and/or modify it
kaf24@8708 10 * under the terms and conditions of the GNU General Public License,
kaf24@8708 11 * version 2, as published by the Free Software Foundation.
kaf24@8708 12 *
kaf24@8708 13 * This program is distributed in the hope it will be useful, but WITHOUT
kaf24@8708 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
kaf24@8708 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
kaf24@8708 16 * more details.
kaf24@8708 17 *
kaf24@8708 18 * You should have received a copy of the GNU General Public License along with
kaf24@8708 19 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
kaf24@8708 20 * Place - Suite 330, Boston, MA 02111-1307 USA.
kaf24@8708 21 */
kfraser@14959 22
kaf24@8708 23 #include "roms.h"
kfraser@14959 24 #include "acpi/acpi2_0.h"
kfraser@10976 25 #include "hypercall.h"
kfraser@10976 26 #include "util.h"
kfraser@12548 27 #include "config.h"
kaf24@12571 28 #include "apic_regs.h"
kfraser@12554 29 #include "pci_regs.h"
keir@15303 30 #include "e820.h"
keir@17374 31 #include "option_rom.h"
kfraser@10976 32 #include <xen/version.h>
kfraser@11081 33 #include <xen/hvm/params.h>
kaf24@8708 34
keir@17463 35 asm (
kfraser@12548 36 " .text \n"
kfraser@12548 37 " .globl _start \n"
kfraser@12548 38 "_start: \n"
kfraser@14373 39 /* C runtime kickoff. */
kfraser@12548 40 " cld \n"
kfraser@12548 41 " cli \n"
kfraser@14373 42 " movl $stack_top,%esp \n"
kfraser@14373 43 " movl %esp,%ebp \n"
kfraser@14373 44 " call main \n"
kfraser@14373 45 /* Relocate real-mode trampoline to 0x0. */
kfraser@14373 46 " mov $trampoline_start,%esi \n"
kfraser@14373 47 " xor %edi,%edi \n"
kfraser@14373 48 " mov $trampoline_end,%ecx \n"
kfraser@14373 49 " sub %esi,%ecx \n"
kfraser@14373 50 " rep movsb \n"
kfraser@14373 51 /* Load real-mode compatible segment state (base 0x0000, limit 0xffff). */
kfraser@12548 52 " lgdt gdt_desr \n"
kfraser@14373 53 " mov $0x0010,%ax \n"
kfraser@14373 54 " mov %ax,%ds \n"
kfraser@14373 55 " mov %ax,%es \n"
kfraser@14373 56 " mov %ax,%fs \n"
kfraser@14373 57 " mov %ax,%gs \n"
kfraser@14373 58 " mov %ax,%ss \n"
kfraser@14391 59 /* Initialise all 32-bit GPRs to zero. */
kfraser@14391 60 " xor %eax,%eax \n"
kfraser@14391 61 " xor %ebx,%ebx \n"
kfraser@14391 62 " xor %ecx,%ecx \n"
kfraser@14391 63 " xor %edx,%edx \n"
kfraser@14391 64 " xor %esp,%esp \n"
kfraser@14391 65 " xor %ebp,%ebp \n"
kfraser@14391 66 " xor %esi,%esi \n"
kfraser@14391 67 " xor %edi,%edi \n"
kfraser@14373 68 /* Enter real mode, reload all segment registers and IDT. */
kfraser@14391 69 " ljmp $0x8,$0x0 \n"
kfraser@14373 70 "trampoline_start: .code16 \n"
kfraser@14373 71 " mov %eax,%cr0 \n"
kfraser@14373 72 " ljmp $0,$1f-trampoline_start\n"
kfraser@14391 73 "1: mov %ax,%ds \n"
kfraser@14373 74 " mov %ax,%es \n"
kfraser@14373 75 " mov %ax,%fs \n"
kfraser@14373 76 " mov %ax,%gs \n"
kfraser@14373 77 " mov %ax,%ss \n"
kfraser@14373 78 " lidt 1f-trampoline_start \n"
kfraser@14373 79 " ljmp $0xf000,$0xfff0 \n"
kfraser@14373 80 "1: .word 0x3ff,0,0 \n"
kfraser@14373 81 "trampoline_end: .code32 \n"
kfraser@12548 82 " \n"
kfraser@12548 83 "gdt_desr: \n"
kfraser@12548 84 " .word gdt_end - gdt - 1 \n"
kfraser@12548 85 " .long gdt \n"
kfraser@12548 86 " \n"
kfraser@12548 87 " .align 8 \n"
kfraser@12548 88 "gdt: \n"
kfraser@12548 89 " .quad 0x0000000000000000 \n"
kfraser@14373 90 " .quad 0x00009a000000ffff \n" /* Ring 0 code, base 0 limit 0xffff */
kfraser@14373 91 " .quad 0x000092000000ffff \n" /* Ring 0 data, base 0 limit 0xffff */
kfraser@12548 92 "gdt_end: \n"
kfraser@12548 93 " \n"
kfraser@12548 94 " .bss \n"
kfraser@12548 95 " .align 8 \n"
kfraser@12548 96 "stack: \n"
kfraser@12548 97 " .skip 0x4000 \n"
kfraser@12548 98 "stack_top: \n"
keir@17467 99 " .text \n"
kfraser@12548 100 );
kaf24@8708 101
keir@17694 102 static enum { VGA_none, VGA_std, VGA_cirrus } virtual_vga = VGA_none;
kaf24@8708 103
keir@18621 104 static void init_hypercalls(void)
kfraser@10976 105 {
kfraser@12548 106 uint32_t eax, ebx, ecx, edx;
kfraser@12548 107 unsigned long i;
kfraser@12554 108 char signature[13];
kfraser@12548 109 xen_extraversion_t extraversion;
keir@18621 110 uint32_t base;
kfraser@10976 111
keir@18621 112 for ( base = 0x40000000; base < 0x40001000; base += 0x100 )
keir@18621 113 {
keir@18621 114 cpuid(base, &eax, &ebx, &ecx, &edx);
kfraser@10976 115
keir@18621 116 *(uint32_t *)(signature + 0) = ebx;
keir@18621 117 *(uint32_t *)(signature + 4) = ecx;
keir@18621 118 *(uint32_t *)(signature + 8) = edx;
keir@18621 119 signature[12] = '\0';
keir@18621 120
keir@18621 121 if ( !strcmp("XenVMMXenVMM", signature) )
keir@18621 122 break;
keir@18621 123 }
keir@18621 124
keir@18621 125 BUG_ON(strcmp("XenVMMXenVMM", signature) || ((eax - base) < 2));
kfraser@10976 126
kfraser@12554 127 /* Fill in hypercall transfer pages. */
keir@18621 128 cpuid(base + 2, &eax, &ebx, &ecx, &edx);
kfraser@12548 129 for ( i = 0; i < eax; i++ )
kfraser@12548 130 wrmsr(ebx, HYPERCALL_PHYSICAL_ADDRESS + (i << 12) + i);
kfraser@12548 131
kfraser@12554 132 /* Print version information. */
keir@18621 133 cpuid(base + 1, &eax, &ebx, &ecx, &edx);
kfraser@12548 134 hypercall_xen_version(XENVER_extraversion, extraversion);
kfraser@12554 135 printf("Detected Xen v%u.%u%s\n", eax >> 16, eax & 0xffff, extraversion);
kfraser@10976 136 }
kfraser@10976 137
kfraser@12548 138 static void apic_setup(void)
kaf24@8708 139 {
kaf24@12571 140 /* Set the IOAPIC ID to tha static value used in the MP/ACPI tables. */
kaf24@12571 141 ioapic_write(0x00, IOAPIC_ID);
kaf24@8708 142
kaf24@12571 143 /* Set up Virtual Wire mode. */
kaf24@12571 144 lapic_write(APIC_SPIV, APIC_SPIV_APIC_ENABLED | 0xFF);
kaf24@12571 145 lapic_write(APIC_LVT0, APIC_MODE_EXTINT << 8);
kaf24@12571 146 lapic_write(APIC_LVT1, APIC_MODE_NMI << 8);
kaf24@8708 147 }
kaf24@8708 148
kfraser@12554 149 static void pci_setup(void)
kfraser@12554 150 {
keir@16835 151 uint32_t base, devfn, bar_reg, bar_data, bar_sz, cmd;
kfraser@12554 152 uint16_t class, vendor_id, device_id;
kfraser@12554 153 unsigned int bar, pin, link, isa_irq;
kfraser@12554 154
keir@16835 155 /* Resources assignable to PCI devices via BARs. */
keir@16835 156 struct resource {
keir@16835 157 uint32_t base, max;
keir@16835 158 } *resource;
keir@17476 159 struct resource mem_resource = { PCI_MEMBASE, PCI_MEMBASE + PCI_MEMSIZE };
keir@16835 160 struct resource io_resource = { 0xc000, 0x10000 };
keir@16835 161
keir@16834 162 /* Create a list of device BARs in descending order of size. */
keir@16834 163 struct bars {
keir@16834 164 uint32_t devfn, bar_reg, bar_sz;
keir@17694 165 } *bars = (struct bars *)SCRATCH_PHYSICAL_ADDRESS;
keir@16834 166 unsigned int i, nr_bars = 0;
keir@16834 167
kfraser@12554 168 /* Program PCI-ISA bridge with appropriate link routes. */
kfraser@15581 169 isa_irq = 0;
kfraser@15581 170 for ( link = 0; link < 4; link++ )
kfraser@12554 171 {
kfraser@15581 172 do { isa_irq = (isa_irq + 1) & 15;
kfraser@15581 173 } while ( !(PCI_ISA_IRQ_MASK & (1U << isa_irq)) );
kfraser@12554 174 pci_writeb(PCI_ISA_DEVFN, 0x60 + link, isa_irq);
kfraser@12554 175 printf("PCI-ISA link %u routed to IRQ%u\n", link, isa_irq);
kfraser@12554 176 }
kfraser@12554 177
kfraser@12554 178 /* Program ELCR to match PCI-wired IRQs. */
kfraser@12554 179 outb(0x4d0, (uint8_t)(PCI_ISA_IRQ_MASK >> 0));
kfraser@12554 180 outb(0x4d1, (uint8_t)(PCI_ISA_IRQ_MASK >> 8));
kfraser@12554 181
kfraser@12554 182 /* Scan the PCI bus and map resources. */
kfraser@12554 183 for ( devfn = 0; devfn < 128; devfn++ )
kfraser@12554 184 {
kfraser@12554 185 class = pci_readw(devfn, PCI_CLASS_DEVICE);
kfraser@12554 186 vendor_id = pci_readw(devfn, PCI_VENDOR_ID);
kfraser@12554 187 device_id = pci_readw(devfn, PCI_DEVICE_ID);
kfraser@12554 188 if ( (vendor_id == 0xffff) && (device_id == 0xffff) )
kfraser@12554 189 continue;
kfraser@12554 190
kfraser@12554 191 ASSERT((devfn != PCI_ISA_DEVFN) ||
kfraser@12554 192 ((vendor_id == 0x8086) && (device_id == 0x7000)));
kfraser@12554 193
kfraser@12554 194 switch ( class )
kfraser@12554 195 {
keir@17694 196 case 0x0300:
keir@17694 197 if ( (vendor_id == 0x1234) && (device_id == 0x1111) )
keir@17694 198 virtual_vga = VGA_std;
keir@17694 199 if ( (vendor_id == 0x1013) && (device_id == 0xb8) )
keir@17694 200 virtual_vga = VGA_cirrus;
keir@17694 201 break;
kfraser@12554 202 case 0x0680:
keir@17698 203 /* PIIX4 ACPI PM. Special device with special PCI config space. */
kfraser@12554 204 ASSERT((vendor_id == 0x8086) && (device_id == 0x7113));
kfraser@12554 205 pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */
kfraser@12554 206 pci_writew(devfn, 0x22, 0x0000);
kfraser@12554 207 pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */
kfraser@12554 208 pci_writew(devfn, 0x3d, 0x0001);
kfraser@12554 209 break;
kfraser@12554 210 case 0x0101:
keir@17911 211 if ( vendor_id == 0x8086 )
keir@17911 212 {
keir@17911 213 /* Intel ICHs since PIIX3: enable IDE legacy mode. */
keir@17911 214 pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */
keir@17911 215 pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */
keir@17911 216 }
keir@17698 217 break;
keir@17698 218 }
kfraser@12554 219
keir@17698 220 /* Map the I/O memory and port resources. */
keir@17698 221 for ( bar = 0; bar < 7; bar++ )
keir@17698 222 {
keir@17698 223 bar_reg = PCI_BASE_ADDRESS_0 + 4*bar;
keir@17698 224 if ( bar == 6 )
keir@17698 225 bar_reg = PCI_ROM_ADDRESS;
kfraser@12554 226
keir@17698 227 bar_data = pci_readl(devfn, bar_reg);
keir@17698 228 pci_writel(devfn, bar_reg, ~0);
keir@17698 229 bar_sz = pci_readl(devfn, bar_reg);
keir@17698 230 pci_writel(devfn, bar_reg, bar_data);
keir@17698 231 if ( bar_sz == 0 )
keir@17698 232 continue;
keir@16834 233
keir@17698 234 bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) ==
keir@17698 235 PCI_BASE_ADDRESS_SPACE_MEMORY) ?
keir@17698 236 PCI_BASE_ADDRESS_MEM_MASK :
keir@17698 237 (PCI_BASE_ADDRESS_IO_MASK & 0xffff));
keir@17698 238 bar_sz &= ~(bar_sz - 1);
keir@16834 239
keir@17698 240 for ( i = 0; i < nr_bars; i++ )
keir@17698 241 if ( bars[i].bar_sz < bar_sz )
keir@17698 242 break;
keir@17698 243
keir@17698 244 if ( i != nr_bars )
keir@17698 245 memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars));
keir@17698 246
keir@17698 247 bars[i].devfn = devfn;
keir@17698 248 bars[i].bar_reg = bar_reg;
keir@17698 249 bars[i].bar_sz = bar_sz;
keir@17698 250
keir@17698 251 nr_bars++;
keir@18405 252
keir@18405 253 /* Skip the upper-half of the address for a 64-bit BAR. */
keir@18405 254 if ( (bar_data & (PCI_BASE_ADDRESS_SPACE |
keir@18405 255 PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
keir@18405 256 (PCI_BASE_ADDRESS_SPACE_MEMORY |
keir@18405 257 PCI_BASE_ADDRESS_MEM_TYPE_64) )
keir@18405 258 bar++;
kfraser@12554 259 }
kfraser@12554 260
kfraser@12554 261 /* Map the interrupt. */
kfraser@12554 262 pin = pci_readb(devfn, PCI_INTERRUPT_PIN);
kfraser@12554 263 if ( pin != 0 )
kfraser@12554 264 {
kfraser@12554 265 /* This is the barber's pole mapping used by Xen. */
kfraser@12554 266 link = ((pin - 1) + (devfn >> 3)) & 3;
kfraser@12554 267 isa_irq = pci_readb(PCI_ISA_DEVFN, 0x60 + link);
kfraser@12554 268 pci_writeb(devfn, PCI_INTERRUPT_LINE, isa_irq);
kfraser@12554 269 printf("pci dev %02x:%x INT%c->IRQ%u\n",
kfraser@12554 270 devfn>>3, devfn&7, 'A'+pin-1, isa_irq);
kfraser@12554 271 }
keir@18921 272
keir@18921 273 /* Enable bus mastering. */
keir@18921 274 cmd = pci_readw(devfn, PCI_COMMAND);
keir@18921 275 cmd |= PCI_COMMAND_MASTER;
keir@18921 276 pci_writew(devfn, PCI_COMMAND, cmd);
kfraser@12554 277 }
keir@16834 278
keir@16834 279 /* Assign iomem and ioport resources in descending order of size. */
keir@16834 280 for ( i = 0; i < nr_bars; i++ )
keir@16834 281 {
keir@16834 282 devfn = bars[i].devfn;
keir@16834 283 bar_reg = bars[i].bar_reg;
keir@16834 284 bar_sz = bars[i].bar_sz;
keir@16834 285
keir@16834 286 bar_data = pci_readl(devfn, bar_reg);
keir@16834 287
keir@16834 288 if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
keir@16834 289 PCI_BASE_ADDRESS_SPACE_MEMORY )
keir@16834 290 {
keir@16835 291 resource = &mem_resource;
keir@16834 292 bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
keir@16834 293 }
keir@16834 294 else
keir@16834 295 {
keir@16835 296 resource = &io_resource;
keir@16834 297 bar_data &= ~PCI_BASE_ADDRESS_IO_MASK;
keir@16834 298 }
keir@16834 299
keir@16835 300 base = (resource->base + bar_sz - 1) & ~(bar_sz - 1);
keir@16835 301 bar_data |= base;
keir@16835 302 base += bar_sz;
keir@16835 303
keir@16835 304 if ( (base < resource->base) || (base > resource->max) )
keir@16835 305 {
keir@16835 306 printf("pci dev %02x:%x bar %02x size %08x: no space for "
keir@16835 307 "resource!\n", devfn>>3, devfn&7, bar_reg, bar_sz);
keir@16835 308 continue;
keir@16835 309 }
keir@16835 310
keir@16835 311 resource->base = base;
keir@16834 312
keir@16834 313 pci_writel(devfn, bar_reg, bar_data);
keir@16835 314 printf("pci dev %02x:%x bar %02x size %08x: %08x\n",
keir@16835 315 devfn>>3, devfn&7, bar_reg, bar_sz, bar_data);
keir@16834 316
keir@16834 317 /* Now enable the memory or I/O mapping. */
keir@16834 318 cmd = pci_readw(devfn, PCI_COMMAND);
keir@16834 319 if ( (bar_reg == PCI_ROM_ADDRESS) ||
keir@16834 320 ((bar_data & PCI_BASE_ADDRESS_SPACE) ==
keir@16834 321 PCI_BASE_ADDRESS_SPACE_MEMORY) )
keir@16834 322 cmd |= PCI_COMMAND_MEMORY;
keir@16834 323 else
keir@16834 324 cmd |= PCI_COMMAND_IO;
keir@16834 325 pci_writew(devfn, PCI_COMMAND, cmd);
keir@16834 326 }
kfraser@12554 327 }
kfraser@12554 328
keir@16960 329 /*
keir@18827 330 * Scan the list of Option ROMs at @roms for one which supports
keir@18828 331 * PCI (@vendor_id, @device_id) found at slot @devfn. If one is found,
keir@18828 332 * copy it to @dest and return its size rounded up to a multiple 2kB. This
keir@18828 333 * function will not copy ROMs beyond address 0xE0000.
keir@16960 334 */
keir@18827 335 #define round_option_rom(x) (((x) + 2047) & ~2047)
keir@18827 336 static int scan_option_rom(
keir@18828 337 uint8_t devfn, uint16_t vendor_id, uint16_t device_id,
keir@18828 338 void *roms, uint32_t dest)
keir@16960 339 {
keir@17374 340 struct option_rom_header *rom;
keir@17374 341 struct option_rom_pnp_header *pnph;
keir@17374 342 struct option_rom_pci_header *pcih;
keir@17374 343 uint8_t csum;
keir@17374 344 int i;
keir@16960 345
keir@18827 346 static uint32_t orom_ids[64];
keir@18827 347 static int nr_roms;
keir@16960 348
keir@18827 349 /* Avoid duplicate ROMs. */
keir@18827 350 for ( i = 0; i < nr_roms; i++ )
keir@18827 351 if ( orom_ids[i] == (vendor_id | ((uint32_t)device_id << 16)) )
keir@18827 352 return 0;
keir@17374 353
keir@18827 354 rom = roms;
keir@18827 355 for ( ; ; )
keir@18827 356 {
keir@18827 357 /* Invalid signature means we're out of option ROMs. */
keir@18827 358 if ( strncmp((char *)rom->signature, "\x55\xaa", 2) ||
keir@18827 359 (rom->rom_size == 0) )
keir@18827 360 break;
keir@17374 361
keir@18827 362 /* Invalid checksum means we're out of option ROMs. */
keir@18827 363 csum = 0;
keir@18827 364 for ( i = 0; i < (rom->rom_size * 512); i++ )
keir@18827 365 csum += ((uint8_t *)rom)[i];
keir@18827 366 if ( csum != 0 )
keir@18827 367 break;
keir@17374 368
keir@18827 369 /* Check the PCI PnP header (if any) for a match. */
keir@18827 370 pcih = (struct option_rom_pci_header *)
keir@18827 371 ((char *)rom + rom->pci_header_offset);
keir@18827 372 if ( (rom->pci_header_offset != 0) &&
keir@18827 373 !strncmp((char *)pcih->signature, "PCIR", 4) &&
keir@18827 374 (pcih->vendor_id == vendor_id) &&
keir@18827 375 (pcih->device_id == device_id) )
keir@18827 376 goto found;
keir@18827 377
keir@18827 378 rom = (struct option_rom_header *)
keir@18827 379 ((char *)rom + rom->rom_size * 512);
keir@16960 380 }
keir@16960 381
keir@16960 382 return 0;
keir@16960 383
keir@16960 384 found:
keir@17412 385 /* Find the PnP expansion header (if any). */
keir@17412 386 pnph = ((rom->expansion_header_offset != 0)
keir@17412 387 ? ((struct option_rom_pnp_header *)
keir@17412 388 ((char *)rom + rom->expansion_header_offset))
keir@17412 389 : ((struct option_rom_pnp_header *)NULL));
keir@17430 390 while ( (pnph != NULL) && strncmp((char *)pnph->signature, "$PnP", 4) )
keir@17412 391 pnph = ((pnph->next_header_offset != 0)
keir@17412 392 ? ((struct option_rom_pnp_header *)
keir@17412 393 ((char *)rom + pnph->next_header_offset))
keir@17412 394 : ((struct option_rom_pnp_header *)NULL));
keir@17412 395
keir@18827 396 printf("Loading PCI Option ROM ...\n");
keir@17374 397 if ( (pnph != NULL) && (pnph->manufacturer_name_offset != 0) )
keir@17374 398 printf(" - Manufacturer: %s\n",
keir@17374 399 (char *)rom + pnph->manufacturer_name_offset);
keir@17374 400 if ( (pnph != NULL) && (pnph->product_name_offset != 0) )
keir@17374 401 printf(" - Product name: %s\n",
keir@17374 402 (char *)rom + pnph->product_name_offset);
keir@18827 403
keir@18828 404 if ( (dest + rom->rom_size * 512 + 1) > 0xe0000u )
keir@18827 405 {
keir@18827 406 printf("Option ROM size %x exceeds available space\n",
keir@18827 407 rom->rom_size * 512);
keir@18827 408 return 0;
keir@18827 409 }
keir@18827 410
keir@18827 411 orom_ids[nr_roms++] = vendor_id | ((uint32_t)device_id << 16);
keir@18827 412 memcpy((void *)dest, rom, rom->rom_size * 512);
keir@18828 413 *(uint8_t *)(dest + rom->rom_size * 512) = devfn;
keir@18828 414 return round_option_rom(rom->rom_size * 512 + 1);
keir@18827 415 }
keir@18827 416
keir@18827 417 /*
keir@18827 418 * Scan the PCI bus for the first NIC supported by etherboot, and copy
keir@18827 419 * the corresponding rom data to *copy_rom_dest. Returns the length of the
keir@18827 420 * selected rom, or 0 if no NIC found.
keir@18827 421 */
keir@18827 422 static int scan_etherboot_nic(uint32_t copy_rom_dest)
keir@18827 423 {
keir@18828 424 uint8_t devfn;
keir@18827 425 uint16_t class, vendor_id, device_id;
keir@18827 426
keir@18827 427 for ( devfn = 0; devfn < 128; devfn++ )
keir@18827 428 {
keir@18827 429 class = pci_readw(devfn, PCI_CLASS_DEVICE);
keir@18827 430 vendor_id = pci_readw(devfn, PCI_VENDOR_ID);
keir@18827 431 device_id = pci_readw(devfn, PCI_DEVICE_ID);
keir@18827 432
keir@18827 433 /* We're only interested in NICs. */
keir@18827 434 if ( (vendor_id != 0xffff) &&
keir@18827 435 (device_id != 0xffff) &&
keir@18827 436 (class == 0x0200) )
keir@18827 437 return scan_option_rom(
keir@18828 438 devfn, vendor_id, device_id, etherboot, copy_rom_dest);
keir@18827 439 }
keir@18827 440
keir@18827 441 return 0;
keir@18827 442 }
keir@18827 443
keir@18827 444 /*
keir@18827 445 * Scan the PCI bus for the devices that have an option ROM, and copy
keir@18827 446 * the corresponding rom data to rom_phys_addr.
keir@18827 447 */
keir@18827 448 static int pci_load_option_roms(uint32_t rom_base_addr)
keir@18827 449 {
keir@18828 450 uint32_t option_rom_addr, rom_phys_addr = rom_base_addr;
keir@18827 451 uint16_t vendor_id, device_id;
keir@18828 452 uint8_t devfn, class;
keir@18827 453
keir@18827 454 for ( devfn = 0; devfn < 128; devfn++ )
keir@18827 455 {
keir@18827 456 class = pci_readb(devfn, PCI_CLASS_DEVICE + 1);
keir@18827 457 vendor_id = pci_readw(devfn, PCI_VENDOR_ID);
keir@18827 458 device_id = pci_readw(devfn, PCI_DEVICE_ID);
keir@18827 459
keir@18827 460 if ( (vendor_id == 0xffff) && (device_id == 0xffff) )
keir@18827 461 continue;
keir@18827 462
keir@18827 463 /*
keir@18827 464 * Currently only scan options from mass storage devices and serial
keir@18827 465 * bus controller (Fibre Channel included).
keir@18827 466 */
keir@18827 467 if ( (class != 0x1) && (class != 0xc) )
keir@18827 468 continue;
keir@18827 469
keir@18827 470 option_rom_addr = pci_readl(devfn, PCI_ROM_ADDRESS);
keir@18827 471 if ( !option_rom_addr )
keir@18827 472 continue;
keir@18827 473
keir@18827 474 /* Ensure Expansion Bar is enabled before copying */
keir@18827 475 pci_writel(devfn, PCI_ROM_ADDRESS, option_rom_addr | 0x1);
keir@18827 476
keir@18827 477 rom_phys_addr += scan_option_rom(
keir@18828 478 devfn, vendor_id, device_id,
keir@18828 479 (void *)(option_rom_addr & ~2047), rom_phys_addr);
keir@18827 480
keir@18827 481 /* Restore the default original value of Expansion Bar */
keir@18827 482 pci_writel(devfn, PCI_ROM_ADDRESS, option_rom_addr);
keir@18827 483 }
keir@18827 484
keir@18827 485 return rom_phys_addr - rom_base_addr;
keir@16960 486 }
keir@16960 487
keir@14449 488 /* Replace possibly erroneous memory-size CMOS fields with correct values. */
keir@14449 489 static void cmos_write_memory_size(void)
keir@14449 490 {
keir@15303 491 struct e820entry *map = HVM_E820;
keir@15303 492 int i, nr = *HVM_E820_NR;
keir@14449 493 uint32_t base_mem = 640, ext_mem = 0, alt_mem = 0;
keir@14449 494
keir@14449 495 for ( i = 0; i < nr; i++ )
keir@14449 496 if ( (map[i].addr >= 0x100000) && (map[i].type == E820_RAM) )
keir@14449 497 break;
keir@14449 498
keir@14449 499 if ( i != nr )
keir@14449 500 {
keir@14449 501 alt_mem = ext_mem = map[i].addr + map[i].size;
keir@14449 502 ext_mem = (ext_mem > 0x0100000) ? (ext_mem - 0x0100000) >> 10 : 0;
keir@14449 503 if ( ext_mem > 0xffff )
keir@14449 504 ext_mem = 0xffff;
keir@14449 505 alt_mem = (alt_mem > 0x1000000) ? (alt_mem - 0x1000000) >> 16 : 0;
keir@14449 506 }
keir@14449 507
keir@14877 508 /* All BIOSes: conventional memory (CMOS *always* reports 640kB). */
keir@14449 509 cmos_outb(0x15, (uint8_t)(base_mem >> 0));
keir@14449 510 cmos_outb(0x16, (uint8_t)(base_mem >> 8));
keir@14449 511
keir@14449 512 /* All BIOSes: extended memory (1kB chunks above 1MB). */
keir@14449 513 cmos_outb(0x17, (uint8_t)( ext_mem >> 0));
keir@14449 514 cmos_outb(0x18, (uint8_t)( ext_mem >> 8));
keir@14449 515 cmos_outb(0x30, (uint8_t)( ext_mem >> 0));
keir@14449 516 cmos_outb(0x31, (uint8_t)( ext_mem >> 8));
keir@14449 517
keir@14449 518 /* Some BIOSes: alternative extended memory (64kB chunks above 16MB). */
keir@14449 519 cmos_outb(0x34, (uint8_t)( alt_mem >> 0));
keir@14449 520 cmos_outb(0x35, (uint8_t)( alt_mem >> 8));
Tim@13140 521 }
Tim@13140 522
keir@18394 523 static uint16_t init_xen_platform_io_base(void)
keir@18030 524 {
keir@18030 525 struct bios_info *bios_info = (struct bios_info *)ACPI_PHYSICAL_ADDRESS;
keir@18030 526 uint32_t devfn, bar_data;
keir@18030 527 uint16_t vendor_id, device_id;
keir@18030 528
keir@18394 529 bios_info->xen_pfiob = 0;
keir@18394 530
keir@18030 531 for ( devfn = 0; devfn < 128; devfn++ )
keir@18030 532 {
keir@18030 533 vendor_id = pci_readw(devfn, PCI_VENDOR_ID);
keir@18030 534 device_id = pci_readw(devfn, PCI_DEVICE_ID);
keir@18030 535 if ( (vendor_id != 0x5853) || (device_id != 0x0001) )
keir@18030 536 continue;
keir@18030 537 bar_data = pci_readl(devfn, PCI_BASE_ADDRESS_0);
keir@18030 538 bios_info->xen_pfiob = bar_data & PCI_BASE_ADDRESS_IO_MASK;
keir@18030 539 }
keir@18394 540
keir@18394 541 return bios_info->xen_pfiob;
keir@18030 542 }
keir@18030 543
keir@18901 544 /* Set up an empty TSS area for virtual 8086 mode to use.
keir@18901 545 * The only important thing is that it musn't have any bits set
keir@18901 546 * in the interrupt redirection bitmap, so all zeros will do. */
keir@18901 547 static void init_vm86_tss(void)
keir@18901 548 {
keir@18901 549 uint32_t tss;
keir@18901 550 struct xen_hvm_param p;
keir@18901 551
keir@18901 552 tss = e820_malloc(128, 128);
keir@18901 553 memset((char *)tss, 0, 128);
keir@18901 554 p.domid = DOMID_SELF;
keir@18901 555 p.index = HVM_PARAM_VM86_TSS;
keir@18901 556 p.value = tss;
keir@18901 557 hypercall_hvm_op(HVMOP_set_param, &p);
keir@18901 558 printf("vm86 TSS at %08x\n", tss);
keir@18901 559 }
keir@18901 560
kfraser@12548 561 int main(void)
kfraser@12548 562 {
keir@18827 563 int option_rom_sz = 0, vgabios_sz = 0, etherboot_sz = 0;
keir@18827 564 int rombios_sz, smbios_sz;
keir@18827 565 uint32_t etherboot_phys_addr, option_rom_phys_addr, vga_ram = 0;
keir@18394 566 uint16_t xen_pfiob;
kaf24@12574 567
kfraser@12554 568 printf("HVM Loader\n");
kfraser@12548 569
kfraser@12548 570 init_hypercalls();
kfraser@12548 571
keir@17363 572 printf("CPU speed is %u MHz\n", get_cpu_mhz());
keir@17363 573
keir@17463 574 smp_initialise();
keir@17463 575
keir@18358 576 perform_tests();
keir@18358 577
kfraser@12554 578 printf("Writing SMBIOS tables ...\n");
kfraser@14959 579 smbios_sz = hvm_write_smbios_tables();
kfraser@12548 580
kfraser@12554 581 printf("Loading ROMBIOS ...\n");
kfraser@14959 582 rombios_sz = sizeof(rombios);
kfraser@14959 583 if ( rombios_sz > 0x10000 )
kfraser@14959 584 rombios_sz = 0x10000;
kfraser@14959 585 memcpy((void *)ROMBIOS_PHYSICAL_ADDRESS, rombios, rombios_sz);
kaf24@13656 586 highbios_setup();
kfraser@12548 587
kfraser@12548 588 apic_setup();
kfraser@12554 589 pci_setup();
kaf24@12574 590
kfraser@12600 591 if ( (get_vcpu_nr() > 1) || get_apic_mode() )
kaf24@12574 592 create_mp_tables();
kfraser@12548 593
keir@17694 594 switch ( virtual_vga )
kfraser@12548 595 {
keir@17694 596 case VGA_cirrus:
kfraser@12554 597 printf("Loading Cirrus VGABIOS ...\n");
kfraser@12548 598 memcpy((void *)VGABIOS_PHYSICAL_ADDRESS,
kfraser@12548 599 vgabios_cirrusvga, sizeof(vgabios_cirrusvga));
keir@18827 600 vgabios_sz = round_option_rom(sizeof(vgabios_cirrusvga));
keir@17694 601 break;
keir@17694 602 case VGA_std:
kfraser@12554 603 printf("Loading Standard VGABIOS ...\n");
kfraser@12548 604 memcpy((void *)VGABIOS_PHYSICAL_ADDRESS,
kfraser@12548 605 vgabios_stdvga, sizeof(vgabios_stdvga));
keir@18827 606 vgabios_sz = round_option_rom(sizeof(vgabios_stdvga));
keir@17694 607 break;
keir@17694 608 default:
keir@17694 609 printf("No emulated VGA adaptor ...\n");
keir@17694 610 break;
kfraser@12548 611 }
kfraser@12548 612
keir@18394 613 if ( virtual_vga != VGA_none )
keir@18394 614 {
keir@18394 615 vga_ram = e820_malloc(8 << 20, 4096);
keir@18394 616 printf("VGA RAM at %08x\n", vga_ram);
keir@18394 617 }
keir@18394 618
keir@18827 619 etherboot_phys_addr = VGABIOS_PHYSICAL_ADDRESS + vgabios_sz;
keir@18827 620 etherboot_sz = scan_etherboot_nic(etherboot_phys_addr);
keir@18827 621
keir@18827 622 option_rom_phys_addr = etherboot_phys_addr + etherboot_sz;
keir@18827 623 option_rom_sz = pci_load_option_roms(option_rom_phys_addr);
Tim@13140 624
kfraser@14959 625 if ( get_acpi_enabled() )
kfraser@12548 626 {
kfraser@12554 627 printf("Loading ACPI ...\n");
keir@18191 628 acpi_build_tables();
kfraser@12548 629 }
kfraser@12548 630
keir@18901 631 init_vm86_tss();
keir@18901 632
keir@14449 633 cmos_write_memory_size();
keir@14449 634
kfraser@14959 635 printf("BIOS map:\n");
kfraser@14959 636 if ( vgabios_sz )
kfraser@14959 637 printf(" %05x-%05x: VGA BIOS\n",
kfraser@14959 638 VGABIOS_PHYSICAL_ADDRESS,
kfraser@14959 639 VGABIOS_PHYSICAL_ADDRESS + vgabios_sz - 1);
kfraser@14959 640 if ( etherboot_sz )
kfraser@14959 641 printf(" %05x-%05x: Etherboot ROM\n",
keir@18826 642 etherboot_phys_addr,
keir@18826 643 etherboot_phys_addr + etherboot_sz - 1);
keir@18827 644 if ( option_rom_sz )
keir@18827 645 printf(" %05x-%05x: PCI Option ROMs\n",
keir@18827 646 option_rom_phys_addr,
keir@18827 647 option_rom_phys_addr + option_rom_sz - 1);
kfraser@14959 648 if ( smbios_sz )
kfraser@14959 649 printf(" %05x-%05x: SMBIOS tables\n",
kfraser@14959 650 SMBIOS_PHYSICAL_ADDRESS,
kfraser@14959 651 SMBIOS_PHYSICAL_ADDRESS + smbios_sz - 1);
kfraser@14959 652 if ( rombios_sz )
kfraser@14959 653 printf(" %05x-%05x: Main BIOS\n",
kfraser@14959 654 ROMBIOS_PHYSICAL_ADDRESS,
kfraser@14959 655 ROMBIOS_PHYSICAL_ADDRESS + rombios_sz - 1);
kfraser@14959 656
keir@18394 657 xen_pfiob = init_xen_platform_io_base();
keir@18394 658 if ( xen_pfiob && vga_ram )
keir@18394 659 outl(xen_pfiob + 4, vga_ram);
keir@18030 660
kfraser@14373 661 printf("Invoking ROMBIOS ...\n");
kfraser@12548 662 return 0;
kfraser@12548 663 }
kfraser@12548 664
kfraser@12548 665 /*
kfraser@12548 666 * Local variables:
kfraser@12548 667 * mode: C
kfraser@12548 668 * c-set-style: "BSD"
kfraser@12548 669 * c-basic-offset: 4
kfraser@12548 670 * tab-width: 4
kfraser@12548 671 * indent-tabs-mode: nil
kfraser@12548 672 * End:
kfraser@12548 673 */