ia64/xen-unstable

annotate xen/include/asm-ia64/xenkregs.h @ 16781:6f7e6608cb74

[IA64] domheap: Allocate privregs from domain heap for VTi domain

- Pin privregs down with both dtr/itr so that privregs can be allocated
from the domain heap
- Introduce vmx_vpd_pin()/vmx_vpd_unpin().
The vpd area is pinned down when current. But two functions,
update_vhpi() and alloc_vpd() are exceptions.
We have to pin down the area before PAL call.
- Minor twist context switch not to use unpinned vpd area.
vmx_load_state() needs the vpd area pinned down.
Call it after vmx_load_all_rr()
- Fix vmx_load_all_rr()
vmx_switch_rr7() sets psr.ic = 0 so that clearing psr.ic before calling
vmx_switch_rr7() doesn't make sense.
- Improve vmx_switch_rr7()
It sets psr.ic = 0 after switching to physical mode. But it can be
done at the switching time.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents ac296153ea64
children af3550f53874
rev   line source
djm@6457 1 #ifndef _ASM_IA64_XENKREGS_H
djm@6457 2 #define _ASM_IA64_XENKREGS_H
djm@6457 3
djm@6457 4 /*
djm@6457 5 * Translation registers:
djm@6457 6 */
alex@16773 7 #define IA64_TR_XEN_HEAP_REGS 3 /* dtr3: xen heap identity mapped regs */
alex@16773 8 #define IA64_TR_SHARED_INFO 4 /* dtr4: page shared with domain */
awilliam@10444 9 #define IA64_TR_MAPPED_REGS 5 /* dtr5: vcpu mapped regs */
alex@16773 10 #define IA64_TR_VHPT 6 /* dtr6: vhpt */
alex@16773 11
alex@16781 12 #define IA64_TR_VPD 2 /* itr2: vpd */
alex@16781 13
alex@16217 14 #define IA64_DTR_GUEST_KERNEL 7
awilliam@9011 15 #define IA64_ITR_GUEST_KERNEL 2
djm@6457 16 /* Processor status register bits: */
djm@6457 17 #define IA64_PSR_VM_BIT 46
djm@6457 18 #define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
djm@6457 19
awilliam@13840 20 #define IA64_DEFAULT_DCR_BITS (IA64_DCR_PP | IA64_DCR_LC | IA64_DCR_DM | \
awilliam@13840 21 IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
awilliam@13840 22 IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
awilliam@13840 23
alex@15903 24 // note IA64_PSR_PK removed from following, why is this necessary?
alex@15903 25 #define DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
alex@15903 26 IA64_PSR_DT | IA64_PSR_RT | \
alex@15903 27 IA64_PSR_IT | IA64_PSR_BN)
alex@15903 28
alex@15903 29 #define DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL| IA64_PSR_DFH| \
alex@15903 30 IA64_PSR_SP | IA64_PSR_DI | IA64_PSR_SI | \
alex@15903 31 IA64_PSR_DB | IA64_PSR_LP | IA64_PSR_TB | \
alex@15903 32 IA64_PSR_CPL| IA64_PSR_MC | IA64_PSR_IS | \
alex@15903 33 IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
alex@15903 34 IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
alex@15903 35
alex@15903 36 // NO PSR_CLR IS DIFFERENT! (CPL)
alex@15903 37 #define IA64_PSR_CPL1 (__IA64_UL(1) << IA64_PSR_CPL1_BIT)
alex@15903 38 #define IA64_PSR_CPL0 (__IA64_UL(1) << IA64_PSR_CPL0_BIT)
alex@15903 39
djm@6457 40 /* Interruption Function State */
djm@6457 41 #define IA64_IFS_V_BIT 63
djm@6457 42 #define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
djm@6457 43
alex@15418 44 /* Interruption Status Register. */
alex@15418 45 #define IA64_ISR_NI_BIT 39 /* Nested interrupt. */
alex@15418 46
djm@6457 47 /* Page Table Address */
djm@6457 48 #define IA64_PTA_VE_BIT 0
djm@6457 49 #define IA64_PTA_SIZE_BIT 2
alex@15694 50 #define IA64_PTA_SIZE_LEN 6
djm@6457 51 #define IA64_PTA_VF_BIT 8
djm@6457 52 #define IA64_PTA_BASE_BIT 15
djm@6457 53
djm@6457 54 #define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
alex@15694 55 #define IA64_PTA_SIZE (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) << \
alex@15694 56 IA64_PTA_SIZE_BIT)
djm@6457 57 #define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
djm@6457 58 #define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
djm@6457 59
alex@15474 60 /* Some cr.itir declarations. */
alex@15474 61 #define IA64_ITIR_PS 2
alex@15474 62 #define IA64_ITIR_PS_LEN 6
alex@15661 63 #define IA64_ITIR_PS_MASK (((__IA64_UL(1) << IA64_ITIR_PS_LEN) - 1) \
alex@15661 64 << IA64_ITIR_PS)
alex@15474 65 #define IA64_ITIR_KEY 8
alex@15474 66 #define IA64_ITIR_KEY_LEN 24
alex@15474 67 #define IA64_ITIR_KEY_MASK (((__IA64_UL(1) << IA64_ITIR_KEY_LEN) - 1) \
alex@15474 68 << IA64_ITIR_KEY)
alex@15661 69 #define IA64_ITIR_PS_KEY(_ps, _key) (((_ps) << IA64_ITIR_PS) | \
alex@15661 70 (((_key) << IA64_ITIR_KEY)))
alex@15661 71
alex@15694 72 /* Region Register Bits */
alex@15694 73 #define IA64_RR_PS 2
alex@15694 74 #define IA64_RR_PS_LEN 6
alex@15694 75 #define IA64_RR_RID 8
alex@15694 76 #define IA64_RR_RID_LEN 24
alex@15694 77 #define IA64_RR_RID_MASK (((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
alex@15694 78 IA64_RR_RID
alex@15694 79
alex@15661 80 /* Define Protection Key Register (PKR) */
alex@15661 81 #define IA64_PKR_V 0
alex@15661 82 #define IA64_PKR_WD 1
alex@15661 83 #define IA64_PKR_RD 2
alex@15661 84 #define IA64_PKR_XD 3
alex@15661 85 #define IA64_PKR_MBZ0 4
alex@15661 86 #define IA64_PKR_KEY 8
alex@15661 87 #define IA64_PKR_KEY_LEN 24
alex@15661 88 #define IA64_PKR_MBZ1 32
alex@15661 89
alex@15661 90 #define IA64_PKR_VALID (1 << IA64_PKR_V)
alex@15661 91 #define IA64_PKR_KEY_MASK (((__IA64_UL(1) << IA64_PKR_KEY_LEN) - 1) \
alex@15661 92 << IA64_PKR_KEY)
alex@15661 93
alex@15661 94 #define XEN_IA64_NPKRS 15 /* Number of pkr's in PV */
alex@15474 95
alex@15664 96 /* A pkr val for the hypervisor: key = 0, valid = 1. */
alex@15664 97 #define XEN_IA64_PKR_VAL ((0 << IA64_PKR_KEY) | IA64_PKR_VALID)
alex@15664 98
djm@6457 99 #endif /* _ASM_IA64_XENKREGS_H */