ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 16940:6ea3db7ae24d

vmx: Enable Core 2 Duo Performance Counters in HVM guest
Signed-off-by: Haitao Shan <haitao.shan@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jan 30 09:59:27 2008 +0000 (2008-01-30)
parents 0d7d6804af22
children 9fd00ff95068
rev   line source
kaf24@1452 1 /*
kfraser@11541 2 * based on linux-2.6.17.13/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kfraser@11204 13 * Maciej W. Rozycki : Various updates and fixes.
kfraser@11204 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@8847 41 * Knob to control our willingness to enable the local APIC.
kaf24@8847 42 */
kaf24@8847 43 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
kaf24@8847 44
kaf24@8847 45 /*
kaf24@4888 46 * Debug level
kaf24@4888 47 */
kaf24@4888 48 int apic_verbosity;
kaf24@4888 49
kaf24@8847 50
kaf24@8847 51 static void apic_pm_activate(void);
kaf24@8847 52
kfraser@11541 53 int modern_apic(void)
kfraser@11541 54 {
kfraser@11541 55 unsigned int lvr, version;
kfraser@11541 56 /* AMD systems use old APIC versions, so check the CPU */
kfraser@11541 57 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
kfraser@11541 58 boot_cpu_data.x86 >= 0xf)
kfraser@11541 59 return 1;
kfraser@11541 60 lvr = apic_read(APIC_LVR);
kfraser@11541 61 version = GET_APIC_VERSION(lvr);
kfraser@11541 62 return version >= 0x14;
kfraser@11541 63 }
kfraser@11541 64
kaf24@8847 65 /*
kaf24@8847 66 * 'what should we do if we get a hw irq event on an illegal vector'.
kaf24@8847 67 * each architecture has to answer this themselves.
kaf24@8847 68 */
kaf24@8847 69 void ack_bad_irq(unsigned int irq)
kaf24@8847 70 {
kaf24@8847 71 printk("unexpected IRQ trap at vector %02x\n", irq);
kaf24@8847 72 /*
kaf24@8847 73 * Currently unexpected vectors happen only on SMP and APIC.
kaf24@8847 74 * We _must_ ack these because every local APIC has only N
kaf24@8847 75 * irq slots per priority level, and a 'hanging, unacked' IRQ
kaf24@8847 76 * holds up an irq slot - in excessive cases (when multiple
kaf24@8847 77 * unexpected vectors occur) that might lock up the APIC
kaf24@8847 78 * completely.
kfraser@11541 79 * But only ack when the APIC is enabled -AK
kaf24@8847 80 */
kfraser@11541 81 if (cpu_has_apic)
kfraser@11541 82 ack_APIC_irq();
kaf24@8847 83 }
kaf24@8847 84
kaf24@8847 85 void __init apic_intr_init(void)
kaf24@8847 86 {
kaf24@8847 87 #ifdef CONFIG_SMP
kaf24@8847 88 smp_intr_init();
kaf24@8847 89 #endif
kaf24@8847 90 /* self generated IPI for local APIC timer */
kaf24@8847 91 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
kaf24@8847 92
kaf24@8847 93 /* IPI vectors for APIC spurious and error interrupts */
kaf24@8847 94 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
kaf24@8847 95 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
kaf24@8847 96
keir@16940 97 /* Performance Counters Interrupt */
keir@16940 98 set_intr_gate(PMU_APIC_VECTOR, pmu_apic_interrupt);
keir@16940 99
kaf24@8847 100 /* thermal monitor LVT interrupt */
kaf24@8847 101 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@8847 102 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
kaf24@8847 103 #endif
kaf24@8847 104 }
kaf24@8847 105
kaf24@1452 106 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 107 int using_apic_timer = 0;
kaf24@1452 108
kaf24@1452 109 static int enabled_via_apicbase;
kaf24@1452 110
kfraser@11541 111 void enable_NMI_through_LVT0 (void * dummy)
kfraser@11541 112 {
kfraser@11541 113 unsigned int v, ver;
kfraser@11541 114
kfraser@11541 115 ver = apic_read(APIC_LVR);
kfraser@11541 116 ver = GET_APIC_VERSION(ver);
kfraser@11541 117 v = APIC_DM_NMI; /* unmask and set to NMI */
kfraser@11541 118 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kfraser@11541 119 v |= APIC_LVT_LEVEL_TRIGGER;
kfraser@11541 120 apic_write_around(APIC_LVT0, v);
kfraser@11541 121 }
kfraser@11541 122
kaf24@4804 123 int get_physical_broadcast(void)
kaf24@4804 124 {
kfraser@11541 125 if (modern_apic())
kaf24@4804 126 return 0xff;
kaf24@4804 127 else
kaf24@4804 128 return 0xf;
kaf24@4804 129 }
kaf24@4804 130
kaf24@1452 131 int get_maxlvt(void)
kaf24@1452 132 {
kaf24@1452 133 unsigned int v, ver, maxlvt;
kaf24@1452 134
kaf24@1452 135 v = apic_read(APIC_LVR);
kaf24@1452 136 ver = GET_APIC_VERSION(v);
kaf24@1452 137 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 138 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 139 return maxlvt;
kaf24@1452 140 }
kaf24@1452 141
kaf24@1452 142 void clear_local_APIC(void)
kaf24@1452 143 {
kaf24@1452 144 int maxlvt;
kaf24@1452 145 unsigned long v;
kaf24@1452 146
kaf24@1452 147 maxlvt = get_maxlvt();
kaf24@1452 148
kaf24@1452 149 /*
kaf24@1452 150 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 151 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 152 */
kaf24@1452 153 if (maxlvt >= 3) {
kaf24@1452 154 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 155 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 156 }
kaf24@1452 157 /*
kaf24@1452 158 * Careful: we have to set masks only first to deassert
kaf24@1452 159 * any level-triggered sources.
kaf24@1452 160 */
kaf24@1452 161 v = apic_read(APIC_LVTT);
kaf24@1452 162 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 163 v = apic_read(APIC_LVT0);
kaf24@1452 164 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 165 v = apic_read(APIC_LVT1);
kaf24@1452 166 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 167 if (maxlvt >= 4) {
kaf24@1452 168 v = apic_read(APIC_LVTPC);
kaf24@1452 169 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 170 }
kaf24@1452 171
kaf24@5211 172 /* lets not touch this if we didn't frob it */
kaf24@5211 173 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 174 if (maxlvt >= 5) {
kaf24@5211 175 v = apic_read(APIC_LVTTHMR);
kaf24@5211 176 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
kaf24@5211 177 }
kaf24@5211 178 #endif
kaf24@1452 179 /*
kaf24@1452 180 * Clean APIC state for other OSs:
kaf24@1452 181 */
kaf24@1452 182 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 183 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 184 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 185 if (maxlvt >= 3)
kaf24@1452 186 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 187 if (maxlvt >= 4)
kaf24@1452 188 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 189
kaf24@5211 190 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 191 if (maxlvt >= 5)
kaf24@5211 192 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
kaf24@5211 193 #endif
kaf24@1452 194 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kfraser@11204 195 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 196 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 197 apic_write(APIC_ESR, 0);
kaf24@1452 198 apic_read(APIC_ESR);
kaf24@1452 199 }
kaf24@1452 200 }
kaf24@1452 201
kaf24@1452 202 void __init connect_bsp_APIC(void)
kaf24@1452 203 {
kaf24@1452 204 if (pic_mode) {
kaf24@1452 205 /*
kaf24@1452 206 * Do not trust the local APIC being empty at bootup.
kaf24@1452 207 */
kaf24@1452 208 clear_local_APIC();
kaf24@1452 209 /*
kaf24@1452 210 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 211 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 212 */
kaf24@4888 213 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 214 "enabling APIC mode.\n");
kaf24@1452 215 outb(0x70, 0x22);
kaf24@1452 216 outb(0x01, 0x23);
kaf24@1452 217 }
kaf24@5211 218 enable_apic_mode();
kaf24@1452 219 }
kaf24@1452 220
kaf24@8847 221 void disconnect_bsp_APIC(int virt_wire_setup)
kaf24@1452 222 {
kaf24@1452 223 if (pic_mode) {
kaf24@1452 224 /*
kaf24@1452 225 * Put the board back into PIC mode (has an effect
kaf24@1452 226 * only on certain older boards). Note that APIC
kaf24@1452 227 * interrupts, including IPIs, won't work beyond
kaf24@1452 228 * this point! The only exception are INIT IPIs.
kaf24@1452 229 */
kaf24@4888 230 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 231 "entering PIC mode.\n");
kaf24@1452 232 outb(0x70, 0x22);
kaf24@1452 233 outb(0x00, 0x23);
kaf24@1452 234 }
kaf24@8847 235 else {
kaf24@8847 236 /* Go back to Virtual Wire compatibility mode */
kaf24@8847 237 unsigned long value;
kaf24@8847 238
kaf24@8847 239 /* For the spurious interrupt use vector F, and enable it */
kaf24@8847 240 value = apic_read(APIC_SPIV);
kaf24@8847 241 value &= ~APIC_VECTOR_MASK;
kaf24@8847 242 value |= APIC_SPIV_APIC_ENABLED;
kaf24@8847 243 value |= 0xf;
kaf24@8847 244 apic_write_around(APIC_SPIV, value);
kaf24@8847 245
kaf24@8847 246 if (!virt_wire_setup) {
kaf24@8847 247 /* For LVT0 make it edge triggered, active high, external and enabled */
kaf24@8847 248 value = apic_read(APIC_LVT0);
kaf24@8847 249 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 250 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 251 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
kaf24@8847 252 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 253 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
kaf24@8847 254 apic_write_around(APIC_LVT0, value);
kaf24@8847 255 }
kaf24@8847 256 else {
kaf24@8847 257 /* Disable LVT0 */
kaf24@8847 258 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@8847 259 }
kaf24@8847 260
kaf24@8847 261 /* For LVT1 make it edge triggered, active high, nmi and enabled */
kaf24@8847 262 value = apic_read(APIC_LVT1);
kaf24@8847 263 value &= ~(
kaf24@8847 264 APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 265 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 266 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
kaf24@8847 267 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 268 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
kaf24@8847 269 apic_write_around(APIC_LVT1, value);
kaf24@8847 270 }
kaf24@1452 271 }
kaf24@1452 272
kaf24@1452 273 void disable_local_APIC(void)
kaf24@1452 274 {
kaf24@1452 275 unsigned long value;
kaf24@1452 276
kaf24@1452 277 clear_local_APIC();
kaf24@1452 278
kaf24@1452 279 /*
kaf24@1452 280 * Disable APIC (implies clearing of registers
kaf24@1452 281 * for 82489DX!).
kaf24@1452 282 */
kaf24@1452 283 value = apic_read(APIC_SPIV);
kaf24@1452 284 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 285 apic_write_around(APIC_SPIV, value);
kaf24@1452 286
kaf24@1452 287 if (enabled_via_apicbase) {
kaf24@1452 288 unsigned int l, h;
kaf24@1452 289 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 290 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 291 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 292 }
kaf24@1452 293 }
kaf24@1452 294
kaf24@1452 295 /*
kaf24@1452 296 * This is to verify that we're looking at a real local APIC.
kaf24@1452 297 * Check these against your board if the CPUs aren't getting
kaf24@1452 298 * started for no apparent reason.
kaf24@1452 299 */
kaf24@1452 300 int __init verify_local_APIC(void)
kaf24@1452 301 {
kaf24@1452 302 unsigned int reg0, reg1;
kaf24@1452 303
kaf24@1452 304 /*
kaf24@1452 305 * The version register is read-only in a real APIC.
kaf24@1452 306 */
kaf24@1452 307 reg0 = apic_read(APIC_LVR);
kaf24@4888 308 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
kaf24@1452 309 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 310 reg1 = apic_read(APIC_LVR);
kaf24@4888 311 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 312
kaf24@1452 313 /*
kaf24@1452 314 * The two version reads above should print the same
kaf24@1452 315 * numbers. If the second one is different, then we
kaf24@1452 316 * poke at a non-APIC.
kaf24@1452 317 */
kaf24@1452 318 if (reg1 != reg0)
kaf24@1452 319 return 0;
kaf24@1452 320
kaf24@1452 321 /*
kaf24@1452 322 * Check if the version looks reasonably.
kaf24@1452 323 */
kaf24@1452 324 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 325 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 326 return 0;
kaf24@1452 327 reg1 = get_maxlvt();
kaf24@1452 328 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 329 return 0;
kaf24@1452 330
kaf24@1452 331 /*
kaf24@1452 332 * The ID register is read/write in a real APIC.
kaf24@1452 333 */
kaf24@1452 334 reg0 = apic_read(APIC_ID);
kaf24@4888 335 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 336
kaf24@1452 337 /*
kaf24@1452 338 * The next two are just to see if we have sane values.
kaf24@1452 339 * They're only really relevant if we're in Virtual Wire
kaf24@1452 340 * compatibility mode, but most boxes are anymore.
kaf24@1452 341 */
kaf24@1452 342 reg0 = apic_read(APIC_LVT0);
kaf24@4888 343 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 344 reg1 = apic_read(APIC_LVT1);
kaf24@4888 345 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 346
kaf24@1452 347 return 1;
kaf24@1452 348 }
kaf24@1452 349
kaf24@1452 350 void __init sync_Arb_IDs(void)
kaf24@1452 351 {
kfraser@11541 352 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
kfraser@11541 353 And not needed on AMD */
kfraser@11541 354 if (modern_apic())
iap10@4548 355 return;
kaf24@1452 356 /*
kaf24@1452 357 * Wait for idle.
kaf24@1452 358 */
kaf24@1452 359 apic_wait_icr_idle();
kaf24@1452 360
kaf24@4888 361 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 362 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 363 | APIC_DM_INIT);
kaf24@1452 364 }
kaf24@1452 365
kaf24@1452 366 extern void __error_in_apic_c (void);
kaf24@1452 367
kaf24@4888 368 /*
kaf24@4888 369 * An initial setup of the virtual wire mode.
kaf24@4888 370 */
kaf24@1452 371 void __init init_bsp_APIC(void)
kaf24@1452 372 {
kaf24@4620 373 unsigned long value, ver;
kaf24@4620 374
kaf24@4620 375 /*
kaf24@4888 376 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 377 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 378 */
kaf24@4620 379 if (smp_found_config || !cpu_has_apic)
kaf24@4620 380 return;
kaf24@4620 381
kaf24@4620 382 value = apic_read(APIC_LVR);
kaf24@4620 383 ver = GET_APIC_VERSION(value);
kaf24@4620 384
kaf24@4620 385 /*
kaf24@4620 386 * Do not trust the local APIC being empty at bootup.
kaf24@4620 387 */
kaf24@4620 388 clear_local_APIC();
kaf24@4620 389
kaf24@4620 390 /*
kaf24@4620 391 * Enable APIC.
kaf24@4620 392 */
kaf24@4620 393 value = apic_read(APIC_SPIV);
kaf24@4620 394 value &= ~APIC_VECTOR_MASK;
kaf24@4620 395 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 396
kaf24@4620 397 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 398 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 399 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 400 else
kaf24@4620 401 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 402 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 403 apic_write_around(APIC_SPIV, value);
kaf24@4620 404
kaf24@4620 405 /*
kaf24@4620 406 * Set up the virtual wire mode.
kaf24@4620 407 */
kaf24@4620 408 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 409 value = APIC_DM_NMI;
kaf24@4620 410 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 411 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 412 apic_write_around(APIC_LVT1, value);
kaf24@1452 413 }
kaf24@1452 414
kaf24@8847 415 void __devinit setup_local_APIC(void)
kaf24@1452 416 {
iap10@4548 417 unsigned long oldvalue, value, ver, maxlvt;
kfraser@11541 418 int i, j;
iap10@4548 419
iap10@4548 420 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 421 if (esr_disable) {
iap10@4548 422 apic_write(APIC_ESR, 0);
iap10@4548 423 apic_write(APIC_ESR, 0);
iap10@4548 424 apic_write(APIC_ESR, 0);
iap10@4548 425 apic_write(APIC_ESR, 0);
iap10@4548 426 }
kaf24@1452 427
kaf24@1452 428 value = apic_read(APIC_LVR);
kaf24@1452 429 ver = GET_APIC_VERSION(value);
kaf24@1452 430
kaf24@1452 431 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 432 __error_in_apic_c();
kaf24@1452 433
iap10@4548 434 /*
iap10@4548 435 * Double-check whether this APIC is really registered.
iap10@4548 436 */
iap10@4548 437 if (!apic_id_registered())
kaf24@1452 438 BUG();
kaf24@1452 439
kaf24@1452 440 /*
kaf24@1452 441 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 442 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 443 * document number 292116). So here it goes...
kaf24@1452 444 */
iap10@4548 445 init_apic_ldr();
kaf24@1452 446
kaf24@1452 447 /*
kaf24@1452 448 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 449 * later on.
kaf24@1452 450 */
kaf24@1452 451 value = apic_read(APIC_TASKPRI);
kaf24@1452 452 value &= ~APIC_TPRI_MASK;
kaf24@1452 453 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 454
kaf24@1452 455 /*
kfraser@11541 456 * After a crash, we no longer service the interrupts and a pending
kfraser@11541 457 * interrupt from previous kernel might still have ISR bit set.
kfraser@11541 458 *
kfraser@11541 459 * Most probably by now CPU has serviced that pending interrupt and
kfraser@11541 460 * it might not have done the ack_APIC_irq() because it thought,
kfraser@11541 461 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
kfraser@11541 462 * does not clear the ISR bit and cpu thinks it has already serivced
kfraser@11541 463 * the interrupt. Hence a vector might get locked. It was noticed
kfraser@11541 464 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
kfraser@11541 465 */
kfraser@11541 466 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
kfraser@11541 467 value = apic_read(APIC_ISR + i*0x10);
kfraser@11541 468 for (j = 31; j >= 0; j--) {
kfraser@11541 469 if (value & (1<<j))
kfraser@11541 470 ack_APIC_irq();
kfraser@11541 471 }
kfraser@11541 472 }
kfraser@11541 473
kfraser@11541 474 /*
kaf24@1452 475 * Now that we are all set up, enable the APIC
kaf24@1452 476 */
kaf24@1452 477 value = apic_read(APIC_SPIV);
kaf24@1452 478 value &= ~APIC_VECTOR_MASK;
kaf24@1452 479 /*
kaf24@1452 480 * Enable APIC
kaf24@1452 481 */
kaf24@1452 482 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 483
iap10@4548 484 /*
iap10@4548 485 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 486 * certain networking cards. If high frequency interrupts are
iap10@4548 487 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 488 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 489 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 490 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 491 * away, oh well :-(
iap10@4548 492 *
iap10@4548 493 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 494 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 495 * BX chipset. ]
iap10@4548 496 */
iap10@4548 497 /*
iap10@4548 498 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 499 * frequent as it makes the interrupt distributon model be more
iap10@4548 500 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 501 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 502 */
iap10@4548 503 #if 1
kaf24@1452 504 /* Enable focus processor (bit==0) */
kaf24@1452 505 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 506 #else
iap10@4548 507 /* Disable focus processor (bit==1) */
iap10@4548 508 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 509 #endif
iap10@4548 510 /*
iap10@4548 511 * Set spurious IRQ vector
iap10@4548 512 */
kaf24@1452 513 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 514 apic_write_around(APIC_SPIV, value);
kaf24@1452 515
kaf24@1452 516 /*
kaf24@1452 517 * Set up LVT0, LVT1:
kaf24@1452 518 *
kaf24@1452 519 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 520 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 521 * we delegate interrupts to the 8259A.
kaf24@1452 522 */
kaf24@1452 523 /*
kaf24@1452 524 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 525 */
kaf24@1452 526 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 527 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 528 value = APIC_DM_EXTINT;
kaf24@4888 529 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 530 smp_processor_id());
kaf24@1452 531 } else {
kaf24@1452 532 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 533 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 534 smp_processor_id());
kaf24@1452 535 }
kaf24@1452 536 apic_write_around(APIC_LVT0, value);
kaf24@1452 537
kaf24@1452 538 /*
kaf24@1452 539 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 540 */
kaf24@1452 541 if (!smp_processor_id())
kaf24@1452 542 value = APIC_DM_NMI;
kaf24@1452 543 else
kaf24@1452 544 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 545 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 546 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 547 apic_write_around(APIC_LVT1, value);
kaf24@1452 548
iap10@4548 549 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 550 maxlvt = get_maxlvt();
kaf24@1452 551 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 552 apic_write(APIC_ESR, 0);
iap10@4548 553 oldvalue = apic_read(APIC_ESR);
kaf24@1452 554
iap10@4548 555 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 556 apic_write_around(APIC_LVTERR, value);
iap10@4548 557 /*
iap10@4548 558 * spec says clear errors after enabling vector.
iap10@4548 559 */
kaf24@1452 560 if (maxlvt > 3)
kaf24@1452 561 apic_write(APIC_ESR, 0);
kaf24@1452 562 value = apic_read(APIC_ESR);
iap10@4548 563 if (value != oldvalue)
kaf24@4888 564 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 565 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 566 oldvalue, value);
kaf24@1452 567 } else {
iap10@4548 568 if (esr_disable)
iap10@4548 569 /*
iap10@4548 570 * Something untraceble is creating bad interrupts on
iap10@4548 571 * secondary quads ... for the moment, just leave the
iap10@4548 572 * ESR disabled - we can't do anything useful with the
iap10@4548 573 * errors anyway - mbligh
iap10@4548 574 */
iap10@4548 575 printk("Leaving ESR disabled.\n");
kaf24@4888 576 else
kaf24@4888 577 printk("No ESR for 82489DX.\n");
kaf24@1452 578 }
kaf24@1452 579
kaf24@8594 580 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@8594 581 setup_apic_nmi_watchdog();
kaf24@8847 582 apic_pm_activate();
kaf24@1452 583 }
kaf24@1452 584
kfraser@15314 585 static struct {
kfraser@15314 586 int active;
kfraser@15314 587 /* r/w apic fields */
kfraser@15314 588 unsigned int apic_id;
kfraser@15314 589 unsigned int apic_taskpri;
kfraser@15314 590 unsigned int apic_ldr;
kfraser@15314 591 unsigned int apic_dfr;
kfraser@15314 592 unsigned int apic_spiv;
kfraser@15314 593 unsigned int apic_lvtt;
kfraser@15314 594 unsigned int apic_lvtpc;
kfraser@15314 595 unsigned int apic_lvt0;
kfraser@15314 596 unsigned int apic_lvt1;
kfraser@15314 597 unsigned int apic_lvterr;
kfraser@15314 598 unsigned int apic_tmict;
kfraser@15314 599 unsigned int apic_tdcr;
kfraser@15314 600 unsigned int apic_thmr;
kfraser@15314 601 } apic_pm_state;
kfraser@15314 602
kfraser@15314 603 int lapic_suspend(void)
kfraser@15314 604 {
kfraser@15314 605 unsigned long flags;
kfraser@15314 606
kfraser@15314 607 if (!apic_pm_state.active)
kfraser@15314 608 return 0;
kfraser@15314 609
kfraser@15314 610 apic_pm_state.apic_id = apic_read(APIC_ID);
kfraser@15314 611 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
kfraser@15314 612 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
kfraser@15314 613 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
kfraser@15314 614 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
kfraser@15314 615 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
kfraser@15314 616 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
kfraser@15314 617 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
kfraser@15314 618 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
kfraser@15314 619 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
kfraser@15314 620 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
kfraser@15314 621 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
kfraser@15314 622 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
kfraser@15314 623
kfraser@15314 624 local_irq_save(flags);
kfraser@15314 625 disable_local_APIC();
kfraser@15314 626 local_irq_restore(flags);
kfraser@15314 627 return 0;
kfraser@15314 628 }
kfraser@15314 629
kfraser@15314 630 int lapic_resume(void)
kfraser@15314 631 {
kfraser@15314 632 unsigned int l, h;
kfraser@15314 633 unsigned long flags;
kfraser@15314 634
kfraser@15314 635 if (!apic_pm_state.active)
kfraser@15314 636 return 0;
kfraser@15314 637
kfraser@15314 638 local_irq_save(flags);
kfraser@15314 639
kfraser@15314 640 /*
kfraser@15314 641 * Make sure the APICBASE points to the right address
kfraser@15314 642 *
kfraser@15314 643 * FIXME! This will be wrong if we ever support suspend on
kfraser@15314 644 * SMP! We'll need to do this as part of the CPU restore!
kfraser@15314 645 */
kfraser@15314 646 rdmsr(MSR_IA32_APICBASE, l, h);
kfraser@15314 647 l &= ~MSR_IA32_APICBASE_BASE;
kfraser@15314 648 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
kfraser@15314 649 wrmsr(MSR_IA32_APICBASE, l, h);
kfraser@15314 650
kfraser@15314 651 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
kfraser@15314 652 apic_write(APIC_ID, apic_pm_state.apic_id);
kfraser@15314 653 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
kfraser@15314 654 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
kfraser@15314 655 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
kfraser@15314 656 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
kfraser@15314 657 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
kfraser@15314 658 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
kfraser@15314 659 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
kfraser@15314 660 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
kfraser@15314 661 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
kfraser@15314 662 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
kfraser@15314 663 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
kfraser@15314 664 apic_write(APIC_ESR, 0);
kfraser@15314 665 apic_read(APIC_ESR);
kfraser@15314 666 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
kfraser@15314 667 apic_write(APIC_ESR, 0);
kfraser@15314 668 apic_read(APIC_ESR);
kfraser@15314 669 local_irq_restore(flags);
kfraser@15314 670 return 0;
kfraser@15314 671 }
kfraser@15314 672
kfraser@15314 673
kfraser@11541 674 /*
kfraser@11541 675 * If Linux enabled the LAPIC against the BIOS default
kfraser@11541 676 * disable it down before re-entering the BIOS on shutdown.
kfraser@11541 677 * Otherwise the BIOS may get confused and not power-off.
kfraser@11541 678 * Additionally clear all LVT entries before disable_local_APIC
kfraser@11541 679 * for the case where Linux didn't enable the LAPIC.
kfraser@11541 680 */
kfraser@11541 681 void lapic_shutdown(void)
kfraser@11541 682 {
kfraser@11541 683 unsigned long flags;
kfraser@11541 684
kfraser@11541 685 if (!cpu_has_apic)
kfraser@11541 686 return;
kfraser@11541 687
kfraser@11541 688 local_irq_save(flags);
kfraser@11541 689 clear_local_APIC();
kfraser@11541 690
kfraser@11541 691 if (enabled_via_apicbase)
kfraser@11541 692 disable_local_APIC();
kfraser@11541 693
kfraser@11541 694 local_irq_restore(flags);
kfraser@11541 695 }
kfraser@11541 696
kfraser@15314 697 static void apic_pm_activate(void)
kfraser@15314 698 {
kfraser@15314 699 apic_pm_state.active = 1;
kfraser@15314 700 }
kaf24@8847 701
kaf24@1452 702 /*
kaf24@1452 703 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 704 * Original code written by Keir Fraser.
kaf24@1452 705 */
kaf24@1452 706
kaf24@5211 707 static void __init lapic_disable(char *str)
kaf24@5211 708 {
kaf24@5211 709 enable_local_apic = -1;
kaf24@5211 710 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 711 }
kaf24@5211 712 custom_param("nolapic", lapic_disable);
kaf24@5211 713
kaf24@5211 714 static void __init lapic_enable(char *str)
kaf24@5211 715 {
kaf24@5211 716 enable_local_apic = 1;
kaf24@5211 717 }
kaf24@5211 718 custom_param("lapic", lapic_enable);
kaf24@5211 719
kaf24@4888 720 static void __init apic_set_verbosity(char *str)
kaf24@4888 721 {
kaf24@4888 722 if (strcmp("debug", str) == 0)
kaf24@4888 723 apic_verbosity = APIC_DEBUG;
kaf24@4888 724 else if (strcmp("verbose", str) == 0)
kaf24@4888 725 apic_verbosity = APIC_VERBOSE;
kaf24@5211 726 else
kaf24@5211 727 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@5211 728 " use apic_verbosity=verbose or apic_verbosity=debug", str);
kaf24@4888 729 }
kaf24@5211 730 custom_param("apic_verbosity", apic_set_verbosity);
kaf24@4888 731
kaf24@1452 732 static int __init detect_init_APIC (void)
kaf24@1452 733 {
kaf24@1452 734 u32 h, l, features;
kaf24@1452 735
kaf24@5211 736 /* Disabled by kernel option? */
kaf24@5211 737 if (enable_local_apic < 0)
kaf24@5211 738 return -1;
kaf24@5211 739
kaf24@1452 740 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 741 case X86_VENDOR_AMD:
iap10@4548 742 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
keir@16093 743 (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
kaf24@1452 744 break;
kaf24@1452 745 goto no_apic;
kaf24@1452 746 case X86_VENDOR_INTEL:
iap10@4548 747 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 748 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 749 break;
kaf24@1452 750 goto no_apic;
kaf24@1452 751 default:
kaf24@1452 752 goto no_apic;
kaf24@1452 753 }
kaf24@1452 754
kaf24@1452 755 if (!cpu_has_apic) {
kaf24@1452 756 /*
kaf24@5211 757 * Over-ride BIOS and try to enable the local
kaf24@5211 758 * APIC only if "lapic" specified.
kaf24@5211 759 */
kaf24@5211 760 if (enable_local_apic <= 0) {
kaf24@5211 761 printk("Local APIC disabled by BIOS -- "
kaf24@5211 762 "you can enable it with \"lapic\"\n");
kaf24@5211 763 return -1;
kaf24@5211 764 }
kaf24@5211 765 /*
kaf24@1452 766 * Some BIOSes disable the local APIC in the
kaf24@1452 767 * APIC_BASE MSR. This can only be done in
iap10@4548 768 * software for Intel P6 or later and AMD K7
iap10@4548 769 * (Model > 1) or later.
kaf24@1452 770 */
kaf24@1452 771 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 772 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 773 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 774 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 775 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 776 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 777 enabled_via_apicbase = 1;
kaf24@1452 778 }
kaf24@1452 779 }
kaf24@4888 780 /*
kaf24@4888 781 * The APIC feature bit should now be enabled
kaf24@4888 782 * in `cpuid'
kaf24@4888 783 */
kaf24@1452 784 features = cpuid_edx(1);
kaf24@1452 785 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 786 printk("Could not enable APIC!\n");
kaf24@1452 787 return -1;
kaf24@1452 788 }
kaf24@4619 789
iap10@4548 790 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 791 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 792
kaf24@1452 793 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 794 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 795 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 796 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 797
kaf24@4619 798 if (nmi_watchdog != NMI_NONE)
kaf24@4619 799 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 800
kaf24@1452 801 printk("Found and enabled local APIC!\n");
iap10@4548 802
kaf24@8847 803 apic_pm_activate();
kaf24@8847 804
kaf24@1452 805 return 0;
kaf24@1452 806
iap10@4548 807 no_apic:
kaf24@1452 808 printk("No local APIC present or hardware disabled\n");
kaf24@1452 809 return -1;
kaf24@1452 810 }
kaf24@1452 811
kaf24@1452 812 void __init init_apic_mappings(void)
kaf24@1452 813 {
iap10@4548 814 unsigned long apic_phys;
kaf24@1452 815
kaf24@1452 816 /*
iap10@4548 817 * If no local APIC can be found then set up a fake all
iap10@4548 818 * zeroes page to simulate the local APIC and another
iap10@4548 819 * one for the IO-APIC.
kaf24@1452 820 */
kaf24@9582 821 if (!smp_found_config && detect_init_APIC()) {
kaf24@5398 822 apic_phys = __pa(alloc_xenheap_page());
kfraser@15405 823 clear_page(__va(apic_phys));
kaf24@9582 824 } else
kaf24@1452 825 apic_phys = mp_lapic_addr;
kaf24@1452 826
kaf24@1452 827 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 828 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 829 apic_phys);
kaf24@1452 830
kaf24@1452 831 /*
kaf24@1452 832 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 833 * default configuration (or the MP table is broken).
kaf24@1452 834 */
kaf24@1452 835 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 836 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 837
kaf24@1452 838 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 839 {
iap10@4548 840 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 841 int i;
kaf24@1452 842
kaf24@1452 843 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 844 if (smp_found_config) {
kaf24@1452 845 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 846 if (!ioapic_phys) {
iap10@4548 847 printk(KERN_ERR
iap10@4548 848 "WARNING: bogus zero IO-APIC "
iap10@4548 849 "address found in MPTABLE, "
iap10@4548 850 "disabling IO/APIC support!\n");
iap10@4548 851 smp_found_config = 0;
iap10@4548 852 skip_ioapic_setup = 1;
iap10@4548 853 goto fake_ioapic_page;
iap10@4548 854 }
iap10@4548 855 } else {
iap10@4548 856 fake_ioapic_page:
kaf24@5398 857 ioapic_phys = __pa(alloc_xenheap_page());
kfraser@15405 858 clear_page(__va(ioapic_phys));
iap10@4548 859 }
kaf24@1452 860 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 861 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 862 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 863 idx++;
kaf24@1452 864 }
kaf24@1452 865 }
kaf24@1452 866 #endif
kaf24@1452 867 }
kaf24@1452 868
kaf24@1452 869 /*****************************************************************************
kaf24@1452 870 * APIC calibration
kaf24@1452 871 *
kaf24@1452 872 * The APIC is programmed in bus cycles.
kaf24@1452 873 * Timeout values should specified in real time units.
kaf24@1452 874 * The "cheapest" time source is the cyclecounter.
kaf24@1452 875 *
kaf24@1452 876 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 877 *
kaf24@1452 878 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 879 * timer chip to generate periodic timer interupts.
kaf24@1452 880 *****************************************************************************/
kaf24@1452 881
kaf24@1452 882 /* used for system time scaling */
kaf24@1672 883 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 884 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 885 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 886
kaf24@1452 887 /*
kaf24@1452 888 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 889 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 890 * to calibrate.
kaf24@1452 891 */
kaf24@1452 892 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 893 {
kaf24@1452 894 /*extern spinlock_t i8253_lock;*/
kaf24@1452 895 /*unsigned long flags;*/
iap10@4548 896
kaf24@1452 897 unsigned int count;
iap10@4548 898
kaf24@1452 899 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 900
iap10@4548 901 outb_p(0x00, PIT_MODE);
iap10@4548 902 count = inb_p(PIT_CH0);
iap10@4548 903 count |= inb_p(PIT_CH0) << 8;
iap10@4548 904
kaf24@1452 905 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 906
kaf24@1452 907 return count;
kaf24@1452 908 }
kaf24@1452 909
iap10@4548 910 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 911 static void __init wait_8254_wraparound(void)
kaf24@1452 912 {
kaf24@4888 913 unsigned int curr_count, prev_count;
kaf24@4888 914
kaf24@1452 915 curr_count = get_8254_timer_count();
kaf24@1452 916 do {
kaf24@1452 917 prev_count = curr_count;
kaf24@1452 918 curr_count = get_8254_timer_count();
iap10@4548 919
kaf24@4888 920 /* workaround for broken Mercury/Neptune */
kaf24@4888 921 if (prev_count >= curr_count + 0x100)
kaf24@4888 922 curr_count = get_8254_timer_count();
kaf24@4888 923
kaf24@4888 924 } while (prev_count >= curr_count);
kaf24@1452 925 }
kaf24@1452 926
kaf24@1452 927 /*
iap10@4548 928 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 929 * we override this later
iap10@4548 930 */
kaf24@4888 931 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 932
iap10@4548 933 /*
kaf24@1452 934 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 935 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 936 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 937 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 938 * call this function only once, with the real, calibrated value.
kaf24@1452 939 *
kaf24@1452 940 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 941 * P5 APIC double write bug.
kaf24@1452 942 */
iap10@4548 943
kaf24@1452 944 #define APIC_DIVISOR 1
iap10@4548 945
kaf24@5146 946 void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 947 {
iap10@4548 948 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 949
iap10@4548 950 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 951 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 952 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 953 if (!APIC_INTEGRATED(ver))
iap10@4548 954 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 955 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 956
kaf24@1452 957 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 958 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 959
kaf24@1452 960 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 961 }
kaf24@1452 962
kfraser@15586 963 static void __devinit setup_APIC_timer(unsigned int clocks)
kaf24@1452 964 {
kaf24@1452 965 unsigned long flags;
kaf24@5146 966 local_irq_save(flags);
kaf24@5146 967 __setup_APIC_LVTT(clocks);
kaf24@5146 968 local_irq_restore(flags);
kaf24@1452 969 }
kaf24@1452 970
kaf24@1452 971 /*
kaf24@5146 972 * In this function we calibrate APIC bus clocks to the external
kaf24@5146 973 * timer. Unfortunately we cannot use jiffies and the timer irq
kaf24@5146 974 * to calibrate, since some later bootup code depends on getting
kaf24@5146 975 * the first irq? Ugh.
kaf24@1452 976 *
kaf24@5146 977 * We want to do the calibration only once since we
kaf24@5146 978 * want to have local timer irqs syncron. CPUs connected
kaf24@5146 979 * by the same APIC bus have the very same bus frequency.
kaf24@5146 980 * And we want to have irqs off anyways, no accidental
kaf24@5146 981 * APIC irq that way.
kaf24@1452 982 */
kaf24@1452 983
kaf24@1452 984 int __init calibrate_APIC_clock(void)
kaf24@1452 985 {
kaf24@1452 986 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 987 long tt1, tt2;
kaf24@1452 988 long result;
kaf24@1452 989 int i;
kaf24@1452 990 const int LOOPS = HZ/10;
kaf24@1452 991
kaf24@4888 992 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 993
iap10@4548 994 /*
iap10@4548 995 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 996 * value into the APIC clock, we just want to get the
iap10@4548 997 * counter running for calibration.
iap10@4548 998 */
kaf24@1452 999 __setup_APIC_LVTT(1000000000);
kaf24@1452 1000
iap10@4548 1001 /*
iap10@4548 1002 * The timer chip counts down to zero. Let's wait
kaf24@1452 1003 * for a wraparound to start exact measurement:
iap10@4548 1004 * (the current tick might have been already half done)
iap10@4548 1005 */
iap10@4548 1006 wait_timer_tick();
iap10@4548 1007
iap10@4548 1008 /*
iap10@4548 1009 * We wrapped around just now. Let's start:
iap10@4548 1010 */
iap10@4548 1011 if (cpu_has_tsc)
kaf24@4619 1012 rdtscll(t1);
kaf24@1452 1013 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 1014
iap10@4548 1015 /*
iap10@4548 1016 * Let's wait LOOPS wraprounds:
iap10@4548 1017 */
kaf24@1452 1018 for (i = 0; i < LOOPS; i++)
iap10@4548 1019 wait_timer_tick();
kaf24@1452 1020
kaf24@1452 1021 tt2 = apic_read(APIC_TMCCT);
iap10@4548 1022 if (cpu_has_tsc)
kaf24@4619 1023 rdtscll(t2);
kaf24@1452 1024
iap10@4548 1025 /*
iap10@4548 1026 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 1027 * might have overflown, but note that we use signed
kaf24@1452 1028 * longs, thus no extra care needed.
kaf24@4888 1029 *
kaf24@4888 1030 * underflown to be exact, as the timer counts down ;)
iap10@4548 1031 */
iap10@4548 1032
kaf24@1452 1033 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 1034
iap10@4548 1035 if (cpu_has_tsc)
kaf24@4888 1036 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 1037 "%ld.%04ld MHz.\n",
kaf24@4888 1038 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 1039 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 1040
kaf24@4888 1041 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kfraser@11204 1042 "%ld.%04ld MHz.\n",
kfraser@11204 1043 result/(1000000/HZ),
kfraser@11204 1044 result%(1000000/HZ));
kaf24@1452 1045
kaf24@1452 1046 /* set up multipliers for accurate timer code */
kaf24@1452 1047 bus_freq = result*HZ;
kaf24@1452 1048 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 1049 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 1050
kaf24@4888 1051 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 1052 /* reset APIC to zero timeout value */
kaf24@1452 1053 __setup_APIC_LVTT(0);
iap10@4548 1054
kaf24@1452 1055 return result;
kaf24@1452 1056 }
kaf24@1452 1057
kaf24@9184 1058 u32 get_apic_bus_cycle(void)
kaf24@7546 1059 {
kaf24@9184 1060 return bus_cycle;
kaf24@7546 1061 }
kaf24@5146 1062
kaf24@5146 1063 static unsigned int calibration_result;
kaf24@5146 1064
kaf24@5146 1065 void __init setup_boot_APIC_clock(void)
kaf24@1452 1066 {
kaf24@8847 1067 unsigned long flags;
kaf24@5146 1068 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
kaf24@1452 1069 using_apic_timer = 1;
kaf24@5146 1070
kaf24@8847 1071 local_irq_save(flags);
kaf24@8847 1072
kaf24@5146 1073 calibration_result = calibrate_APIC_clock();
kaf24@5146 1074 /*
kaf24@5146 1075 * Now set up the timer for real.
kaf24@5146 1076 */
kaf24@5146 1077 setup_APIC_timer(calibration_result);
kaf24@5146 1078
kaf24@8847 1079 local_irq_restore(flags);
kaf24@5146 1080 }
kaf24@5146 1081
kaf24@8847 1082 void __devinit setup_secondary_APIC_clock(void)
kaf24@5146 1083 {
kaf24@5146 1084 setup_APIC_timer(calibration_result);
kaf24@5146 1085 }
kaf24@5146 1086
kaf24@8847 1087 void disable_APIC_timer(void)
kaf24@5146 1088 {
kaf24@5146 1089 if (using_apic_timer) {
kaf24@5146 1090 unsigned long v;
kaf24@5146 1091
kaf24@5146 1092 v = apic_read(APIC_LVTT);
kaf24@5146 1093 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@5146 1094 }
kaf24@5146 1095 }
kaf24@5146 1096
kaf24@5146 1097 void enable_APIC_timer(void)
kaf24@5146 1098 {
kaf24@5146 1099 if (using_apic_timer) {
kaf24@5146 1100 unsigned long v;
kaf24@5146 1101
kaf24@5146 1102 v = apic_read(APIC_LVTT);
kaf24@5146 1103 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
kaf24@5146 1104 }
kaf24@1452 1105 }
kaf24@1452 1106
kaf24@1452 1107 #undef APIC_DIVISOR
kaf24@1452 1108
kaf24@1452 1109 /*
kaf24@1452 1110 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 1111 * returns 1 on success
kaf24@1452 1112 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 1113 */
kaf24@8586 1114 int reprogram_timer(s_time_t timeout)
kaf24@1452 1115 {
kaf24@1452 1116 s_time_t now;
kaf24@1452 1117 s_time_t expire;
kaf24@1452 1118 u64 apic_tmict;
kaf24@1452 1119
kaf24@1452 1120 /*
kfraser@14340 1121 * If we don't have local APIC then we just poll the timer list off the
kfraser@14340 1122 * PIT interrupt.
kfraser@14340 1123 */
kfraser@14340 1124 if ( !cpu_has_apic )
kfraser@14340 1125 return 1;
kfraser@14340 1126
kfraser@14340 1127 /*
kaf24@1452 1128 * We use this value because we don't trust zero (we think it may just
kaf24@1452 1129 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 1130 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 1131 */
kaf24@1452 1132 if ( timeout == 0 )
kaf24@1452 1133 {
kaf24@1452 1134 apic_tmict = 0xffffffff;
kaf24@1452 1135 goto reprogram;
kaf24@1452 1136 }
kaf24@1452 1137
kaf24@1452 1138 now = NOW();
kaf24@1452 1139 expire = timeout - now; /* value from now */
kaf24@1452 1140
kaf24@1452 1141 if ( expire <= 0 )
kaf24@1452 1142 {
kaf24@1452 1143 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 1144 smp_processor_id(), (u32)(now>>32),
kaf24@1452 1145 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 1146 return 0;
kaf24@1452 1147 }
kaf24@1452 1148
kaf24@1452 1149 /* conversion to bus units */
kaf24@1452 1150 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 1151
kaf24@1452 1152 if ( apic_tmict >= 0xffffffff )
kaf24@1452 1153 {
kaf24@1452 1154 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 1155 apic_tmict = 0xffffffff;
kaf24@1452 1156 }
kaf24@1452 1157
kaf24@1452 1158 if ( apic_tmict == 0 )
kaf24@1452 1159 {
kaf24@1452 1160 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 1161 return 0;
kaf24@1452 1162 }
kaf24@1452 1163
kaf24@1452 1164 reprogram:
kaf24@1452 1165 /* Program the timer. */
kaf24@1452 1166 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 1167
kaf24@1452 1168 return 1;
kaf24@1452 1169 }
kaf24@1452 1170
kaf24@8846 1171 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 1172 {
kaf24@1452 1173 ack_APIC_irq();
kfraser@14595 1174 perfc_incr(apic_timer);
kaf24@8586 1175 raise_softirq(TIMER_SOFTIRQ);
kaf24@1452 1176 }
kaf24@1452 1177
kaf24@1452 1178 /*
kaf24@1452 1179 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 1180 */
kaf24@8846 1181 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1182 {
kaf24@1452 1183 unsigned long v;
kaf24@1452 1184
kaf24@8847 1185 irq_enter();
kaf24@1452 1186 /*
kaf24@1452 1187 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 1188 * if it is a vectored one. Just in case...
kaf24@1452 1189 * Spurious interrupts should not be ACKed.
kaf24@1452 1190 */
kaf24@1452 1191 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 1192 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 1193 ack_APIC_irq();
kaf24@1452 1194
kaf24@1452 1195 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@5146 1196 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 1197 smp_processor_id());
kaf24@8847 1198 irq_exit();
kaf24@1452 1199 }
kaf24@1452 1200
kaf24@1452 1201 /*
kaf24@1452 1202 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 1203 */
kaf24@1452 1204
kaf24@8846 1205 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1206 {
kaf24@1452 1207 unsigned long v, v1;
kaf24@1452 1208
kaf24@8847 1209 irq_enter();
kaf24@1452 1210 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 1211 v = apic_read(APIC_ESR);
kaf24@1452 1212 apic_write(APIC_ESR, 0);
kaf24@1452 1213 v1 = apic_read(APIC_ESR);
kaf24@1452 1214 ack_APIC_irq();
kaf24@1452 1215 atomic_inc(&irq_err_count);
kaf24@1452 1216
kaf24@1452 1217 /* Here is what the APIC error bits mean:
kaf24@1452 1218 0: Send CS error
kaf24@1452 1219 1: Receive CS error
kaf24@1452 1220 2: Send accept error
kaf24@1452 1221 3: Receive accept error
kaf24@1452 1222 4: Reserved
kaf24@1452 1223 5: Send illegal vector
kaf24@1452 1224 6: Received illegal vector
kaf24@1452 1225 7: Illegal register address
kaf24@1452 1226 */
kaf24@5146 1227 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@5146 1228 smp_processor_id(), v , v1);
kaf24@8847 1229 irq_exit();
kaf24@1452 1230 }
kaf24@1452 1231
kaf24@1452 1232 /*
keir@16940 1233 * This interrupt handles performance counters interrupt
keir@16940 1234 */
keir@16940 1235
keir@16940 1236 fastcall void smp_pmu_apic_interrupt(struct cpu_user_regs *regs)
keir@16940 1237 {
keir@16940 1238 ack_APIC_irq();
keir@16940 1239 hvm_do_pmu_interrupt(regs);
keir@16940 1240 }
keir@16940 1241
keir@16940 1242 /*
kaf24@1452 1243 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 1244 * a UP kernel.
kaf24@1452 1245 */
kaf24@1452 1246 int __init APIC_init_uniprocessor (void)
kaf24@1452 1247 {
kaf24@5211 1248 if (enable_local_apic < 0)
kaf24@5211 1249 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 1250
kaf24@1452 1251 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 1252 return -1;
kaf24@1452 1253
kaf24@1452 1254 /*
kaf24@1452 1255 * Complain if the BIOS pretends there is one.
kaf24@1452 1256 */
iap10@4548 1257 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 1258 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 1259 boot_cpu_physical_apicid);
kfraser@11541 1260 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 1261 return -1;
kaf24@1452 1262 }
kaf24@1452 1263
kaf24@1452 1264 verify_local_APIC();
kaf24@1452 1265
kaf24@1452 1266 connect_bsp_APIC();
kaf24@1452 1267
kfraser@11541 1268 /*
kfraser@11541 1269 * Hack: In case of kdump, after a crash, kernel might be booting
kfraser@11541 1270 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
kfraser@11541 1271 * might be zero if read from MP tables. Get it from LAPIC.
kfraser@11541 1272 */
kfraser@11541 1273 #ifdef CONFIG_CRASH_DUMP
kfraser@11541 1274 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kfraser@11541 1275 #endif
kaf24@4804 1276 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 1277
kaf24@1452 1278 setup_local_APIC();
kaf24@1452 1279
kaf24@5146 1280 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@5146 1281 check_nmi_watchdog();
kaf24@1452 1282 #ifdef CONFIG_X86_IO_APIC
iap10@4548 1283 if (smp_found_config)
iap10@4548 1284 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 1285 setup_IO_APIC();
iap10@4548 1286 #endif
kaf24@5146 1287 setup_boot_APIC_clock();
kaf24@1452 1288
kaf24@1452 1289 return 0;
kaf24@1452 1290 }