ia64/xen-unstable

annotate xen/arch/ia64/vmx/vmx_minstate.h @ 16758:5ab3288e5b0f

[IA64] vti fault handler clean up: introduce VMX_SAVE_MIN_WITH_COVER_NO_PANIC

For later use. This is a version of VMX_SAVE_MIN_WITH_COVER which
doesn't call vmx_panic even when p6 is true.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Fri Dec 14 13:40:29 2007 -0700 (2007-12-14)
parents 9ab95900afec
children 6cf504b4de7d
rev   line source
djm@6458 1 /*
djm@6458 2 * vmx_minstate.h:
djm@6458 3 * Copyright (c) 2005, Intel Corporation.
djm@6458 4 *
djm@6458 5 * This program is free software; you can redistribute it and/or modify it
djm@6458 6 * under the terms and conditions of the GNU General Public License,
djm@6458 7 * version 2, as published by the Free Software Foundation.
djm@6458 8 *
djm@6458 9 * This program is distributed in the hope it will be useful, but WITHOUT
djm@6458 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
djm@6458 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
djm@6458 12 * more details.
djm@6458 13 *
djm@6458 14 * You should have received a copy of the GNU General Public License along with
djm@6458 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
djm@6458 16 * Place - Suite 330, Boston, MA 02111-1307 USA.
djm@6458 17 *
djm@6458 18 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
djm@6458 19 */
djm@6458 20
djm@6458 21 #include <linux/config.h>
djm@6458 22
djm@6458 23 #include <asm/asmmacro.h>
djm@6458 24 #include <asm/fpu.h>
djm@6458 25 #include <asm/mmu_context.h>
djm@6458 26 #include <asm/offsets.h>
djm@6458 27 #include <asm/pal.h>
djm@6458 28 #include <asm/pgtable.h>
djm@6458 29 #include <asm/processor.h>
djm@6458 30 #include <asm/ptrace.h>
djm@6458 31 #include <asm/system.h>
djm@6458 32 #include <asm/vmx_pal_vsa.h>
djm@6458 33 #include <asm/vmx_vpd.h>
djm@6458 34 #include <asm/cache.h>
djm@6458 35 #include "entry.h"
djm@6458 36
alex@16749 37 #define VMX_MINSTATE_START_SAVE_MIN \
alex@16756 38 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
alex@16756 39 ;; \
alex@16756 40 (pUStk) mov.m r28=ar.rnat; \
alex@16756 41 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
alex@16756 42 (pKStk) mov r1=sp; /* get sp */ \
alex@16756 43 ;; \
alex@16756 44 (pUStk) lfetch.fault.excl.nt1 [r22]; \
alex@16756 45 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
alex@16756 46 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
alex@16756 47 ;; \
alex@16756 48 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
alex@16756 49 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
alex@16756 50 ;; \
alex@16756 51 (pUStk) mov r18=ar.bsp; \
alex@16756 52 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
djm@6458 53
alex@16749 54 #define VMX_MINSTATE_END_SAVE_MIN \
alex@16749 55 bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
djm@6458 56 ;;
djm@6458 57
alex@16749 58 #define PAL_VSA_SYNC_READ \
alex@16749 59 /* begin to call pal vps sync_read */ \
alex@16756 60 (pUStk) add r25=IA64_VPD_BASE_OFFSET, r21; \
alex@16756 61 (pUStk) movl r20=__vsa_base; \
alex@16749 62 ;; \
alex@16756 63 (pUStk) ld8 r25=[r25]; /* read vpd base */ \
alex@16756 64 (pUStk) ld8 r20=[r20]; /* read entry point */ \
alex@16749 65 ;; \
alex@16756 66 (pUStk) add r20=PAL_VPS_SYNC_READ,r20; \
alex@16749 67 ;; \
alex@16749 68 { .mii; \
alex@16756 69 (pUStk) nop 0x0; \
alex@16756 70 (pUStk) mov r24=ip; \
alex@16756 71 (pUStk) mov b0=r20; \
alex@16749 72 ;; \
alex@16749 73 }; \
alex@16749 74 { .mmb; \
alex@16756 75 (pUStk) add r24 = 0x20, r24; \
alex@16756 76 (pUStk) nop 0x0; \
alex@16756 77 (pUStk) br.cond.sptk b0; /* call the service */ \
alex@16749 78 ;; \
alex@16749 79 };
djm@6458 80
djm@6458 81 #define IA64_CURRENT_REG IA64_KR(CURRENT) /* r21 is reserved for current pointer */
djm@6458 82 //#define VMX_MINSTATE_GET_CURRENT(reg) mov reg=IA64_CURRENT_REG
djm@6458 83 #define VMX_MINSTATE_GET_CURRENT(reg) mov reg=r21
djm@6458 84
djm@6458 85 /*
djm@6458 86 * VMX_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
djm@6458 87 * the minimum state necessary that allows us to turn psr.ic back
djm@6458 88 * on.
djm@6458 89 *
djm@6458 90 * Assumed state upon entry:
djm@6458 91 * psr.ic: off
djm@6458 92 * r31: contains saved predicates (pr)
djm@6458 93 *
djm@6458 94 * Upon exit, the state is as follows:
djm@6458 95 * psr.ic: off
djm@6458 96 * r2 = points to &pt_regs.r16
djm@6458 97 * r8 = contents of ar.ccv
djm@6458 98 * r9 = contents of ar.csd
djm@6458 99 * r10 = contents of ar.ssd
djm@6458 100 * r11 = FPSR_DEFAULT
djm@6458 101 * r12 = kernel sp (kernel virtual address)
djm@6458 102 * r13 = points to current task_struct (kernel virtual address)
alex@16757 103 * p6 = (psr.vm || isr.ni)
alex@16757 104 * panic if not external interrupt (fault in xen VMM)
djm@6458 105 * p15 = TRUE if psr.i is set in cr.ipsr
djm@6458 106 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
djm@6458 107 * preserved
djm@6458 108 *
djm@6458 109 * Note that psr.ic is NOT turned on by this macro. This is so that
djm@6458 110 * we can pass interruption state as arguments to a handler.
djm@6458 111 */
djm@6469 112
alex@16757 113 #ifdef CONFIG_VMX_PANIC
alex@16757 114 # define P6_BR_VMX_PANIC (p6)br.spnt.few vmx_panic;
alex@16757 115 #else
alex@16757 116 # define P6_BR_VMX_PANIC /* nothing */
alex@16757 117 #endif
alex@16757 118
alex@16757 119 #define P6_BR_CALL_PANIC(panic_string) \
alex@16757 120 (p6) movl out0=panic_string; \
alex@16757 121 (p6) br.call.spnt.few b6=panic;
alex@16757 122
alex@16758 123 #define VMX_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA,VMX_PANIC) \
alex@16749 124 mov r27=ar.rsc; /* M */ \
alex@16749 125 mov r20=r1; /* A */ \
alex@16749 126 mov r25=ar.unat; /* M */ \
alex@16749 127 mov r29=cr.ipsr; /* M */ \
alex@16749 128 mov r26=ar.pfs; /* I */ \
alex@16749 129 mov r18=cr.isr; \
alex@16749 130 COVER; /* B;; (or nothing) */ \
alex@16749 131 ;; \
alex@16756 132 cmp.eq p6,p0=r0,r0; \
alex@16756 133 tbit.z pKStk,pUStk=r29,IA64_PSR_VM_BIT; \
alex@16756 134 tbit.z p0,p15=r29,IA64_PSR_I_BIT; \
alex@16749 135 ;; \
alex@16756 136 (pUStk) tbit.nz.and p6,p0=r18,IA64_ISR_NI_BIT; \
alex@16756 137 (pUStk)VMX_MINSTATE_GET_CURRENT(r1); \
alex@16758 138 VMX_PANIC \
alex@16749 139 /* switch from user to kernel RBS: */ \
alex@16749 140 ;; \
alex@16749 141 invala; /* M */ \
alex@16749 142 SAVE_IFS; \
alex@16749 143 ;; \
alex@16749 144 VMX_MINSTATE_START_SAVE_MIN \
alex@16749 145 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
alex@16749 146 adds r16=PT(CR_IPSR),r1; \
alex@16749 147 ;; \
alex@16749 148 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
alex@16749 149 st8 [r16]=r29; /* save cr.ipsr */ \
alex@16749 150 ;; \
alex@16749 151 lfetch.fault.excl.nt1 [r17]; \
alex@16749 152 mov r29=b0 \
alex@16749 153 ;; \
alex@16749 154 adds r16=PT(R8),r1; /* initialize first base pointer */ \
alex@16749 155 adds r17=PT(R9),r1; /* initialize second base pointer */ \
alex@16756 156 (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \
alex@16749 157 ;; \
alex@16749 158 .mem.offset 0,0; st8.spill [r16]=r8,16; \
alex@16749 159 .mem.offset 8,0; st8.spill [r17]=r9,16; \
alex@16749 160 ;; \
alex@16749 161 .mem.offset 0,0; st8.spill [r16]=r10,24; \
alex@16749 162 .mem.offset 8,0; st8.spill [r17]=r11,24; \
alex@16749 163 ;; \
alex@16749 164 mov r9=cr.iip; /* M */ \
alex@16749 165 mov r10=ar.fpsr; /* M */ \
alex@16749 166 ;; \
alex@16749 167 st8 [r16]=r9,16; /* save cr.iip */ \
alex@16749 168 st8 [r17]=r30,16; /* save cr.ifs */ \
alex@16756 169 (pUStk) sub r18=r18,r22;/* r18=RSE.ndirty*8 */ \
alex@16749 170 ;; \
alex@16749 171 st8 [r16]=r25,16; /* save ar.unat */ \
alex@16749 172 st8 [r17]=r26,16; /* save ar.pfs */ \
alex@16749 173 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
alex@16749 174 ;; \
alex@16749 175 st8 [r16]=r27,16; /* save ar.rsc */ \
alex@16756 176 (pUStk) st8 [r17]=r28,16;/* save ar.rnat */ \
alex@16756 177 (pKStk) adds r17=16,r17;/* skip over ar_rnat field */ \
alex@16749 178 ;; /* avoid RAW on r16 & r17 */ \
alex@16756 179 (pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \
alex@16749 180 st8 [r17]=r31,16; /* save predicates */ \
alex@16756 181 (pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \
alex@16749 182 ;; \
alex@16749 183 st8 [r16]=r29,16; /* save b0 */ \
alex@16749 184 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
alex@16749 185 cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \
alex@16749 186 ;; \
alex@16749 187 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
alex@16749 188 .mem.offset 8,0; st8.spill [r17]=r12,16; \
djm@6458 189 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
alex@16749 190 ;; \
alex@16749 191 .mem.offset 0,0; st8.spill [r16]=r13,16; \
alex@16749 192 .mem.offset 8,0; st8.spill [r17]=r10,16; /* save ar.fpsr */ \
alex@16756 193 (pUStk) VMX_MINSTATE_GET_CURRENT(r13); /* establish `current' */ \
alex@16756 194 (pKStk) movl r13=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;/* From MINSTATE_GET_CURRENT */\
alex@16749 195 ;; \
alex@16749 196 .mem.offset 0,0; st8.spill [r16]=r15,16; \
alex@16749 197 .mem.offset 8,0; st8.spill [r17]=r14,16; \
alex@16756 198 (pKStk) ld8 r13=[r13]; /* establish `current' */ \
alex@16749 199 ;; \
alex@16749 200 .mem.offset 0,0; st8.spill [r16]=r2,16; \
alex@16749 201 .mem.offset 8,0; st8.spill [r17]=r3,16; \
alex@16749 202 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
alex@16749 203 ;; \
alex@16756 204 (pUStk) adds r16=IA64_VCPU_IIPA_OFFSET,r13; \
alex@16756 205 (pUStk) adds r17=IA64_VCPU_ISR_OFFSET,r13; \
alex@16756 206 (pUStk) mov r26=cr.iipa; \
alex@16756 207 (pUStk) mov r27=cr.isr; \
alex@16749 208 ;; \
alex@16756 209 (pUStk) st8 [r16]=r26; \
alex@16756 210 (pUStk) st8 [r17]=r27; \
alex@16749 211 ;; \
alex@16749 212 EXTRA; \
alex@16749 213 mov r8=ar.ccv; \
alex@16749 214 mov r9=ar.csd; \
alex@16749 215 mov r10=ar.ssd; \
alex@16749 216 movl r11=FPSR_DEFAULT; /* L-unit */ \
alex@16749 217 movl r1=__gp; /* establish kernel global pointer */ \
alex@16749 218 ;; \
alex@16749 219 PAL_VSA_SYNC_READ \
djm@6458 220 VMX_MINSTATE_END_SAVE_MIN
djm@6458 221
djm@6458 222 /*
djm@6458 223 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
djm@6458 224 *
djm@6458 225 * Assumed state upon entry:
djm@6458 226 * psr.ic: on
djm@6458 227 * r2: points to &pt_regs.f6
djm@6458 228 * r3: points to &pt_regs.f7
djm@6867 229 * r8: contents of ar.ccv
djm@6458 230 * r9: contents of ar.csd
djm@6458 231 * r10: contents of ar.ssd
djm@6458 232 * r11: FPSR_DEFAULT
djm@6458 233 *
djm@6458 234 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
djm@6458 235 */
alex@16749 236 #define VMX_SAVE_REST \
alex@16749 237 .mem.offset 0,0; st8.spill [r2]=r16,16; \
alex@16749 238 .mem.offset 8,0; st8.spill [r3]=r17,16; \
alex@16749 239 ;; \
alex@16749 240 .mem.offset 0,0; st8.spill [r2]=r18,16; \
alex@16749 241 .mem.offset 8,0; st8.spill [r3]=r19,16; \
alex@16749 242 ;; \
alex@16749 243 .mem.offset 0,0; st8.spill [r2]=r20,16; \
alex@16749 244 .mem.offset 8,0; st8.spill [r3]=r21,16; \
alex@16749 245 mov r18=b6; \
alex@16749 246 ;; \
alex@16749 247 .mem.offset 0,0; st8.spill [r2]=r22,16; \
alex@16749 248 .mem.offset 8,0; st8.spill [r3]=r23,16; \
alex@16749 249 mov r19=b7; \
alex@16749 250 ;; \
alex@16749 251 .mem.offset 0,0; st8.spill [r2]=r24,16; \
alex@16749 252 .mem.offset 8,0; st8.spill [r3]=r25,16; \
alex@16749 253 ;; \
alex@16749 254 .mem.offset 0,0; st8.spill [r2]=r26,16; \
alex@16749 255 .mem.offset 8,0; st8.spill [r3]=r27,16; \
alex@16749 256 ;; \
alex@16749 257 .mem.offset 0,0; st8.spill [r2]=r28,16; \
alex@16749 258 .mem.offset 8,0; st8.spill [r3]=r29,16; \
alex@16749 259 ;; \
alex@16749 260 .mem.offset 0,0; st8.spill [r2]=r30,16; \
alex@16749 261 .mem.offset 8,0; st8.spill [r3]=r31,32; \
alex@16749 262 ;; \
alex@16749 263 mov ar.fpsr=r11; \
alex@16749 264 st8 [r2]=r8,8; \
alex@16749 265 adds r24=PT(B6)-PT(F7),r3; \
alex@16749 266 ;; \
alex@16749 267 stf.spill [r2]=f6,32; \
alex@16749 268 stf.spill [r3]=f7,32; \
alex@16749 269 ;; \
alex@16749 270 stf.spill [r2]=f8,32; \
alex@16749 271 stf.spill [r3]=f9,32; \
alex@16749 272 ;; \
alex@16749 273 stf.spill [r2]=f10,32; \
alex@16749 274 stf.spill [r3]=f11; \
alex@16749 275 adds r25=PT(B7)-PT(F11),r3; \
alex@16749 276 ;; \
alex@16749 277 st8 [r24]=r18,16; /* b6 */ \
alex@16749 278 st8 [r25]=r19,16; /* b7 */ \
alex@16749 279 adds r3=PT(R5)-PT(F11),r3; \
alex@16749 280 ;; \
alex@16749 281 st8 [r24]=r9; /* ar.csd */ \
alex@16749 282 st8 [r25]=r10; /* ar.ssd */ \
alex@16749 283 ;; \
alex@16756 284 (pUStk)mov r18=ar.unat; \
alex@16756 285 (pUStk)adds r19=PT(EML_UNAT)-PT(R4),r2; \
alex@16749 286 ;; \
alex@16756 287 (pUStk)st8 [r19]=r18; /* eml_unat */
awilliam@10871 288
alex@16749 289 #define VMX_SAVE_EXTRA \
alex@16749 290 .mem.offset 0,0; st8.spill [r2]=r4,16; \
alex@16749 291 .mem.offset 8,0; st8.spill [r3]=r5,16; \
alex@16749 292 ;; \
alex@16749 293 .mem.offset 0,0; st8.spill [r2]=r6,16; \
alex@16749 294 .mem.offset 8,0; st8.spill [r3]=r7; \
alex@16749 295 ;; \
alex@16749 296 mov r26=ar.unat; \
alex@16749 297 ;; \
alex@16749 298 st8 [r2]=r26; /* eml_unat */
awilliam@10699 299
alex@16758 300 #define VMX_SAVE_MIN_WITH_COVER VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,, P6_BR_VMX_PANIC)
alex@16758 301 #define VMX_SAVE_MIN_WITH_COVER_NO_PANIC \
alex@16758 302 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,, )
alex@16758 303 #define VMX_SAVE_MIN_WITH_COVER_R19 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19, P6_BR_VMX_PANIC)
alex@16758 304 #define VMX_SAVE_MIN VMX_DO_SAVE_MIN( , mov r30=r0,, P6_BR_VMX_PANIC)
djm@6458 305
alex@16749 306 /*
alex@16749 307 * Local variables:
alex@16749 308 * mode: C
alex@16749 309 * c-set-style: "BSD"
alex@16749 310 * c-basic-offset: 4
alex@16749 311 * tab-width: 4
alex@16749 312 * indent-tabs-mode: nil
alex@16749 313 * End:
alex@16749 314 */