ia64/xen-unstable

annotate xen/include/asm-x86/msr.h @ 15708:52e5c110aadb

[HVM] Yet another MCA/MCE MSR.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Fri Aug 03 12:10:35 2007 +0100 (2007-08-03)
parents 912f7e312ec2
children 9554ec3e27cd
rev   line source
kaf24@1452 1 #ifndef __ASM_MSR_H
kaf24@1452 2 #define __ASM_MSR_H
kaf24@1452 3
kaf24@8255 4 #ifndef __ASSEMBLY__
kaf24@8255 5
kfraser@15105 6 #include <xen/smp.h>
kfraser@15105 7 #include <xen/percpu.h>
kfraser@15105 8
kaf24@1452 9 #define rdmsr(msr,val1,val2) \
kaf24@1452 10 __asm__ __volatile__("rdmsr" \
kaf24@1452 11 : "=a" (val1), "=d" (val2) \
kaf24@1452 12 : "c" (msr))
kaf24@1452 13
arun@4587 14 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
arun@4587 15 __asm__ __volatile__("rdmsr" \
arun@4587 16 : "=a" (a__), "=d" (b__) \
arun@4587 17 : "c" (msr)); \
kaf24@8465 18 val = a__ | ((u64)b__<<32); \
shand@11156 19 } while(0);
arun@4587 20
kaf24@1452 21 #define wrmsr(msr,val1,val2) \
kaf24@1452 22 __asm__ __volatile__("wrmsr" \
kaf24@1452 23 : /* no outputs */ \
kaf24@1452 24 : "c" (msr), "a" (val1), "d" (val2))
kaf24@1452 25
kaf24@8255 26 static inline void wrmsrl(unsigned int msr, __u64 val)
kaf24@8255 27 {
kaf24@8255 28 __u32 lo, hi;
kaf24@8255 29 lo = (__u32)val;
kaf24@8255 30 hi = (__u32)(val >> 32);
kaf24@8255 31 wrmsr(msr, lo, hi);
kaf24@8255 32 }
kaf24@5659 33
kaf24@8846 34 /* rdmsr with exception handling */
kaf24@8846 35 #define rdmsr_safe(msr,val1,val2) ({\
kaf24@3959 36 int _rc; \
kaf24@3861 37 __asm__ __volatile__( \
kaf24@3861 38 "1: rdmsr\n2:\n" \
kaf24@3861 39 ".section .fixup,\"ax\"\n" \
kaf24@8846 40 "3: movl %5,%2\n; jmp 2b\n" \
kaf24@3861 41 ".previous\n" \
kaf24@3861 42 ".section __ex_table,\"a\"\n" \
kaf24@3861 43 " "__FIXUP_ALIGN"\n" \
kaf24@3861 44 " "__FIXUP_WORD" 1b,3b\n" \
kaf24@3861 45 ".previous\n" \
kaf24@3959 46 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
kaf24@8846 47 : "c" (msr), "2" (0), "i" (-EFAULT)); \
kaf24@3861 48 _rc; })
kaf24@3861 49
kaf24@8846 50 /* wrmsr with exception handling */
kaf24@8846 51 #define wrmsr_safe(msr,val1,val2) ({\
kaf24@3959 52 int _rc; \
kaf24@3861 53 __asm__ __volatile__( \
kaf24@3861 54 "1: wrmsr\n2:\n" \
kaf24@3861 55 ".section .fixup,\"ax\"\n" \
kaf24@8846 56 "3: movl %5,%0\n; jmp 2b\n" \
kaf24@3861 57 ".previous\n" \
kaf24@3861 58 ".section __ex_table,\"a\"\n" \
kaf24@3861 59 " "__FIXUP_ALIGN"\n" \
kaf24@3861 60 " "__FIXUP_WORD" 1b,3b\n" \
kaf24@3861 61 ".previous\n" \
kaf24@3959 62 : "=&r" (_rc) \
kaf24@8846 63 : "c" (msr), "a" (val1), "d" (val2), "0" (0), "i" (-EFAULT)); \
kaf24@3861 64 _rc; })
kaf24@3861 65
kaf24@1452 66 #define rdtsc(low,high) \
kaf24@1452 67 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
kaf24@1452 68
kaf24@1452 69 #define rdtscl(low) \
kaf24@1452 70 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
kaf24@1452 71
kaf24@1463 72 #if defined(__i386__)
kaf24@1452 73 #define rdtscll(val) \
kaf24@1452 74 __asm__ __volatile__("rdtsc" : "=A" (val))
kaf24@1463 75 #elif defined(__x86_64__)
kaf24@1452 76 #define rdtscll(val) do { \
kaf24@1452 77 unsigned int a,d; \
kaf24@1452 78 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
kaf24@1452 79 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
kaf24@1452 80 } while(0)
kaf24@1452 81 #endif
kaf24@1452 82
kaf24@1452 83 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
kaf24@1452 84
kaf24@1452 85 #define rdpmc(counter,low,high) \
kaf24@1452 86 __asm__ __volatile__("rdpmc" \
kaf24@1452 87 : "=a" (low), "=d" (high) \
kaf24@1452 88 : "c" (counter))
kaf24@1452 89
kaf24@8255 90 #endif /* !__ASSEMBLY__ */
kaf24@8255 91
kaf24@1452 92 /* symbolic names for some interesting MSRs */
kaf24@1452 93 /* Intel defined MSRs. */
kaf24@1452 94 #define MSR_IA32_P5_MC_ADDR 0
kaf24@1452 95 #define MSR_IA32_P5_MC_TYPE 1
kaf24@8708 96 #define MSR_IA32_TIME_STAMP_COUNTER 0x10
kaf24@1452 97 #define MSR_IA32_PLATFORM_ID 0x17
kaf24@1452 98 #define MSR_IA32_EBL_CR_POWERON 0x2a
kfraser@15354 99 #define MSR_IA32_EBC_FREQUENCY_ID 0x2c
kaf24@1452 100
kaf24@5167 101 #define MSR_IA32_APICBASE 0x1b
kaf24@5167 102 #define MSR_IA32_APICBASE_BSP (1<<8)
kaf24@5167 103 #define MSR_IA32_APICBASE_ENABLE (1<<11)
kaf24@5167 104 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
kaf24@5167 105
kaf24@5167 106 #define MSR_IA32_UCODE_WRITE 0x79
kaf24@5167 107 #define MSR_IA32_UCODE_REV 0x8b
kaf24@5167 108
kaf24@5167 109 #define MSR_P6_PERFCTR0 0xc1
kaf24@5167 110 #define MSR_P6_PERFCTR1 0xc2
kaf24@5167 111
kaf24@5059 112 /* MSRs & bits used for VMX enabling */
kfraser@15241 113 #define MSR_IA32_VMX_BASIC 0x480
kfraser@15241 114 #define MSR_IA32_VMX_PINBASED_CTLS 0x481
kfraser@15241 115 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
kfraser@15241 116 #define MSR_IA32_VMX_EXIT_CTLS 0x483
kfraser@15241 117 #define MSR_IA32_VMX_ENTRY_CTLS 0x484
kfraser@15241 118 #define MSR_IA32_VMX_MISC 0x485
tdeegan@11172 119 #define MSR_IA32_VMX_CR0_FIXED0 0x486
tdeegan@11172 120 #define MSR_IA32_VMX_CR0_FIXED1 0x487
tdeegan@11172 121 #define MSR_IA32_VMX_CR4_FIXED0 0x488
tdeegan@11172 122 #define MSR_IA32_VMX_CR4_FIXED1 0x489
kfraser@15240 123 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
kaf24@5059 124 #define IA32_FEATURE_CONTROL_MSR 0x3a
kaf24@5059 125 #define IA32_FEATURE_CONTROL_MSR_LOCK 0x1
kaf24@5059 126 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON 0x4
kaf24@5059 127
kaf24@1452 128 /* AMD/K8 specific MSRs */
kaf24@1452 129 #define MSR_EFER 0xc0000080 /* extended feature register */
kaf24@1452 130 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
kaf24@1452 131 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
kaf24@1452 132 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
kaf24@1452 133 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
kfraser@14664 134 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
kfraser@14664 135 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
kaf24@3761 136 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
kaf24@1452 137 /* EFER bits: */
kaf24@1452 138 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
kaf24@1452 139 #define _EFER_LME 8 /* Long mode enable */
kaf24@1452 140 #define _EFER_LMA 10 /* Long mode active (read-only) */
kaf24@1452 141 #define _EFER_NX 11 /* No execute enable */
kaf24@8708 142 #define _EFER_SVME 12
kaf24@1452 143
kaf24@1452 144 #define EFER_SCE (1<<_EFER_SCE)
kaf24@1739 145 #define EFER_LME (1<<_EFER_LME)
kaf24@1739 146 #define EFER_LMA (1<<_EFER_LMA)
kaf24@1452 147 #define EFER_NX (1<<_EFER_NX)
kaf24@8708 148 #define EFER_SVME (1<<_EFER_SVME)
kaf24@1452 149
kfraser@15105 150 #ifndef __ASSEMBLY__
kfraser@15105 151
kfraser@15105 152 DECLARE_PER_CPU(__u64, efer);
kfraser@15105 153
kfraser@15105 154 static inline __u64 read_efer(void)
kfraser@15105 155 {
kfraser@15105 156 if (!this_cpu(efer))
kfraser@15105 157 rdmsrl(MSR_EFER, this_cpu(efer));
kfraser@15105 158 return this_cpu(efer);
kfraser@15105 159 }
kfraser@15105 160
kfraser@15105 161 static inline void write_efer(__u64 val)
kfraser@15105 162 {
kfraser@15105 163 this_cpu(efer) = val;
kfraser@15105 164 wrmsrl(MSR_EFER, val);
kfraser@15105 165 }
kfraser@15105 166
kfraser@15105 167 #endif
kfraser@15105 168
kaf24@1452 169 /* Intel MSRs. Some also available on other CPUs */
kaf24@1452 170 #define MSR_IA32_PLATFORM_ID 0x17
kaf24@1452 171
kaf24@1452 172 #define MSR_MTRRcap 0x0fe
kaf24@1452 173 #define MSR_IA32_BBL_CR_CTL 0x119
kaf24@1452 174
iap10@3290 175 #define MSR_IA32_SYSENTER_CS 0x174
iap10@3290 176 #define MSR_IA32_SYSENTER_ESP 0x175
iap10@3290 177 #define MSR_IA32_SYSENTER_EIP 0x176
iap10@3290 178
kaf24@1452 179 #define MSR_IA32_MCG_CAP 0x179
kaf24@1452 180 #define MSR_IA32_MCG_STATUS 0x17a
kaf24@1452 181 #define MSR_IA32_MCG_CTL 0x17b
kaf24@1452 182
kaf24@7829 183 /* P4/Xeon+ specific */
kaf24@7829 184 #define MSR_IA32_MCG_EAX 0x180
kaf24@7829 185 #define MSR_IA32_MCG_EBX 0x181
kaf24@7829 186 #define MSR_IA32_MCG_ECX 0x182
kaf24@7829 187 #define MSR_IA32_MCG_EDX 0x183
kaf24@7829 188 #define MSR_IA32_MCG_ESI 0x184
kaf24@7829 189 #define MSR_IA32_MCG_EDI 0x185
kaf24@7829 190 #define MSR_IA32_MCG_EBP 0x186
kaf24@7829 191 #define MSR_IA32_MCG_ESP 0x187
kaf24@7829 192 #define MSR_IA32_MCG_EFLAGS 0x188
kaf24@7829 193 #define MSR_IA32_MCG_EIP 0x189
kaf24@7829 194 #define MSR_IA32_MCG_RESERVED 0x18A
kaf24@7829 195
kaf24@7829 196 #define MSR_P6_EVNTSEL0 0x186
kaf24@7829 197 #define MSR_P6_EVNTSEL1 0x187
kaf24@7829 198
kaf24@7829 199 #define MSR_IA32_PERF_STATUS 0x198
kaf24@7829 200 #define MSR_IA32_PERF_CTL 0x199
kaf24@7829 201
kaf24@1452 202 #define MSR_IA32_THERM_CONTROL 0x19a
kaf24@1452 203 #define MSR_IA32_THERM_INTERRUPT 0x19b
kaf24@1452 204 #define MSR_IA32_THERM_STATUS 0x19c
kaf24@1452 205 #define MSR_IA32_MISC_ENABLE 0x1a0
kaf24@1452 206
mafetter@3507 207 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
mafetter@3507 208 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
mafetter@3507 209 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
mafetter@3507 210
kaf24@1452 211 #define MSR_IA32_DEBUGCTLMSR 0x1d9
kaf24@7829 212 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
kaf24@7829 213 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
kaf24@7829 214 #define MSR_IA32_LASTINTFROMIP 0x1dd
kaf24@7829 215 #define MSR_IA32_LASTINTTOIP 0x1de
kaf24@1452 216
kaf24@1452 217 #define MSR_IA32_MC0_CTL 0x400
kaf24@1452 218 #define MSR_IA32_MC0_STATUS 0x401
kaf24@1452 219 #define MSR_IA32_MC0_ADDR 0x402
kaf24@1452 220 #define MSR_IA32_MC0_MISC 0x403
kaf24@1452 221
kfraser@15198 222 /* K8 Machine Check MSRs */
kfraser@15198 223 #define MSR_K8_MC1_CTL 0x404
kfraser@15198 224 #define MSR_K8_MC1_STATUS 0x405
kfraser@15198 225 #define MSR_K8_MC1_ADDR 0x406
kfraser@15198 226 #define MSR_K8_MC1_MISC 0x407
kfraser@15198 227
kfraser@15198 228 #define MSR_K8_MC2_CTL 0x408
kfraser@15198 229 #define MSR_K8_MC2_STATUS 0x409
kfraser@15198 230 #define MSR_K8_MC2_ADDR 0x40A
kfraser@15198 231 #define MSR_K8_MC2_MISC 0x40B
kfraser@15198 232
kfraser@15198 233 #define MSR_K8_MC3_CTL 0x40C
kfraser@15198 234 #define MSR_K8_MC3_STATUS 0x40D
kfraser@15198 235 #define MSR_K8_MC3_ADDR 0x40E
kfraser@15198 236 #define MSR_K8_MC3_MISC 0x40F
kfraser@15198 237
kfraser@15198 238 #define MSR_K8_MC4_CTL 0x410
kfraser@15198 239 #define MSR_K8_MC4_STATUS 0x411
kfraser@15198 240 #define MSR_K8_MC4_ADDR 0x412
kfraser@15198 241 #define MSR_K8_MC4_MISC 0x413
kfraser@15198 242
Tim@15708 243 #define MSR_K8_MC5_CTL 0x414
Tim@15708 244 #define MSR_K8_MC5_STATUS 0x415
Tim@15708 245 #define MSR_K8_MC5_ADDR 0x416
Tim@15708 246 #define MSR_K8_MC5_MISC 0x417
Tim@15708 247
kaf24@7829 248 /* Pentium IV performance counter MSRs */
kaf24@7829 249 #define MSR_P4_BPU_PERFCTR0 0x300
kaf24@7829 250 #define MSR_P4_BPU_PERFCTR1 0x301
kaf24@7829 251 #define MSR_P4_BPU_PERFCTR2 0x302
kaf24@7829 252 #define MSR_P4_BPU_PERFCTR3 0x303
kaf24@7829 253 #define MSR_P4_MS_PERFCTR0 0x304
kaf24@7829 254 #define MSR_P4_MS_PERFCTR1 0x305
kaf24@7829 255 #define MSR_P4_MS_PERFCTR2 0x306
kaf24@7829 256 #define MSR_P4_MS_PERFCTR3 0x307
kaf24@7829 257 #define MSR_P4_FLAME_PERFCTR0 0x308
kaf24@7829 258 #define MSR_P4_FLAME_PERFCTR1 0x309
kaf24@7829 259 #define MSR_P4_FLAME_PERFCTR2 0x30a
kaf24@7829 260 #define MSR_P4_FLAME_PERFCTR3 0x30b
kaf24@7829 261 #define MSR_P4_IQ_PERFCTR0 0x30c
kaf24@7829 262 #define MSR_P4_IQ_PERFCTR1 0x30d
kaf24@7829 263 #define MSR_P4_IQ_PERFCTR2 0x30e
kaf24@7829 264 #define MSR_P4_IQ_PERFCTR3 0x30f
kaf24@7829 265 #define MSR_P4_IQ_PERFCTR4 0x310
kaf24@7829 266 #define MSR_P4_IQ_PERFCTR5 0x311
kaf24@7829 267 #define MSR_P4_BPU_CCCR0 0x360
kaf24@7829 268 #define MSR_P4_BPU_CCCR1 0x361
kaf24@7829 269 #define MSR_P4_BPU_CCCR2 0x362
kaf24@7829 270 #define MSR_P4_BPU_CCCR3 0x363
kaf24@7829 271 #define MSR_P4_MS_CCCR0 0x364
kaf24@7829 272 #define MSR_P4_MS_CCCR1 0x365
kaf24@7829 273 #define MSR_P4_MS_CCCR2 0x366
kaf24@7829 274 #define MSR_P4_MS_CCCR3 0x367
kaf24@7829 275 #define MSR_P4_FLAME_CCCR0 0x368
kaf24@7829 276 #define MSR_P4_FLAME_CCCR1 0x369
kaf24@7829 277 #define MSR_P4_FLAME_CCCR2 0x36a
kaf24@7829 278 #define MSR_P4_FLAME_CCCR3 0x36b
kaf24@7829 279 #define MSR_P4_IQ_CCCR0 0x36c
kaf24@7829 280 #define MSR_P4_IQ_CCCR1 0x36d
kaf24@7829 281 #define MSR_P4_IQ_CCCR2 0x36e
kaf24@7829 282 #define MSR_P4_IQ_CCCR3 0x36f
kaf24@7829 283 #define MSR_P4_IQ_CCCR4 0x370
kaf24@7829 284 #define MSR_P4_IQ_CCCR5 0x371
kaf24@7829 285 #define MSR_P4_ALF_ESCR0 0x3ca
kaf24@7829 286 #define MSR_P4_ALF_ESCR1 0x3cb
kaf24@7829 287 #define MSR_P4_BPU_ESCR0 0x3b2
kaf24@7829 288 #define MSR_P4_BPU_ESCR1 0x3b3
kaf24@7829 289 #define MSR_P4_BSU_ESCR0 0x3a0
kaf24@7829 290 #define MSR_P4_BSU_ESCR1 0x3a1
kaf24@7829 291 #define MSR_P4_CRU_ESCR0 0x3b8
kaf24@7829 292 #define MSR_P4_CRU_ESCR1 0x3b9
kaf24@7829 293 #define MSR_P4_CRU_ESCR2 0x3cc
kaf24@7829 294 #define MSR_P4_CRU_ESCR3 0x3cd
kaf24@7829 295 #define MSR_P4_CRU_ESCR4 0x3e0
kaf24@7829 296 #define MSR_P4_CRU_ESCR5 0x3e1
kaf24@7829 297 #define MSR_P4_DAC_ESCR0 0x3a8
kaf24@7829 298 #define MSR_P4_DAC_ESCR1 0x3a9
kaf24@7829 299 #define MSR_P4_FIRM_ESCR0 0x3a4
kaf24@7829 300 #define MSR_P4_FIRM_ESCR1 0x3a5
kaf24@7829 301 #define MSR_P4_FLAME_ESCR0 0x3a6
kaf24@7829 302 #define MSR_P4_FLAME_ESCR1 0x3a7
kaf24@7829 303 #define MSR_P4_FSB_ESCR0 0x3a2
kaf24@7829 304 #define MSR_P4_FSB_ESCR1 0x3a3
kaf24@7829 305 #define MSR_P4_IQ_ESCR0 0x3ba
kaf24@7829 306 #define MSR_P4_IQ_ESCR1 0x3bb
kaf24@7829 307 #define MSR_P4_IS_ESCR0 0x3b4
kaf24@7829 308 #define MSR_P4_IS_ESCR1 0x3b5
kaf24@7829 309 #define MSR_P4_ITLB_ESCR0 0x3b6
kaf24@7829 310 #define MSR_P4_ITLB_ESCR1 0x3b7
kaf24@7829 311 #define MSR_P4_IX_ESCR0 0x3c8
kaf24@7829 312 #define MSR_P4_IX_ESCR1 0x3c9
kaf24@7829 313 #define MSR_P4_MOB_ESCR0 0x3aa
kaf24@7829 314 #define MSR_P4_MOB_ESCR1 0x3ab
kaf24@7829 315 #define MSR_P4_MS_ESCR0 0x3c0
kaf24@7829 316 #define MSR_P4_MS_ESCR1 0x3c1
kaf24@7829 317 #define MSR_P4_PMH_ESCR0 0x3ac
kaf24@7829 318 #define MSR_P4_PMH_ESCR1 0x3ad
kaf24@7829 319 #define MSR_P4_RAT_ESCR0 0x3bc
kaf24@7829 320 #define MSR_P4_RAT_ESCR1 0x3bd
kaf24@7829 321 #define MSR_P4_SAAT_ESCR0 0x3ae
kaf24@7829 322 #define MSR_P4_SAAT_ESCR1 0x3af
kaf24@7829 323 #define MSR_P4_SSU_ESCR0 0x3be
kaf24@7829 324 #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
kaf24@7829 325 #define MSR_P4_TBPU_ESCR0 0x3c2
kaf24@7829 326 #define MSR_P4_TBPU_ESCR1 0x3c3
kaf24@7829 327 #define MSR_P4_TC_ESCR0 0x3c4
kaf24@7829 328 #define MSR_P4_TC_ESCR1 0x3c5
kaf24@7829 329 #define MSR_P4_U2L_ESCR0 0x3b0
kaf24@7829 330 #define MSR_P4_U2L_ESCR1 0x3b1
mafetter@3507 331
kaf24@1452 332 #define MSR_K6_EFER 0xC0000080
kaf24@1452 333 #define MSR_K6_STAR 0xC0000081
kaf24@1452 334 #define MSR_K6_WHCR 0xC0000082
kaf24@1452 335 #define MSR_K6_UWCCR 0xC0000085
kaf24@1452 336 #define MSR_K6_EPMR 0xC0000086
kaf24@1452 337 #define MSR_K6_PSOR 0xC0000087
kaf24@1452 338 #define MSR_K6_PFIR 0xC0000088
kaf24@1452 339
kaf24@7829 340 #define MSR_K7_EVNTSEL0 0xC0010000
kaf24@7829 341 #define MSR_K7_EVNTSEL1 0xC0010001
kaf24@7829 342 #define MSR_K7_EVNTSEL2 0xC0010002
kaf24@7829 343 #define MSR_K7_EVNTSEL3 0xC0010003
kaf24@7829 344 #define MSR_K7_PERFCTR0 0xC0010004
kaf24@7829 345 #define MSR_K7_PERFCTR1 0xC0010005
kaf24@7829 346 #define MSR_K7_PERFCTR2 0xC0010006
kaf24@7829 347 #define MSR_K7_PERFCTR3 0xC0010007
kaf24@7829 348 #define MSR_K7_HWCR 0xC0010015
kaf24@7829 349 #define MSR_K7_CLK_CTL 0xC001001b
kaf24@7829 350 #define MSR_K7_FID_VID_CTL 0xC0010041
kaf24@7829 351 #define MSR_K7_FID_VID_STATUS 0xC0010042
kaf24@7829 352
kaf24@8708 353 #define MSR_K8_TOP_MEM1 0xC001001A
kaf24@8708 354 #define MSR_K8_TOP_MEM2 0xC001001D
kfraser@11798 355 #define MSR_K8_SYSCFG 0xC0010010
kfraser@11798 356 #define MSR_K8_HWCR 0xC0010015
kfraser@11798 357 #define MSR_K8_VM_CR 0xC0010114
kaf24@8708 358 #define MSR_K8_VM_HSAVE_PA 0xC0010117
kfraser@11798 359
kfraser@11798 360 /* MSR_K8_VM_CR bits: */
kfraser@11798 361 #define _K8_VMCR_SVME_DISABLE 4
kfraser@11798 362 #define K8_VMCR_SVME_DISABLE (1 << _K8_VMCR_SVME_DISABLE)
kaf24@8708 363
kaf24@1452 364 /* Centaur-Hauls/IDT defined MSRs. */
kaf24@1452 365 #define MSR_IDT_FCR1 0x107
kaf24@1452 366 #define MSR_IDT_FCR2 0x108
kaf24@1452 367 #define MSR_IDT_FCR3 0x109
kaf24@1452 368 #define MSR_IDT_FCR4 0x10a
kaf24@1452 369
kaf24@1452 370 #define MSR_IDT_MCR0 0x110
kaf24@1452 371 #define MSR_IDT_MCR1 0x111
kaf24@1452 372 #define MSR_IDT_MCR2 0x112
kaf24@1452 373 #define MSR_IDT_MCR3 0x113
kaf24@1452 374 #define MSR_IDT_MCR4 0x114
kaf24@1452 375 #define MSR_IDT_MCR5 0x115
kaf24@1452 376 #define MSR_IDT_MCR6 0x116
kaf24@1452 377 #define MSR_IDT_MCR7 0x117
kaf24@1452 378 #define MSR_IDT_MCR_CTRL 0x120
kaf24@1452 379
kaf24@1452 380 /* VIA Cyrix defined MSRs*/
kaf24@1452 381 #define MSR_VIA_FCR 0x1107
kaf24@1452 382 #define MSR_VIA_LONGHAUL 0x110a
kaf24@5167 383 #define MSR_VIA_RNG 0x110b
kaf24@1452 384 #define MSR_VIA_BCR2 0x1147
kaf24@1452 385
kaf24@1452 386 /* Transmeta defined MSRs */
kaf24@1452 387 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
kaf24@1452 388 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
kaf24@1452 389 #define MSR_TMTA_LRTI_READOUT 0x80868018
kaf24@1452 390 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
kaf24@1452 391
kaf24@1452 392 #endif /* __ASM_MSR_H */