ia64/xen-unstable

annotate extras/mini-os/hypervisor.c @ 10843:4f6d858ea570

[PCI] Per-device permissive flag (replaces global permissive flag).
Signed-off-by: Chris Bookholt <hap10@tycho.ncsc.mil>
author kfraser@localhost.localdomain
date Fri Jul 28 12:56:10 2006 +0100 (2006-07-28)
parents f6507937cb7c
children f40079acf646
rev   line source
iap10@792 1 /******************************************************************************
iap10@792 2 * hypervisor.c
iap10@792 3 *
iap10@792 4 * Communication to/from hypervisor.
kaf24@801 5 *
kaf24@838 6 * Copyright (c) 2002-2003, K A Fraser
kaf24@5675 7 * Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
kaf24@801 8 *
kaf24@838 9 * Permission is hereby granted, free of charge, to any person obtaining a copy
kaf24@838 10 * of this software and associated documentation files (the "Software"), to
kaf24@838 11 * deal in the Software without restriction, including without limitation the
kaf24@838 12 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
kaf24@838 13 * sell copies of the Software, and to permit persons to whom the Software is
kaf24@838 14 * furnished to do so, subject to the following conditions:
kaf24@801 15 *
kaf24@838 16 * The above copyright notice and this permission notice shall be included in
kaf24@838 17 * all copies or substantial portions of the Software.
kaf24@838 18 *
kaf24@838 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
kaf24@838 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
kaf24@838 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
kaf24@838 22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
kaf24@838 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
kaf24@838 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
kaf24@838 25 * DEALINGS IN THE SOFTWARE.
iap10@792 26 */
iap10@792 27
iap10@792 28 #include <os.h>
iap10@792 29 #include <hypervisor.h>
kaf24@5675 30 #include <events.h>
iap10@792 31
kaf24@5675 32 #define active_evtchns(cpu,sh,idx) \
kaf24@5675 33 ((sh)->evtchn_pending[idx] & \
kaf24@5675 34 ~(sh)->evtchn_mask[idx])
iap10@792 35
iap10@792 36 void do_hypervisor_callback(struct pt_regs *regs)
iap10@792 37 {
kaf24@5675 38 u32 l1, l2;
kaf24@5675 39 unsigned int l1i, l2i, port;
kaf24@5675 40 int cpu = 0;
kaf24@5675 41 shared_info_t *s = HYPERVISOR_shared_info;
kaf24@8251 42 vcpu_info_t *vcpu_info = &s->vcpu_info[cpu];
iap10@792 43
kaf24@9911 44
kaf24@5675 45 vcpu_info->evtchn_upcall_pending = 0;
kaf24@5675 46 /* NB. No need for a barrier here -- XCHG is a barrier on x86. */
kaf24@5675 47 l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
kaf24@5675 48 while ( l1 != 0 )
kaf24@5675 49 {
kaf24@5675 50 l1i = __ffs(l1);
kaf24@5675 51 l1 &= ~(1 << l1i);
kaf24@5675 52
kaf24@5675 53 while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 )
kaf24@5675 54 {
kaf24@5675 55 l2i = __ffs(l2);
kaf24@5675 56 l2 &= ~(1 << l2i);
iap10@792 57
kaf24@5675 58 port = (l1i << 5) + l2i;
kaf24@5675 59 do_event(port, regs);
kaf24@5675 60 }
iap10@792 61 }
iap10@792 62 }
iap10@792 63
kaf24@5675 64
kaf24@5675 65 inline void mask_evtchn(u32 port)
iap10@792 66 {
kaf24@5675 67 shared_info_t *s = HYPERVISOR_shared_info;
kaf24@5675 68 synch_set_bit(port, &s->evtchn_mask[0]);
iap10@792 69 }
iap10@792 70
kaf24@5675 71 inline void unmask_evtchn(u32 port)
iap10@792 72 {
kaf24@5675 73 shared_info_t *s = HYPERVISOR_shared_info;
kaf24@8251 74 vcpu_info_t *vcpu_info = &s->vcpu_info[smp_processor_id()];
kaf24@5675 75
kaf24@5675 76 synch_clear_bit(port, &s->evtchn_mask[0]);
kaf24@5675 77
kaf24@5675 78 /*
kaf24@5675 79 * The following is basically the equivalent of 'hw_resend_irq'. Just like
kaf24@5675 80 * a real IO-APIC we 'lose the interrupt edge' if the channel is masked.
kaf24@5675 81 */
kaf24@5675 82 if ( synch_test_bit (port, &s->evtchn_pending[0]) &&
kaf24@5675 83 !synch_test_and_set_bit(port>>5, &vcpu_info->evtchn_pending_sel) )
kaf24@5675 84 {
kaf24@5675 85 vcpu_info->evtchn_upcall_pending = 1;
kaf24@5675 86 if ( !vcpu_info->evtchn_upcall_mask )
kaf24@5675 87 force_evtchn_callback();
kaf24@5675 88 }
iap10@792 89 }
iap10@792 90
kaf24@5675 91 inline void clear_evtchn(u32 port)
iap10@792 92 {
kaf24@5675 93 shared_info_t *s = HYPERVISOR_shared_info;
kaf24@5675 94 synch_clear_bit(port, &s->evtchn_pending[0]);
iap10@792 95 }