ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 15314:35e38c9048c8

Add suspend/resume to devices owned by Xen.

Signed-off-by: Ke Yu <ke.yu@intel.com>
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Mon Jun 11 15:44:48 2007 +0100 (2007-06-11)
parents ea0b50ca4999
children 005dd6b1cf8e
rev   line source
kaf24@1452 1 /*
kfraser@11541 2 * based on linux-2.6.17.13/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kfraser@11204 13 * Maciej W. Rozycki : Various updates and fixes.
kfraser@11204 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@8847 41 * Knob to control our willingness to enable the local APIC.
kaf24@8847 42 */
kaf24@8847 43 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
kaf24@8847 44
kaf24@8847 45 /*
kaf24@4888 46 * Debug level
kaf24@4888 47 */
kaf24@4888 48 int apic_verbosity;
kaf24@4888 49
kaf24@8847 50
kaf24@8847 51 static void apic_pm_activate(void);
kaf24@8847 52
kfraser@11541 53 int modern_apic(void)
kfraser@11541 54 {
kfraser@11541 55 unsigned int lvr, version;
kfraser@11541 56 /* AMD systems use old APIC versions, so check the CPU */
kfraser@11541 57 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
kfraser@11541 58 boot_cpu_data.x86 >= 0xf)
kfraser@11541 59 return 1;
kfraser@11541 60 lvr = apic_read(APIC_LVR);
kfraser@11541 61 version = GET_APIC_VERSION(lvr);
kfraser@11541 62 return version >= 0x14;
kfraser@11541 63 }
kfraser@11541 64
kaf24@8847 65 /*
kaf24@8847 66 * 'what should we do if we get a hw irq event on an illegal vector'.
kaf24@8847 67 * each architecture has to answer this themselves.
kaf24@8847 68 */
kaf24@8847 69 void ack_bad_irq(unsigned int irq)
kaf24@8847 70 {
kaf24@8847 71 printk("unexpected IRQ trap at vector %02x\n", irq);
kaf24@8847 72 /*
kaf24@8847 73 * Currently unexpected vectors happen only on SMP and APIC.
kaf24@8847 74 * We _must_ ack these because every local APIC has only N
kaf24@8847 75 * irq slots per priority level, and a 'hanging, unacked' IRQ
kaf24@8847 76 * holds up an irq slot - in excessive cases (when multiple
kaf24@8847 77 * unexpected vectors occur) that might lock up the APIC
kaf24@8847 78 * completely.
kfraser@11541 79 * But only ack when the APIC is enabled -AK
kaf24@8847 80 */
kfraser@11541 81 if (cpu_has_apic)
kfraser@11541 82 ack_APIC_irq();
kaf24@8847 83 }
kaf24@8847 84
kaf24@8847 85 void __init apic_intr_init(void)
kaf24@8847 86 {
kaf24@8847 87 #ifdef CONFIG_SMP
kaf24@8847 88 smp_intr_init();
kaf24@8847 89 #endif
kaf24@8847 90 /* self generated IPI for local APIC timer */
kaf24@8847 91 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
kaf24@8847 92
kaf24@8847 93 /* IPI vectors for APIC spurious and error interrupts */
kaf24@8847 94 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
kaf24@8847 95 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
kaf24@8847 96
kaf24@8847 97 /* thermal monitor LVT interrupt */
kaf24@8847 98 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@8847 99 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
kaf24@8847 100 #endif
kaf24@8847 101 }
kaf24@8847 102
kaf24@1452 103 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 104 int using_apic_timer = 0;
kaf24@1452 105
kaf24@1452 106 static int enabled_via_apicbase;
kaf24@1452 107
kfraser@11541 108 void enable_NMI_through_LVT0 (void * dummy)
kfraser@11541 109 {
kfraser@11541 110 unsigned int v, ver;
kfraser@11541 111
kfraser@11541 112 ver = apic_read(APIC_LVR);
kfraser@11541 113 ver = GET_APIC_VERSION(ver);
kfraser@11541 114 v = APIC_DM_NMI; /* unmask and set to NMI */
kfraser@11541 115 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kfraser@11541 116 v |= APIC_LVT_LEVEL_TRIGGER;
kfraser@11541 117 apic_write_around(APIC_LVT0, v);
kfraser@11541 118 }
kfraser@11541 119
kaf24@4804 120 int get_physical_broadcast(void)
kaf24@4804 121 {
kfraser@11541 122 if (modern_apic())
kaf24@4804 123 return 0xff;
kaf24@4804 124 else
kaf24@4804 125 return 0xf;
kaf24@4804 126 }
kaf24@4804 127
kaf24@1452 128 int get_maxlvt(void)
kaf24@1452 129 {
kaf24@1452 130 unsigned int v, ver, maxlvt;
kaf24@1452 131
kaf24@1452 132 v = apic_read(APIC_LVR);
kaf24@1452 133 ver = GET_APIC_VERSION(v);
kaf24@1452 134 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 135 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 136 return maxlvt;
kaf24@1452 137 }
kaf24@1452 138
kaf24@1452 139 void clear_local_APIC(void)
kaf24@1452 140 {
kaf24@1452 141 int maxlvt;
kaf24@1452 142 unsigned long v;
kaf24@1452 143
kaf24@1452 144 maxlvt = get_maxlvt();
kaf24@1452 145
kaf24@1452 146 /*
kaf24@1452 147 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 148 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 149 */
kaf24@1452 150 if (maxlvt >= 3) {
kaf24@1452 151 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 152 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 153 }
kaf24@1452 154 /*
kaf24@1452 155 * Careful: we have to set masks only first to deassert
kaf24@1452 156 * any level-triggered sources.
kaf24@1452 157 */
kaf24@1452 158 v = apic_read(APIC_LVTT);
kaf24@1452 159 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 160 v = apic_read(APIC_LVT0);
kaf24@1452 161 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 162 v = apic_read(APIC_LVT1);
kaf24@1452 163 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 164 if (maxlvt >= 4) {
kaf24@1452 165 v = apic_read(APIC_LVTPC);
kaf24@1452 166 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 167 }
kaf24@1452 168
kaf24@5211 169 /* lets not touch this if we didn't frob it */
kaf24@5211 170 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 171 if (maxlvt >= 5) {
kaf24@5211 172 v = apic_read(APIC_LVTTHMR);
kaf24@5211 173 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
kaf24@5211 174 }
kaf24@5211 175 #endif
kaf24@1452 176 /*
kaf24@1452 177 * Clean APIC state for other OSs:
kaf24@1452 178 */
kaf24@1452 179 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 180 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 181 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 182 if (maxlvt >= 3)
kaf24@1452 183 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 184 if (maxlvt >= 4)
kaf24@1452 185 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 186
kaf24@5211 187 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 188 if (maxlvt >= 5)
kaf24@5211 189 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
kaf24@5211 190 #endif
kaf24@1452 191 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kfraser@11204 192 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 193 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 194 apic_write(APIC_ESR, 0);
kaf24@1452 195 apic_read(APIC_ESR);
kaf24@1452 196 }
kaf24@1452 197 }
kaf24@1452 198
kaf24@1452 199 void __init connect_bsp_APIC(void)
kaf24@1452 200 {
kaf24@1452 201 if (pic_mode) {
kaf24@1452 202 /*
kaf24@1452 203 * Do not trust the local APIC being empty at bootup.
kaf24@1452 204 */
kaf24@1452 205 clear_local_APIC();
kaf24@1452 206 /*
kaf24@1452 207 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 208 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 209 */
kaf24@4888 210 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 211 "enabling APIC mode.\n");
kaf24@1452 212 outb(0x70, 0x22);
kaf24@1452 213 outb(0x01, 0x23);
kaf24@1452 214 }
kaf24@5211 215 enable_apic_mode();
kaf24@1452 216 }
kaf24@1452 217
kaf24@8847 218 void disconnect_bsp_APIC(int virt_wire_setup)
kaf24@1452 219 {
kaf24@1452 220 if (pic_mode) {
kaf24@1452 221 /*
kaf24@1452 222 * Put the board back into PIC mode (has an effect
kaf24@1452 223 * only on certain older boards). Note that APIC
kaf24@1452 224 * interrupts, including IPIs, won't work beyond
kaf24@1452 225 * this point! The only exception are INIT IPIs.
kaf24@1452 226 */
kaf24@4888 227 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 228 "entering PIC mode.\n");
kaf24@1452 229 outb(0x70, 0x22);
kaf24@1452 230 outb(0x00, 0x23);
kaf24@1452 231 }
kaf24@8847 232 else {
kaf24@8847 233 /* Go back to Virtual Wire compatibility mode */
kaf24@8847 234 unsigned long value;
kaf24@8847 235
kaf24@8847 236 /* For the spurious interrupt use vector F, and enable it */
kaf24@8847 237 value = apic_read(APIC_SPIV);
kaf24@8847 238 value &= ~APIC_VECTOR_MASK;
kaf24@8847 239 value |= APIC_SPIV_APIC_ENABLED;
kaf24@8847 240 value |= 0xf;
kaf24@8847 241 apic_write_around(APIC_SPIV, value);
kaf24@8847 242
kaf24@8847 243 if (!virt_wire_setup) {
kaf24@8847 244 /* For LVT0 make it edge triggered, active high, external and enabled */
kaf24@8847 245 value = apic_read(APIC_LVT0);
kaf24@8847 246 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 247 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 248 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
kaf24@8847 249 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 250 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
kaf24@8847 251 apic_write_around(APIC_LVT0, value);
kaf24@8847 252 }
kaf24@8847 253 else {
kaf24@8847 254 /* Disable LVT0 */
kaf24@8847 255 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@8847 256 }
kaf24@8847 257
kaf24@8847 258 /* For LVT1 make it edge triggered, active high, nmi and enabled */
kaf24@8847 259 value = apic_read(APIC_LVT1);
kaf24@8847 260 value &= ~(
kaf24@8847 261 APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 262 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 263 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
kaf24@8847 264 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 265 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
kaf24@8847 266 apic_write_around(APIC_LVT1, value);
kaf24@8847 267 }
kaf24@1452 268 }
kaf24@1452 269
kaf24@1452 270 void disable_local_APIC(void)
kaf24@1452 271 {
kaf24@1452 272 unsigned long value;
kaf24@1452 273
kaf24@1452 274 clear_local_APIC();
kaf24@1452 275
kaf24@1452 276 /*
kaf24@1452 277 * Disable APIC (implies clearing of registers
kaf24@1452 278 * for 82489DX!).
kaf24@1452 279 */
kaf24@1452 280 value = apic_read(APIC_SPIV);
kaf24@1452 281 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 282 apic_write_around(APIC_SPIV, value);
kaf24@1452 283
kaf24@1452 284 if (enabled_via_apicbase) {
kaf24@1452 285 unsigned int l, h;
kaf24@1452 286 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 287 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 288 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 289 }
kaf24@1452 290 }
kaf24@1452 291
kaf24@1452 292 /*
kaf24@1452 293 * This is to verify that we're looking at a real local APIC.
kaf24@1452 294 * Check these against your board if the CPUs aren't getting
kaf24@1452 295 * started for no apparent reason.
kaf24@1452 296 */
kaf24@1452 297 int __init verify_local_APIC(void)
kaf24@1452 298 {
kaf24@1452 299 unsigned int reg0, reg1;
kaf24@1452 300
kaf24@1452 301 /*
kaf24@1452 302 * The version register is read-only in a real APIC.
kaf24@1452 303 */
kaf24@1452 304 reg0 = apic_read(APIC_LVR);
kaf24@4888 305 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
kaf24@1452 306 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 307 reg1 = apic_read(APIC_LVR);
kaf24@4888 308 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 309
kaf24@1452 310 /*
kaf24@1452 311 * The two version reads above should print the same
kaf24@1452 312 * numbers. If the second one is different, then we
kaf24@1452 313 * poke at a non-APIC.
kaf24@1452 314 */
kaf24@1452 315 if (reg1 != reg0)
kaf24@1452 316 return 0;
kaf24@1452 317
kaf24@1452 318 /*
kaf24@1452 319 * Check if the version looks reasonably.
kaf24@1452 320 */
kaf24@1452 321 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 322 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 323 return 0;
kaf24@1452 324 reg1 = get_maxlvt();
kaf24@1452 325 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 326 return 0;
kaf24@1452 327
kaf24@1452 328 /*
kaf24@1452 329 * The ID register is read/write in a real APIC.
kaf24@1452 330 */
kaf24@1452 331 reg0 = apic_read(APIC_ID);
kaf24@4888 332 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 333
kaf24@1452 334 /*
kaf24@1452 335 * The next two are just to see if we have sane values.
kaf24@1452 336 * They're only really relevant if we're in Virtual Wire
kaf24@1452 337 * compatibility mode, but most boxes are anymore.
kaf24@1452 338 */
kaf24@1452 339 reg0 = apic_read(APIC_LVT0);
kaf24@4888 340 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 341 reg1 = apic_read(APIC_LVT1);
kaf24@4888 342 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 343
kaf24@1452 344 return 1;
kaf24@1452 345 }
kaf24@1452 346
kaf24@1452 347 void __init sync_Arb_IDs(void)
kaf24@1452 348 {
kfraser@11541 349 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
kfraser@11541 350 And not needed on AMD */
kfraser@11541 351 if (modern_apic())
iap10@4548 352 return;
kaf24@1452 353 /*
kaf24@1452 354 * Wait for idle.
kaf24@1452 355 */
kaf24@1452 356 apic_wait_icr_idle();
kaf24@1452 357
kaf24@4888 358 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 359 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 360 | APIC_DM_INIT);
kaf24@1452 361 }
kaf24@1452 362
kaf24@1452 363 extern void __error_in_apic_c (void);
kaf24@1452 364
kaf24@4888 365 /*
kaf24@4888 366 * An initial setup of the virtual wire mode.
kaf24@4888 367 */
kaf24@1452 368 void __init init_bsp_APIC(void)
kaf24@1452 369 {
kaf24@4620 370 unsigned long value, ver;
kaf24@4620 371
kaf24@4620 372 /*
kaf24@4888 373 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 374 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 375 */
kaf24@4620 376 if (smp_found_config || !cpu_has_apic)
kaf24@4620 377 return;
kaf24@4620 378
kaf24@4620 379 value = apic_read(APIC_LVR);
kaf24@4620 380 ver = GET_APIC_VERSION(value);
kaf24@4620 381
kaf24@4620 382 /*
kaf24@4620 383 * Do not trust the local APIC being empty at bootup.
kaf24@4620 384 */
kaf24@4620 385 clear_local_APIC();
kaf24@4620 386
kaf24@4620 387 /*
kaf24@4620 388 * Enable APIC.
kaf24@4620 389 */
kaf24@4620 390 value = apic_read(APIC_SPIV);
kaf24@4620 391 value &= ~APIC_VECTOR_MASK;
kaf24@4620 392 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 393
kaf24@4620 394 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 395 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 396 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 397 else
kaf24@4620 398 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 399 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 400 apic_write_around(APIC_SPIV, value);
kaf24@4620 401
kaf24@4620 402 /*
kaf24@4620 403 * Set up the virtual wire mode.
kaf24@4620 404 */
kaf24@4620 405 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 406 value = APIC_DM_NMI;
kaf24@4620 407 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 408 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 409 apic_write_around(APIC_LVT1, value);
kaf24@1452 410 }
kaf24@1452 411
kaf24@8847 412 void __devinit setup_local_APIC(void)
kaf24@1452 413 {
iap10@4548 414 unsigned long oldvalue, value, ver, maxlvt;
kfraser@11541 415 int i, j;
iap10@4548 416
iap10@4548 417 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 418 if (esr_disable) {
iap10@4548 419 apic_write(APIC_ESR, 0);
iap10@4548 420 apic_write(APIC_ESR, 0);
iap10@4548 421 apic_write(APIC_ESR, 0);
iap10@4548 422 apic_write(APIC_ESR, 0);
iap10@4548 423 }
kaf24@1452 424
kaf24@1452 425 value = apic_read(APIC_LVR);
kaf24@1452 426 ver = GET_APIC_VERSION(value);
kaf24@1452 427
kaf24@1452 428 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 429 __error_in_apic_c();
kaf24@1452 430
iap10@4548 431 /*
iap10@4548 432 * Double-check whether this APIC is really registered.
iap10@4548 433 */
iap10@4548 434 if (!apic_id_registered())
kaf24@1452 435 BUG();
kaf24@1452 436
kaf24@1452 437 /*
kaf24@1452 438 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 439 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 440 * document number 292116). So here it goes...
kaf24@1452 441 */
iap10@4548 442 init_apic_ldr();
kaf24@1452 443
kaf24@1452 444 /*
kaf24@1452 445 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 446 * later on.
kaf24@1452 447 */
kaf24@1452 448 value = apic_read(APIC_TASKPRI);
kaf24@1452 449 value &= ~APIC_TPRI_MASK;
kaf24@1452 450 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 451
kaf24@1452 452 /*
kfraser@11541 453 * After a crash, we no longer service the interrupts and a pending
kfraser@11541 454 * interrupt from previous kernel might still have ISR bit set.
kfraser@11541 455 *
kfraser@11541 456 * Most probably by now CPU has serviced that pending interrupt and
kfraser@11541 457 * it might not have done the ack_APIC_irq() because it thought,
kfraser@11541 458 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
kfraser@11541 459 * does not clear the ISR bit and cpu thinks it has already serivced
kfraser@11541 460 * the interrupt. Hence a vector might get locked. It was noticed
kfraser@11541 461 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
kfraser@11541 462 */
kfraser@11541 463 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
kfraser@11541 464 value = apic_read(APIC_ISR + i*0x10);
kfraser@11541 465 for (j = 31; j >= 0; j--) {
kfraser@11541 466 if (value & (1<<j))
kfraser@11541 467 ack_APIC_irq();
kfraser@11541 468 }
kfraser@11541 469 }
kfraser@11541 470
kfraser@11541 471 /*
kaf24@1452 472 * Now that we are all set up, enable the APIC
kaf24@1452 473 */
kaf24@1452 474 value = apic_read(APIC_SPIV);
kaf24@1452 475 value &= ~APIC_VECTOR_MASK;
kaf24@1452 476 /*
kaf24@1452 477 * Enable APIC
kaf24@1452 478 */
kaf24@1452 479 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 480
iap10@4548 481 /*
iap10@4548 482 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 483 * certain networking cards. If high frequency interrupts are
iap10@4548 484 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 485 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 486 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 487 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 488 * away, oh well :-(
iap10@4548 489 *
iap10@4548 490 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 491 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 492 * BX chipset. ]
iap10@4548 493 */
iap10@4548 494 /*
iap10@4548 495 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 496 * frequent as it makes the interrupt distributon model be more
iap10@4548 497 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 498 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 499 */
iap10@4548 500 #if 1
kaf24@1452 501 /* Enable focus processor (bit==0) */
kaf24@1452 502 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 503 #else
iap10@4548 504 /* Disable focus processor (bit==1) */
iap10@4548 505 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 506 #endif
iap10@4548 507 /*
iap10@4548 508 * Set spurious IRQ vector
iap10@4548 509 */
kaf24@1452 510 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 511 apic_write_around(APIC_SPIV, value);
kaf24@1452 512
kaf24@1452 513 /*
kaf24@1452 514 * Set up LVT0, LVT1:
kaf24@1452 515 *
kaf24@1452 516 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 517 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 518 * we delegate interrupts to the 8259A.
kaf24@1452 519 */
kaf24@1452 520 /*
kaf24@1452 521 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 522 */
kaf24@1452 523 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 524 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 525 value = APIC_DM_EXTINT;
kaf24@4888 526 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 527 smp_processor_id());
kaf24@1452 528 } else {
kaf24@1452 529 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 530 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 531 smp_processor_id());
kaf24@1452 532 }
kaf24@1452 533 apic_write_around(APIC_LVT0, value);
kaf24@1452 534
kaf24@1452 535 /*
kaf24@1452 536 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 537 */
kaf24@1452 538 if (!smp_processor_id())
kaf24@1452 539 value = APIC_DM_NMI;
kaf24@1452 540 else
kaf24@1452 541 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 542 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 543 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 544 apic_write_around(APIC_LVT1, value);
kaf24@1452 545
iap10@4548 546 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 547 maxlvt = get_maxlvt();
kaf24@1452 548 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 549 apic_write(APIC_ESR, 0);
iap10@4548 550 oldvalue = apic_read(APIC_ESR);
kaf24@1452 551
iap10@4548 552 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 553 apic_write_around(APIC_LVTERR, value);
iap10@4548 554 /*
iap10@4548 555 * spec says clear errors after enabling vector.
iap10@4548 556 */
kaf24@1452 557 if (maxlvt > 3)
kaf24@1452 558 apic_write(APIC_ESR, 0);
kaf24@1452 559 value = apic_read(APIC_ESR);
iap10@4548 560 if (value != oldvalue)
kaf24@4888 561 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 562 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 563 oldvalue, value);
kaf24@1452 564 } else {
iap10@4548 565 if (esr_disable)
iap10@4548 566 /*
iap10@4548 567 * Something untraceble is creating bad interrupts on
iap10@4548 568 * secondary quads ... for the moment, just leave the
iap10@4548 569 * ESR disabled - we can't do anything useful with the
iap10@4548 570 * errors anyway - mbligh
iap10@4548 571 */
iap10@4548 572 printk("Leaving ESR disabled.\n");
kaf24@4888 573 else
kaf24@4888 574 printk("No ESR for 82489DX.\n");
kaf24@1452 575 }
kaf24@1452 576
kaf24@8594 577 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@8594 578 setup_apic_nmi_watchdog();
kaf24@8847 579 apic_pm_activate();
kaf24@1452 580 }
kaf24@1452 581
kfraser@15314 582 static struct {
kfraser@15314 583 int active;
kfraser@15314 584 /* r/w apic fields */
kfraser@15314 585 unsigned int apic_id;
kfraser@15314 586 unsigned int apic_taskpri;
kfraser@15314 587 unsigned int apic_ldr;
kfraser@15314 588 unsigned int apic_dfr;
kfraser@15314 589 unsigned int apic_spiv;
kfraser@15314 590 unsigned int apic_lvtt;
kfraser@15314 591 unsigned int apic_lvtpc;
kfraser@15314 592 unsigned int apic_lvt0;
kfraser@15314 593 unsigned int apic_lvt1;
kfraser@15314 594 unsigned int apic_lvterr;
kfraser@15314 595 unsigned int apic_tmict;
kfraser@15314 596 unsigned int apic_tdcr;
kfraser@15314 597 unsigned int apic_thmr;
kfraser@15314 598 } apic_pm_state;
kfraser@15314 599
kfraser@15314 600 int lapic_suspend(void)
kfraser@15314 601 {
kfraser@15314 602 unsigned long flags;
kfraser@15314 603
kfraser@15314 604 if (!apic_pm_state.active)
kfraser@15314 605 return 0;
kfraser@15314 606
kfraser@15314 607 apic_pm_state.apic_id = apic_read(APIC_ID);
kfraser@15314 608 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
kfraser@15314 609 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
kfraser@15314 610 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
kfraser@15314 611 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
kfraser@15314 612 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
kfraser@15314 613 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
kfraser@15314 614 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
kfraser@15314 615 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
kfraser@15314 616 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
kfraser@15314 617 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
kfraser@15314 618 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
kfraser@15314 619 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
kfraser@15314 620
kfraser@15314 621 local_irq_save(flags);
kfraser@15314 622 disable_local_APIC();
kfraser@15314 623 local_irq_restore(flags);
kfraser@15314 624 return 0;
kfraser@15314 625 }
kfraser@15314 626
kfraser@15314 627 int lapic_resume(void)
kfraser@15314 628 {
kfraser@15314 629 unsigned int l, h;
kfraser@15314 630 unsigned long flags;
kfraser@15314 631
kfraser@15314 632 if (!apic_pm_state.active)
kfraser@15314 633 return 0;
kfraser@15314 634
kfraser@15314 635 local_irq_save(flags);
kfraser@15314 636
kfraser@15314 637 /*
kfraser@15314 638 * Make sure the APICBASE points to the right address
kfraser@15314 639 *
kfraser@15314 640 * FIXME! This will be wrong if we ever support suspend on
kfraser@15314 641 * SMP! We'll need to do this as part of the CPU restore!
kfraser@15314 642 */
kfraser@15314 643 rdmsr(MSR_IA32_APICBASE, l, h);
kfraser@15314 644 l &= ~MSR_IA32_APICBASE_BASE;
kfraser@15314 645 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
kfraser@15314 646 wrmsr(MSR_IA32_APICBASE, l, h);
kfraser@15314 647
kfraser@15314 648 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
kfraser@15314 649 apic_write(APIC_ID, apic_pm_state.apic_id);
kfraser@15314 650 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
kfraser@15314 651 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
kfraser@15314 652 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
kfraser@15314 653 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
kfraser@15314 654 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
kfraser@15314 655 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
kfraser@15314 656 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
kfraser@15314 657 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
kfraser@15314 658 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
kfraser@15314 659 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
kfraser@15314 660 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
kfraser@15314 661 apic_write(APIC_ESR, 0);
kfraser@15314 662 apic_read(APIC_ESR);
kfraser@15314 663 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
kfraser@15314 664 apic_write(APIC_ESR, 0);
kfraser@15314 665 apic_read(APIC_ESR);
kfraser@15314 666 local_irq_restore(flags);
kfraser@15314 667 return 0;
kfraser@15314 668 }
kfraser@15314 669
kfraser@15314 670
kfraser@11541 671 /*
kfraser@11541 672 * If Linux enabled the LAPIC against the BIOS default
kfraser@11541 673 * disable it down before re-entering the BIOS on shutdown.
kfraser@11541 674 * Otherwise the BIOS may get confused and not power-off.
kfraser@11541 675 * Additionally clear all LVT entries before disable_local_APIC
kfraser@11541 676 * for the case where Linux didn't enable the LAPIC.
kfraser@11541 677 */
kfraser@11541 678 void lapic_shutdown(void)
kfraser@11541 679 {
kfraser@11541 680 unsigned long flags;
kfraser@11541 681
kfraser@11541 682 if (!cpu_has_apic)
kfraser@11541 683 return;
kfraser@11541 684
kfraser@11541 685 local_irq_save(flags);
kfraser@11541 686 clear_local_APIC();
kfraser@11541 687
kfraser@11541 688 if (enabled_via_apicbase)
kfraser@11541 689 disable_local_APIC();
kfraser@11541 690
kfraser@11541 691 local_irq_restore(flags);
kfraser@11541 692 }
kfraser@11541 693
kfraser@15314 694 static void apic_pm_activate(void)
kfraser@15314 695 {
kfraser@15314 696 apic_pm_state.active = 1;
kfraser@15314 697 }
kaf24@8847 698
kaf24@1452 699 /*
kaf24@1452 700 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 701 * Original code written by Keir Fraser.
kaf24@1452 702 */
kaf24@1452 703
kaf24@5211 704 static void __init lapic_disable(char *str)
kaf24@5211 705 {
kaf24@5211 706 enable_local_apic = -1;
kaf24@5211 707 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 708 }
kaf24@5211 709 custom_param("nolapic", lapic_disable);
kaf24@5211 710
kaf24@5211 711 static void __init lapic_enable(char *str)
kaf24@5211 712 {
kaf24@5211 713 enable_local_apic = 1;
kaf24@5211 714 }
kaf24@5211 715 custom_param("lapic", lapic_enable);
kaf24@5211 716
kaf24@4888 717 static void __init apic_set_verbosity(char *str)
kaf24@4888 718 {
kaf24@4888 719 if (strcmp("debug", str) == 0)
kaf24@4888 720 apic_verbosity = APIC_DEBUG;
kaf24@4888 721 else if (strcmp("verbose", str) == 0)
kaf24@4888 722 apic_verbosity = APIC_VERBOSE;
kaf24@5211 723 else
kaf24@5211 724 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@5211 725 " use apic_verbosity=verbose or apic_verbosity=debug", str);
kaf24@4888 726 }
kaf24@5211 727 custom_param("apic_verbosity", apic_set_verbosity);
kaf24@4888 728
kaf24@1452 729 static int __init detect_init_APIC (void)
kaf24@1452 730 {
kaf24@1452 731 u32 h, l, features;
kaf24@1452 732
kaf24@5211 733 /* Disabled by kernel option? */
kaf24@5211 734 if (enable_local_apic < 0)
kaf24@5211 735 return -1;
kaf24@5211 736
kaf24@1452 737 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 738 case X86_VENDOR_AMD:
iap10@4548 739 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 740 (boot_cpu_data.x86 == 15))
kaf24@1452 741 break;
kaf24@1452 742 goto no_apic;
kaf24@1452 743 case X86_VENDOR_INTEL:
iap10@4548 744 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 745 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 746 break;
kaf24@1452 747 goto no_apic;
kaf24@1452 748 default:
kaf24@1452 749 goto no_apic;
kaf24@1452 750 }
kaf24@1452 751
kaf24@1452 752 if (!cpu_has_apic) {
kaf24@1452 753 /*
kaf24@5211 754 * Over-ride BIOS and try to enable the local
kaf24@5211 755 * APIC only if "lapic" specified.
kaf24@5211 756 */
kaf24@5211 757 if (enable_local_apic <= 0) {
kaf24@5211 758 printk("Local APIC disabled by BIOS -- "
kaf24@5211 759 "you can enable it with \"lapic\"\n");
kaf24@5211 760 return -1;
kaf24@5211 761 }
kaf24@5211 762 /*
kaf24@1452 763 * Some BIOSes disable the local APIC in the
kaf24@1452 764 * APIC_BASE MSR. This can only be done in
iap10@4548 765 * software for Intel P6 or later and AMD K7
iap10@4548 766 * (Model > 1) or later.
kaf24@1452 767 */
kaf24@1452 768 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 769 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 770 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 771 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 772 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 773 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 774 enabled_via_apicbase = 1;
kaf24@1452 775 }
kaf24@1452 776 }
kaf24@4888 777 /*
kaf24@4888 778 * The APIC feature bit should now be enabled
kaf24@4888 779 * in `cpuid'
kaf24@4888 780 */
kaf24@1452 781 features = cpuid_edx(1);
kaf24@1452 782 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 783 printk("Could not enable APIC!\n");
kaf24@1452 784 return -1;
kaf24@1452 785 }
kaf24@4619 786
iap10@4548 787 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 788 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 789
kaf24@1452 790 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 791 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 792 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 793 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 794
kaf24@4619 795 if (nmi_watchdog != NMI_NONE)
kaf24@4619 796 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 797
kaf24@1452 798 printk("Found and enabled local APIC!\n");
iap10@4548 799
kaf24@8847 800 apic_pm_activate();
kaf24@8847 801
kaf24@1452 802 return 0;
kaf24@1452 803
iap10@4548 804 no_apic:
kaf24@1452 805 printk("No local APIC present or hardware disabled\n");
kaf24@1452 806 return -1;
kaf24@1452 807 }
kaf24@1452 808
kaf24@1452 809 void __init init_apic_mappings(void)
kaf24@1452 810 {
iap10@4548 811 unsigned long apic_phys;
kaf24@1452 812
kaf24@1452 813 /*
iap10@4548 814 * If no local APIC can be found then set up a fake all
iap10@4548 815 * zeroes page to simulate the local APIC and another
iap10@4548 816 * one for the IO-APIC.
kaf24@1452 817 */
kaf24@9582 818 if (!smp_found_config && detect_init_APIC()) {
kaf24@5398 819 apic_phys = __pa(alloc_xenheap_page());
kaf24@9582 820 memset(__va(apic_phys), 0, PAGE_SIZE);
kaf24@9582 821 } else
kaf24@1452 822 apic_phys = mp_lapic_addr;
kaf24@1452 823
kaf24@1452 824 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 825 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 826 apic_phys);
kaf24@1452 827
kaf24@1452 828 /*
kaf24@1452 829 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 830 * default configuration (or the MP table is broken).
kaf24@1452 831 */
kaf24@1452 832 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 833 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 834
kaf24@1452 835 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 836 {
iap10@4548 837 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 838 int i;
kaf24@1452 839
kaf24@1452 840 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 841 if (smp_found_config) {
kaf24@1452 842 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 843 if (!ioapic_phys) {
iap10@4548 844 printk(KERN_ERR
iap10@4548 845 "WARNING: bogus zero IO-APIC "
iap10@4548 846 "address found in MPTABLE, "
iap10@4548 847 "disabling IO/APIC support!\n");
iap10@4548 848 smp_found_config = 0;
iap10@4548 849 skip_ioapic_setup = 1;
iap10@4548 850 goto fake_ioapic_page;
iap10@4548 851 }
iap10@4548 852 } else {
iap10@4548 853 fake_ioapic_page:
kaf24@5398 854 ioapic_phys = __pa(alloc_xenheap_page());
kaf24@9582 855 memset(__va(ioapic_phys), 0, PAGE_SIZE);
iap10@4548 856 }
kaf24@1452 857 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 858 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 859 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 860 idx++;
kaf24@1452 861 }
kaf24@1452 862 }
kaf24@1452 863 #endif
kaf24@1452 864 }
kaf24@1452 865
kaf24@1452 866 /*****************************************************************************
kaf24@1452 867 * APIC calibration
kaf24@1452 868 *
kaf24@1452 869 * The APIC is programmed in bus cycles.
kaf24@1452 870 * Timeout values should specified in real time units.
kaf24@1452 871 * The "cheapest" time source is the cyclecounter.
kaf24@1452 872 *
kaf24@1452 873 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 874 *
kaf24@1452 875 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 876 * timer chip to generate periodic timer interupts.
kaf24@1452 877 *****************************************************************************/
kaf24@1452 878
kaf24@1452 879 /* used for system time scaling */
kaf24@1672 880 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 881 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 882 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 883
kaf24@1452 884 /*
kaf24@1452 885 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 886 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 887 * to calibrate.
kaf24@1452 888 */
kaf24@1452 889 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 890 {
kaf24@1452 891 /*extern spinlock_t i8253_lock;*/
kaf24@1452 892 /*unsigned long flags;*/
iap10@4548 893
kaf24@1452 894 unsigned int count;
iap10@4548 895
kaf24@1452 896 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 897
iap10@4548 898 outb_p(0x00, PIT_MODE);
iap10@4548 899 count = inb_p(PIT_CH0);
iap10@4548 900 count |= inb_p(PIT_CH0) << 8;
iap10@4548 901
kaf24@1452 902 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 903
kaf24@1452 904 return count;
kaf24@1452 905 }
kaf24@1452 906
iap10@4548 907 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 908 static void __init wait_8254_wraparound(void)
kaf24@1452 909 {
kaf24@4888 910 unsigned int curr_count, prev_count;
kaf24@4888 911
kaf24@1452 912 curr_count = get_8254_timer_count();
kaf24@1452 913 do {
kaf24@1452 914 prev_count = curr_count;
kaf24@1452 915 curr_count = get_8254_timer_count();
iap10@4548 916
kaf24@4888 917 /* workaround for broken Mercury/Neptune */
kaf24@4888 918 if (prev_count >= curr_count + 0x100)
kaf24@4888 919 curr_count = get_8254_timer_count();
kaf24@4888 920
kaf24@4888 921 } while (prev_count >= curr_count);
kaf24@1452 922 }
kaf24@1452 923
kaf24@1452 924 /*
iap10@4548 925 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 926 * we override this later
iap10@4548 927 */
kaf24@4888 928 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 929
iap10@4548 930 /*
kaf24@1452 931 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 932 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 933 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 934 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 935 * call this function only once, with the real, calibrated value.
kaf24@1452 936 *
kaf24@1452 937 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 938 * P5 APIC double write bug.
kaf24@1452 939 */
iap10@4548 940
kaf24@1452 941 #define APIC_DIVISOR 1
iap10@4548 942
kaf24@5146 943 void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 944 {
iap10@4548 945 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 946
iap10@4548 947 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 948 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 949 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 950 if (!APIC_INTEGRATED(ver))
iap10@4548 951 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 952 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 953
kaf24@1452 954 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 955 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 956
kaf24@1452 957 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 958 }
kaf24@1452 959
kaf24@5146 960 static void __init setup_APIC_timer(unsigned int clocks)
kaf24@1452 961 {
kaf24@1452 962 unsigned long flags;
kaf24@5146 963 local_irq_save(flags);
kaf24@5146 964 __setup_APIC_LVTT(clocks);
kaf24@5146 965 local_irq_restore(flags);
kaf24@1452 966 }
kaf24@1452 967
kaf24@1452 968 /*
kaf24@5146 969 * In this function we calibrate APIC bus clocks to the external
kaf24@5146 970 * timer. Unfortunately we cannot use jiffies and the timer irq
kaf24@5146 971 * to calibrate, since some later bootup code depends on getting
kaf24@5146 972 * the first irq? Ugh.
kaf24@1452 973 *
kaf24@5146 974 * We want to do the calibration only once since we
kaf24@5146 975 * want to have local timer irqs syncron. CPUs connected
kaf24@5146 976 * by the same APIC bus have the very same bus frequency.
kaf24@5146 977 * And we want to have irqs off anyways, no accidental
kaf24@5146 978 * APIC irq that way.
kaf24@1452 979 */
kaf24@1452 980
kaf24@1452 981 int __init calibrate_APIC_clock(void)
kaf24@1452 982 {
kaf24@1452 983 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 984 long tt1, tt2;
kaf24@1452 985 long result;
kaf24@1452 986 int i;
kaf24@1452 987 const int LOOPS = HZ/10;
kaf24@1452 988
kaf24@4888 989 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 990
iap10@4548 991 /*
iap10@4548 992 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 993 * value into the APIC clock, we just want to get the
iap10@4548 994 * counter running for calibration.
iap10@4548 995 */
kaf24@1452 996 __setup_APIC_LVTT(1000000000);
kaf24@1452 997
iap10@4548 998 /*
iap10@4548 999 * The timer chip counts down to zero. Let's wait
kaf24@1452 1000 * for a wraparound to start exact measurement:
iap10@4548 1001 * (the current tick might have been already half done)
iap10@4548 1002 */
iap10@4548 1003 wait_timer_tick();
iap10@4548 1004
iap10@4548 1005 /*
iap10@4548 1006 * We wrapped around just now. Let's start:
iap10@4548 1007 */
iap10@4548 1008 if (cpu_has_tsc)
kaf24@4619 1009 rdtscll(t1);
kaf24@1452 1010 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 1011
iap10@4548 1012 /*
iap10@4548 1013 * Let's wait LOOPS wraprounds:
iap10@4548 1014 */
kaf24@1452 1015 for (i = 0; i < LOOPS; i++)
iap10@4548 1016 wait_timer_tick();
kaf24@1452 1017
kaf24@1452 1018 tt2 = apic_read(APIC_TMCCT);
iap10@4548 1019 if (cpu_has_tsc)
kaf24@4619 1020 rdtscll(t2);
kaf24@1452 1021
iap10@4548 1022 /*
iap10@4548 1023 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 1024 * might have overflown, but note that we use signed
kaf24@1452 1025 * longs, thus no extra care needed.
kaf24@4888 1026 *
kaf24@4888 1027 * underflown to be exact, as the timer counts down ;)
iap10@4548 1028 */
iap10@4548 1029
kaf24@1452 1030 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 1031
iap10@4548 1032 if (cpu_has_tsc)
kaf24@4888 1033 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 1034 "%ld.%04ld MHz.\n",
kaf24@4888 1035 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 1036 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 1037
kaf24@4888 1038 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kfraser@11204 1039 "%ld.%04ld MHz.\n",
kfraser@11204 1040 result/(1000000/HZ),
kfraser@11204 1041 result%(1000000/HZ));
kaf24@1452 1042
kaf24@1452 1043 /* set up multipliers for accurate timer code */
kaf24@1452 1044 bus_freq = result*HZ;
kaf24@1452 1045 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 1046 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 1047
kaf24@4888 1048 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 1049 /* reset APIC to zero timeout value */
kaf24@1452 1050 __setup_APIC_LVTT(0);
iap10@4548 1051
kaf24@1452 1052 return result;
kaf24@1452 1053 }
kaf24@1452 1054
kaf24@9184 1055 u32 get_apic_bus_cycle(void)
kaf24@7546 1056 {
kaf24@9184 1057 return bus_cycle;
kaf24@7546 1058 }
kaf24@5146 1059
kaf24@5146 1060 static unsigned int calibration_result;
kaf24@5146 1061
kaf24@5146 1062 void __init setup_boot_APIC_clock(void)
kaf24@1452 1063 {
kaf24@8847 1064 unsigned long flags;
kaf24@5146 1065 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
kaf24@1452 1066 using_apic_timer = 1;
kaf24@5146 1067
kaf24@8847 1068 local_irq_save(flags);
kaf24@8847 1069
kaf24@5146 1070 calibration_result = calibrate_APIC_clock();
kaf24@5146 1071 /*
kaf24@5146 1072 * Now set up the timer for real.
kaf24@5146 1073 */
kaf24@5146 1074 setup_APIC_timer(calibration_result);
kaf24@5146 1075
kaf24@8847 1076 local_irq_restore(flags);
kaf24@5146 1077 }
kaf24@5146 1078
kaf24@8847 1079 void __devinit setup_secondary_APIC_clock(void)
kaf24@5146 1080 {
kaf24@5146 1081 setup_APIC_timer(calibration_result);
kaf24@5146 1082 }
kaf24@5146 1083
kaf24@8847 1084 void disable_APIC_timer(void)
kaf24@5146 1085 {
kaf24@5146 1086 if (using_apic_timer) {
kaf24@5146 1087 unsigned long v;
kaf24@5146 1088
kaf24@5146 1089 v = apic_read(APIC_LVTT);
kaf24@5146 1090 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@5146 1091 }
kaf24@5146 1092 }
kaf24@5146 1093
kaf24@5146 1094 void enable_APIC_timer(void)
kaf24@5146 1095 {
kaf24@5146 1096 if (using_apic_timer) {
kaf24@5146 1097 unsigned long v;
kaf24@5146 1098
kaf24@5146 1099 v = apic_read(APIC_LVTT);
kaf24@5146 1100 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
kaf24@5146 1101 }
kaf24@1452 1102 }
kaf24@1452 1103
kaf24@1452 1104 #undef APIC_DIVISOR
kaf24@1452 1105
kaf24@1452 1106 /*
kaf24@1452 1107 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 1108 * returns 1 on success
kaf24@1452 1109 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 1110 */
kaf24@8586 1111 int reprogram_timer(s_time_t timeout)
kaf24@1452 1112 {
kaf24@1452 1113 s_time_t now;
kaf24@1452 1114 s_time_t expire;
kaf24@1452 1115 u64 apic_tmict;
kaf24@1452 1116
kaf24@1452 1117 /*
kfraser@14340 1118 * If we don't have local APIC then we just poll the timer list off the
kfraser@14340 1119 * PIT interrupt.
kfraser@14340 1120 */
kfraser@14340 1121 if ( !cpu_has_apic )
kfraser@14340 1122 return 1;
kfraser@14340 1123
kfraser@14340 1124 /*
kaf24@1452 1125 * We use this value because we don't trust zero (we think it may just
kaf24@1452 1126 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 1127 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 1128 */
kaf24@1452 1129 if ( timeout == 0 )
kaf24@1452 1130 {
kaf24@1452 1131 apic_tmict = 0xffffffff;
kaf24@1452 1132 goto reprogram;
kaf24@1452 1133 }
kaf24@1452 1134
kaf24@1452 1135 now = NOW();
kaf24@1452 1136 expire = timeout - now; /* value from now */
kaf24@1452 1137
kaf24@1452 1138 if ( expire <= 0 )
kaf24@1452 1139 {
kaf24@1452 1140 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 1141 smp_processor_id(), (u32)(now>>32),
kaf24@1452 1142 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 1143 return 0;
kaf24@1452 1144 }
kaf24@1452 1145
kaf24@1452 1146 /* conversion to bus units */
kaf24@1452 1147 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 1148
kaf24@1452 1149 if ( apic_tmict >= 0xffffffff )
kaf24@1452 1150 {
kaf24@1452 1151 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 1152 apic_tmict = 0xffffffff;
kaf24@1452 1153 }
kaf24@1452 1154
kaf24@1452 1155 if ( apic_tmict == 0 )
kaf24@1452 1156 {
kaf24@1452 1157 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 1158 return 0;
kaf24@1452 1159 }
kaf24@1452 1160
kaf24@1452 1161 reprogram:
kaf24@1452 1162 /* Program the timer. */
kaf24@1452 1163 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 1164
kaf24@1452 1165 return 1;
kaf24@1452 1166 }
kaf24@1452 1167
kaf24@8846 1168 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 1169 {
kaf24@1452 1170 ack_APIC_irq();
kfraser@14595 1171 perfc_incr(apic_timer);
kaf24@8586 1172 raise_softirq(TIMER_SOFTIRQ);
kaf24@1452 1173 }
kaf24@1452 1174
kaf24@1452 1175 /*
kaf24@1452 1176 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 1177 */
kaf24@8846 1178 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1179 {
kaf24@1452 1180 unsigned long v;
kaf24@1452 1181
kaf24@8847 1182 irq_enter();
kaf24@1452 1183 /*
kaf24@1452 1184 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 1185 * if it is a vectored one. Just in case...
kaf24@1452 1186 * Spurious interrupts should not be ACKed.
kaf24@1452 1187 */
kaf24@1452 1188 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 1189 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 1190 ack_APIC_irq();
kaf24@1452 1191
kaf24@1452 1192 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@5146 1193 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 1194 smp_processor_id());
kaf24@8847 1195 irq_exit();
kaf24@1452 1196 }
kaf24@1452 1197
kaf24@1452 1198 /*
kaf24@1452 1199 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 1200 */
kaf24@1452 1201
kaf24@8846 1202 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1203 {
kaf24@1452 1204 unsigned long v, v1;
kaf24@1452 1205
kaf24@8847 1206 irq_enter();
kaf24@1452 1207 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 1208 v = apic_read(APIC_ESR);
kaf24@1452 1209 apic_write(APIC_ESR, 0);
kaf24@1452 1210 v1 = apic_read(APIC_ESR);
kaf24@1452 1211 ack_APIC_irq();
kaf24@1452 1212 atomic_inc(&irq_err_count);
kaf24@1452 1213
kaf24@1452 1214 /* Here is what the APIC error bits mean:
kaf24@1452 1215 0: Send CS error
kaf24@1452 1216 1: Receive CS error
kaf24@1452 1217 2: Send accept error
kaf24@1452 1218 3: Receive accept error
kaf24@1452 1219 4: Reserved
kaf24@1452 1220 5: Send illegal vector
kaf24@1452 1221 6: Received illegal vector
kaf24@1452 1222 7: Illegal register address
kaf24@1452 1223 */
kaf24@5146 1224 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@5146 1225 smp_processor_id(), v , v1);
kaf24@8847 1226 irq_exit();
kaf24@1452 1227 }
kaf24@1452 1228
kaf24@1452 1229 /*
kaf24@1452 1230 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 1231 * a UP kernel.
kaf24@1452 1232 */
kaf24@1452 1233 int __init APIC_init_uniprocessor (void)
kaf24@1452 1234 {
kaf24@5211 1235 if (enable_local_apic < 0)
kaf24@5211 1236 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 1237
kaf24@1452 1238 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 1239 return -1;
kaf24@1452 1240
kaf24@1452 1241 /*
kaf24@1452 1242 * Complain if the BIOS pretends there is one.
kaf24@1452 1243 */
iap10@4548 1244 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 1245 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 1246 boot_cpu_physical_apicid);
kfraser@11541 1247 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 1248 return -1;
kaf24@1452 1249 }
kaf24@1452 1250
kaf24@1452 1251 verify_local_APIC();
kaf24@1452 1252
kaf24@1452 1253 connect_bsp_APIC();
kaf24@1452 1254
kfraser@11541 1255 /*
kfraser@11541 1256 * Hack: In case of kdump, after a crash, kernel might be booting
kfraser@11541 1257 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
kfraser@11541 1258 * might be zero if read from MP tables. Get it from LAPIC.
kfraser@11541 1259 */
kfraser@11541 1260 #ifdef CONFIG_CRASH_DUMP
kfraser@11541 1261 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kfraser@11541 1262 #endif
kaf24@4804 1263 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 1264
kaf24@1452 1265 setup_local_APIC();
kaf24@1452 1266
kaf24@5146 1267 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@5146 1268 check_nmi_watchdog();
kaf24@1452 1269 #ifdef CONFIG_X86_IO_APIC
iap10@4548 1270 if (smp_found_config)
iap10@4548 1271 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 1272 setup_IO_APIC();
iap10@4548 1273 #endif
kaf24@5146 1274 setup_boot_APIC_clock();
kaf24@1452 1275
kaf24@1452 1276 return 0;
kaf24@1452 1277 }