ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 4804:3404966959f2

bitkeeper revision 1.1389.10.1 (427fa2d3ZV92f_ErvLuIzWbV1f67QA)

Phase 1 of upgrading platform code to be derived from Linux 2.6.11
rather than 2.4.x.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon May 09 17:50:11 2005 +0000 (2005-05-09)
parents 38a02ee9a9c8
children f470118a979e
rev   line source
kaf24@1452 1 /*
iap10@4548 2 * based on linux-2.6.10/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kaf24@1452 13 * Maciej W. Rozycki : Various updates and fixes.
kaf24@1452 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@1452 40 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 41 int using_apic_timer = 0;
kaf24@1452 42
kaf24@4804 43 int apic_verbosity;
kaf24@4804 44
kaf24@1452 45 static int enabled_via_apicbase;
kaf24@1452 46
kaf24@4804 47 int get_physical_broadcast(void)
kaf24@4804 48 {
kaf24@4804 49 unsigned int lvr, version;
kaf24@4804 50 lvr = apic_read(APIC_LVR);
kaf24@4804 51 version = GET_APIC_VERSION(lvr);
kaf24@4804 52 if (!APIC_INTEGRATED(version) || version >= 0x14)
kaf24@4804 53 return 0xff;
kaf24@4804 54 else
kaf24@4804 55 return 0xf;
kaf24@4804 56 }
kaf24@4804 57
kaf24@1452 58 int get_maxlvt(void)
kaf24@1452 59 {
kaf24@1452 60 unsigned int v, ver, maxlvt;
kaf24@1452 61
kaf24@1452 62 v = apic_read(APIC_LVR);
kaf24@1452 63 ver = GET_APIC_VERSION(v);
kaf24@1452 64 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 65 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 66 return maxlvt;
kaf24@1452 67 }
kaf24@1452 68
kaf24@1452 69 void clear_local_APIC(void)
kaf24@1452 70 {
kaf24@1452 71 int maxlvt;
kaf24@1452 72 unsigned long v;
kaf24@1452 73
kaf24@1452 74 maxlvt = get_maxlvt();
kaf24@1452 75
kaf24@1452 76 /*
kaf24@1452 77 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 78 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 79 */
kaf24@1452 80 if (maxlvt >= 3) {
kaf24@1452 81 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 82 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 83 }
kaf24@1452 84 /*
kaf24@1452 85 * Careful: we have to set masks only first to deassert
kaf24@1452 86 * any level-triggered sources.
kaf24@1452 87 */
kaf24@1452 88 v = apic_read(APIC_LVTT);
kaf24@1452 89 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 90 v = apic_read(APIC_LVT0);
kaf24@1452 91 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 92 v = apic_read(APIC_LVT1);
kaf24@1452 93 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 94 if (maxlvt >= 4) {
kaf24@1452 95 v = apic_read(APIC_LVTPC);
kaf24@1452 96 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 97 }
kaf24@1452 98
kaf24@1452 99 /*
kaf24@1452 100 * Clean APIC state for other OSs:
kaf24@1452 101 */
kaf24@1452 102 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 103 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 104 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 105 if (maxlvt >= 3)
kaf24@1452 106 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 107 if (maxlvt >= 4)
kaf24@1452 108 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 109
kaf24@1452 110 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@1452 111 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 112 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 113 apic_write(APIC_ESR, 0);
kaf24@1452 114 apic_read(APIC_ESR);
kaf24@1452 115 }
kaf24@1452 116 }
kaf24@1452 117
kaf24@1452 118 void __init connect_bsp_APIC(void)
kaf24@1452 119 {
kaf24@1452 120 if (pic_mode) {
kaf24@1452 121 /*
kaf24@1452 122 * Do not trust the local APIC being empty at bootup.
kaf24@1452 123 */
kaf24@1452 124 clear_local_APIC();
kaf24@1452 125 /*
kaf24@1452 126 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 127 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 128 */
kaf24@1452 129 printk("leaving PIC mode, enabling APIC mode.\n");
kaf24@1452 130 outb(0x70, 0x22);
kaf24@1452 131 outb(0x01, 0x23);
kaf24@1452 132 }
kaf24@1452 133 }
kaf24@1452 134
kaf24@1452 135 void disconnect_bsp_APIC(void)
kaf24@1452 136 {
kaf24@1452 137 if (pic_mode) {
kaf24@1452 138 /*
kaf24@1452 139 * Put the board back into PIC mode (has an effect
kaf24@1452 140 * only on certain older boards). Note that APIC
kaf24@1452 141 * interrupts, including IPIs, won't work beyond
kaf24@1452 142 * this point! The only exception are INIT IPIs.
kaf24@1452 143 */
kaf24@1452 144 printk("disabling APIC mode, entering PIC mode.\n");
kaf24@1452 145 outb(0x70, 0x22);
kaf24@1452 146 outb(0x00, 0x23);
kaf24@1452 147 }
kaf24@1452 148 }
kaf24@1452 149
kaf24@1452 150 void disable_local_APIC(void)
kaf24@1452 151 {
kaf24@1452 152 unsigned long value;
kaf24@1452 153
kaf24@1452 154 clear_local_APIC();
kaf24@1452 155
kaf24@1452 156 /*
kaf24@1452 157 * Disable APIC (implies clearing of registers
kaf24@1452 158 * for 82489DX!).
kaf24@1452 159 */
kaf24@1452 160 value = apic_read(APIC_SPIV);
kaf24@1452 161 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 162 apic_write_around(APIC_SPIV, value);
kaf24@1452 163
kaf24@1452 164 if (enabled_via_apicbase) {
kaf24@1452 165 unsigned int l, h;
kaf24@1452 166 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 167 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 168 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 169 }
kaf24@1452 170 }
kaf24@1452 171
kaf24@1452 172 /*
kaf24@1452 173 * This is to verify that we're looking at a real local APIC.
kaf24@1452 174 * Check these against your board if the CPUs aren't getting
kaf24@1452 175 * started for no apparent reason.
kaf24@1452 176 */
kaf24@1452 177 int __init verify_local_APIC(void)
kaf24@1452 178 {
kaf24@1452 179 unsigned int reg0, reg1;
kaf24@1452 180
kaf24@1452 181 /*
kaf24@1452 182 * The version register is read-only in a real APIC.
kaf24@1452 183 */
kaf24@1452 184 reg0 = apic_read(APIC_LVR);
kaf24@1452 185 Dprintk("Getting VERSION: %x\n", reg0);
kaf24@1452 186 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 187 reg1 = apic_read(APIC_LVR);
kaf24@1452 188 Dprintk("Getting VERSION: %x\n", reg1);
kaf24@1452 189
kaf24@1452 190 /*
kaf24@1452 191 * The two version reads above should print the same
kaf24@1452 192 * numbers. If the second one is different, then we
kaf24@1452 193 * poke at a non-APIC.
kaf24@1452 194 */
kaf24@1452 195 if (reg1 != reg0)
kaf24@1452 196 return 0;
kaf24@1452 197
kaf24@1452 198 /*
kaf24@1452 199 * Check if the version looks reasonably.
kaf24@1452 200 */
kaf24@1452 201 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 202 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 203 return 0;
kaf24@1452 204 reg1 = get_maxlvt();
kaf24@1452 205 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 206 return 0;
kaf24@1452 207
kaf24@1452 208 /*
kaf24@1452 209 * The ID register is read/write in a real APIC.
kaf24@1452 210 */
kaf24@1452 211 reg0 = apic_read(APIC_ID);
kaf24@1452 212 Dprintk("Getting ID: %x\n", reg0);
kaf24@1452 213
kaf24@1452 214 /*
kaf24@1452 215 * The next two are just to see if we have sane values.
kaf24@1452 216 * They're only really relevant if we're in Virtual Wire
kaf24@1452 217 * compatibility mode, but most boxes are anymore.
kaf24@1452 218 */
kaf24@1452 219 reg0 = apic_read(APIC_LVT0);
kaf24@1452 220 Dprintk("Getting LVT0: %x\n", reg0);
kaf24@1452 221 reg1 = apic_read(APIC_LVT1);
kaf24@1452 222 Dprintk("Getting LVT1: %x\n", reg1);
kaf24@1452 223
kaf24@1452 224 return 1;
kaf24@1452 225 }
kaf24@1452 226
kaf24@1452 227 void __init sync_Arb_IDs(void)
kaf24@1452 228 {
iap10@4548 229 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
iap10@4548 230 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
iap10@4548 231 if (ver >= 0x14) /* P4 or higher */
iap10@4548 232 return;
kaf24@1452 233 /*
kaf24@1452 234 * Wait for idle.
kaf24@1452 235 */
kaf24@1452 236 apic_wait_icr_idle();
kaf24@1452 237
kaf24@1452 238 Dprintk("Synchronizing Arb IDs.\n");
kaf24@1452 239 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 240 | APIC_DM_INIT);
kaf24@1452 241 }
kaf24@1452 242
kaf24@1452 243 extern void __error_in_apic_c (void);
kaf24@1452 244
kaf24@1452 245 void __init init_bsp_APIC(void)
kaf24@1452 246 {
kaf24@4620 247 unsigned long value, ver;
kaf24@4620 248
kaf24@4620 249 /*
kaf24@4620 250 * Don't do the setup now if we have a SMP BIOS as the through-I/O-APIC
kaf24@4620 251 * virtual wire mode might be active.
kaf24@4620 252 */
kaf24@4620 253 if (smp_found_config || !cpu_has_apic)
kaf24@4620 254 return;
kaf24@4620 255
kaf24@4620 256 value = apic_read(APIC_LVR);
kaf24@4620 257 ver = GET_APIC_VERSION(value);
kaf24@4620 258
kaf24@4620 259 /*
kaf24@4620 260 * Do not trust the local APIC being empty at bootup.
kaf24@4620 261 */
kaf24@4620 262 clear_local_APIC();
kaf24@4620 263
kaf24@4620 264 /*
kaf24@4620 265 * Enable APIC.
kaf24@4620 266 */
kaf24@4620 267 value = apic_read(APIC_SPIV);
kaf24@4620 268 value &= ~APIC_VECTOR_MASK;
kaf24@4620 269 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 270
kaf24@4620 271 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 272 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 273 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 274 else
kaf24@4620 275 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 276 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 277 apic_write_around(APIC_SPIV, value);
kaf24@4620 278
kaf24@4620 279 /*
kaf24@4620 280 * Set up the virtual wire mode.
kaf24@4620 281 */
kaf24@4620 282 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 283 value = APIC_DM_NMI;
kaf24@4620 284 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 285 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 286 apic_write_around(APIC_LVT1, value);
kaf24@1452 287 }
kaf24@1452 288
kaf24@1452 289 void __init setup_local_APIC (void)
kaf24@1452 290 {
iap10@4548 291 unsigned long oldvalue, value, ver, maxlvt;
iap10@4548 292
iap10@4548 293 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 294 if (esr_disable) {
iap10@4548 295 apic_write(APIC_ESR, 0);
iap10@4548 296 apic_write(APIC_ESR, 0);
iap10@4548 297 apic_write(APIC_ESR, 0);
iap10@4548 298 apic_write(APIC_ESR, 0);
iap10@4548 299 }
kaf24@1452 300
kaf24@1452 301 value = apic_read(APIC_LVR);
kaf24@1452 302 ver = GET_APIC_VERSION(value);
kaf24@1452 303
kaf24@1452 304 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 305 __error_in_apic_c();
kaf24@1452 306
iap10@4548 307 /*
iap10@4548 308 * Double-check whether this APIC is really registered.
iap10@4548 309 */
iap10@4548 310 if (!apic_id_registered())
kaf24@1452 311 BUG();
kaf24@1452 312
kaf24@1452 313 /*
kaf24@1452 314 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 315 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 316 * document number 292116). So here it goes...
kaf24@1452 317 */
iap10@4548 318 init_apic_ldr();
kaf24@1452 319
kaf24@1452 320 /*
kaf24@1452 321 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 322 * later on.
kaf24@1452 323 */
kaf24@1452 324 value = apic_read(APIC_TASKPRI);
kaf24@1452 325 value &= ~APIC_TPRI_MASK;
kaf24@1452 326 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 327
kaf24@1452 328 /*
kaf24@1452 329 * Now that we are all set up, enable the APIC
kaf24@1452 330 */
kaf24@1452 331 value = apic_read(APIC_SPIV);
kaf24@1452 332 value &= ~APIC_VECTOR_MASK;
kaf24@1452 333 /*
kaf24@1452 334 * Enable APIC
kaf24@1452 335 */
kaf24@1452 336 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 337
iap10@4548 338 /*
iap10@4548 339 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 340 * certain networking cards. If high frequency interrupts are
iap10@4548 341 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 342 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 343 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 344 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 345 * away, oh well :-(
iap10@4548 346 *
iap10@4548 347 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 348 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 349 * BX chipset. ]
iap10@4548 350 */
iap10@4548 351 /*
iap10@4548 352 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 353 * frequent as it makes the interrupt distributon model be more
iap10@4548 354 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 355 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 356 */
iap10@4548 357 #if 1
kaf24@1452 358 /* Enable focus processor (bit==0) */
kaf24@1452 359 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 360 #else
iap10@4548 361 /* Disable focus processor (bit==1) */
iap10@4548 362 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 363 #endif
iap10@4548 364 /*
iap10@4548 365 * Set spurious IRQ vector
iap10@4548 366 */
kaf24@1452 367 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 368 apic_write_around(APIC_SPIV, value);
kaf24@1452 369
kaf24@1452 370 /*
kaf24@1452 371 * Set up LVT0, LVT1:
kaf24@1452 372 *
kaf24@1452 373 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 374 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 375 * we delegate interrupts to the 8259A.
kaf24@1452 376 */
kaf24@1452 377 /*
kaf24@1452 378 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 379 */
kaf24@1452 380 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 381 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 382 value = APIC_DM_EXTINT;
kaf24@1452 383 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
kaf24@1452 384 } else {
kaf24@1452 385 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@1452 386 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
kaf24@1452 387 }
kaf24@1452 388 apic_write_around(APIC_LVT0, value);
kaf24@1452 389
kaf24@1452 390 /*
kaf24@1452 391 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 392 */
kaf24@1452 393 if (!smp_processor_id())
kaf24@1452 394 value = APIC_DM_NMI;
kaf24@1452 395 else
kaf24@1452 396 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 397 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 398 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 399 apic_write_around(APIC_LVT1, value);
kaf24@1452 400
iap10@4548 401 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 402 maxlvt = get_maxlvt();
kaf24@1452 403 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 404 apic_write(APIC_ESR, 0);
iap10@4548 405 oldvalue = apic_read(APIC_ESR);
kaf24@1452 406
iap10@4548 407 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 408 apic_write_around(APIC_LVTERR, value);
iap10@4548 409 /*
iap10@4548 410 * spec says clear errors after enabling vector.
iap10@4548 411 */
kaf24@1452 412 if (maxlvt > 3)
kaf24@1452 413 apic_write(APIC_ESR, 0);
kaf24@1452 414 value = apic_read(APIC_ESR);
iap10@4548 415 if (value != oldvalue)
iap10@4548 416 printk("ESR value before enabling vector: 0x%08lx "
iap10@4548 417 "after: 0x%08lx\n", oldvalue, value);
kaf24@1452 418 } else {
iap10@4548 419 if (esr_disable)
iap10@4548 420 /*
iap10@4548 421 * Something untraceble is creating bad interrupts on
iap10@4548 422 * secondary quads ... for the moment, just leave the
iap10@4548 423 * ESR disabled - we can't do anything useful with the
iap10@4548 424 * errors anyway - mbligh
iap10@4548 425 */
iap10@4548 426 printk("Leaving ESR disabled.\n");
iap10@4548 427 else
kaf24@1452 428 printk("No ESR for 82489DX.\n");
kaf24@1452 429 }
kaf24@1452 430
iap10@4548 431 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@1452 432 setup_apic_nmi_watchdog();
kaf24@1452 433 }
kaf24@1452 434
kaf24@1452 435 /*
kaf24@1452 436 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 437 * Original code written by Keir Fraser.
kaf24@1452 438 */
kaf24@1452 439
kaf24@1452 440 static int __init detect_init_APIC (void)
kaf24@1452 441 {
kaf24@1452 442 u32 h, l, features;
kaf24@1452 443 extern void get_cpu_vendor(struct cpuinfo_x86*);
kaf24@1452 444
kaf24@1452 445 /* Workaround for us being called before identify_cpu(). */
kaf24@1452 446 get_cpu_vendor(&boot_cpu_data);
kaf24@1452 447
kaf24@1452 448 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 449 case X86_VENDOR_AMD:
iap10@4548 450 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 451 (boot_cpu_data.x86 == 15))
kaf24@1452 452 break;
kaf24@1452 453 goto no_apic;
kaf24@1452 454 case X86_VENDOR_INTEL:
iap10@4548 455 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 456 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 457 break;
kaf24@1452 458 goto no_apic;
kaf24@1452 459 default:
kaf24@1452 460 goto no_apic;
kaf24@1452 461 }
kaf24@1452 462
kaf24@1452 463 if (!cpu_has_apic) {
kaf24@1452 464 /*
kaf24@1452 465 * Some BIOSes disable the local APIC in the
kaf24@1452 466 * APIC_BASE MSR. This can only be done in
iap10@4548 467 * software for Intel P6 or later and AMD K7
iap10@4548 468 * (Model > 1) or later.
kaf24@1452 469 */
kaf24@1452 470 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 471 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 472 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 473 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 474 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 475 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 476 enabled_via_apicbase = 1;
kaf24@1452 477 }
kaf24@1452 478 }
kaf24@4619 479
kaf24@4619 480 /* The APIC feature bit should now be enabled in `cpuid' */
kaf24@1452 481 features = cpuid_edx(1);
kaf24@1452 482 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 483 printk("Could not enable APIC!\n");
kaf24@1452 484 return -1;
kaf24@1452 485 }
kaf24@4619 486
iap10@4548 487 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 488 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 489
kaf24@1452 490 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 491 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 492 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 493 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 494
kaf24@4619 495 if (nmi_watchdog != NMI_NONE)
kaf24@4619 496 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 497
kaf24@1452 498 printk("Found and enabled local APIC!\n");
iap10@4548 499
kaf24@1452 500 return 0;
kaf24@1452 501
iap10@4548 502 no_apic:
kaf24@1452 503 printk("No local APIC present or hardware disabled\n");
kaf24@1452 504 return -1;
kaf24@1452 505 }
kaf24@1452 506
kaf24@1452 507 void __init init_apic_mappings(void)
kaf24@1452 508 {
iap10@4548 509 unsigned long apic_phys;
kaf24@1452 510
kaf24@1452 511 /*
iap10@4548 512 * If no local APIC can be found then set up a fake all
iap10@4548 513 * zeroes page to simulate the local APIC and another
iap10@4548 514 * one for the IO-APIC.
kaf24@1452 515 */
kaf24@1452 516 if (!smp_found_config && detect_init_APIC()) {
kaf24@1920 517 apic_phys = alloc_xenheap_page();
kaf24@1452 518 apic_phys = __pa(apic_phys);
kaf24@1452 519 } else
kaf24@1452 520 apic_phys = mp_lapic_addr;
kaf24@1452 521
kaf24@1452 522 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@1452 523 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
kaf24@1452 524
kaf24@1452 525 /*
kaf24@1452 526 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 527 * default configuration (or the MP table is broken).
kaf24@1452 528 */
kaf24@1452 529 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 530 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 531
kaf24@1452 532 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 533 {
iap10@4548 534 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 535 int i;
kaf24@1452 536
kaf24@1452 537 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 538 if (smp_found_config) {
kaf24@1452 539 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 540 if (!ioapic_phys) {
iap10@4548 541 printk(KERN_ERR
iap10@4548 542 "WARNING: bogus zero IO-APIC "
iap10@4548 543 "address found in MPTABLE, "
iap10@4548 544 "disabling IO/APIC support!\n");
iap10@4548 545 smp_found_config = 0;
iap10@4548 546 skip_ioapic_setup = 1;
iap10@4548 547 goto fake_ioapic_page;
iap10@4548 548 }
iap10@4548 549 } else {
iap10@4548 550 fake_ioapic_page:
iap10@4548 551 ioapic_phys = alloc_xenheap_page();
iap10@4548 552 ioapic_phys = __pa(ioapic_phys);
iap10@4548 553 }
kaf24@1452 554 set_fixmap_nocache(idx, ioapic_phys);
kaf24@1452 555 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
kaf24@1508 556 fix_to_virt(idx), ioapic_phys);
kaf24@1452 557 idx++;
kaf24@1452 558 }
kaf24@1452 559 }
kaf24@1452 560 #endif
kaf24@1452 561 }
kaf24@1452 562
kaf24@1452 563 /*****************************************************************************
kaf24@1452 564 * APIC calibration
kaf24@1452 565 *
kaf24@1452 566 * The APIC is programmed in bus cycles.
kaf24@1452 567 * Timeout values should specified in real time units.
kaf24@1452 568 * The "cheapest" time source is the cyclecounter.
kaf24@1452 569 *
kaf24@1452 570 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 571 *
kaf24@1452 572 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 573 * timer chip to generate periodic timer interupts.
kaf24@1452 574 *****************************************************************************/
kaf24@1452 575
kaf24@1452 576 /* used for system time scaling */
kaf24@1672 577 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 578 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 579 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 580
kaf24@1452 581 /*
kaf24@1452 582 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 583 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 584 * to calibrate.
kaf24@1452 585 */
kaf24@1452 586 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 587 {
kaf24@1452 588 /*extern spinlock_t i8253_lock;*/
kaf24@1452 589 /*unsigned long flags;*/
iap10@4548 590
kaf24@1452 591 unsigned int count;
iap10@4548 592
kaf24@1452 593 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 594
iap10@4548 595 outb_p(0x00, PIT_MODE);
iap10@4548 596 count = inb_p(PIT_CH0);
iap10@4548 597 count |= inb_p(PIT_CH0) << 8;
iap10@4548 598
kaf24@1452 599 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 600
kaf24@1452 601 return count;
kaf24@1452 602 }
kaf24@1452 603
iap10@4548 604 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 605 static void __init wait_8254_wraparound(void)
kaf24@1452 606 {
kaf24@1452 607 unsigned int curr_count, prev_count=~0;
kaf24@1452 608 int delta;
iap10@4548 609
kaf24@1452 610 curr_count = get_8254_timer_count();
iap10@4548 611
kaf24@1452 612 do {
kaf24@1452 613 prev_count = curr_count;
kaf24@1452 614 curr_count = get_8254_timer_count();
kaf24@1452 615 delta = curr_count-prev_count;
iap10@4548 616
kaf24@1452 617 /*
kaf24@4619 618 * This limit for delta seems arbitrary, but it isn't, it's slightly
kaf24@4619 619 * above the level of error a buggy Mercury/Neptune chipset timer can
kaf24@4619 620 * cause.
kaf24@1452 621 */
kaf24@1452 622 } while (delta < 300);
kaf24@1452 623 }
kaf24@1452 624
kaf24@1452 625 /*
iap10@4548 626 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 627 * we override this later
iap10@4548 628 */
iap10@4548 629 void (*wait_timer_tick)(void) = wait_8254_wraparound;
iap10@4548 630
iap10@4548 631 /*
kaf24@1452 632 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 633 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@1452 634 * this function with a very large value and read the current time after
kaf24@1452 635 * a well defined period of time as expired.
kaf24@1452 636 *
kaf24@1452 637 * Calibration is only performed once, for CPU0!
kaf24@1452 638 *
kaf24@1452 639 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 640 * P5 APIC double write bug.
kaf24@1452 641 */
iap10@4548 642
kaf24@1452 643 #define APIC_DIVISOR 1
iap10@4548 644
kaf24@1452 645 static void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 646 {
iap10@4548 647 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 648
iap10@4548 649 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 650 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 651 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 652 if (!APIC_INTEGRATED(ver))
iap10@4548 653 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 654 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 655
kaf24@1452 656 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 657 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 658
kaf24@1452 659 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 660 }
kaf24@1452 661
kaf24@1452 662 /*
kaf24@1452 663 * this is done for every CPU from setup_APIC_clocks() below.
kaf24@1452 664 * We setup each local APIC with a zero timeout value for now.
kaf24@1452 665 * Unlike Linux, we don't have to wait for slices etc.
kaf24@1452 666 */
kaf24@1452 667 void setup_APIC_timer(void * data)
kaf24@1452 668 {
kaf24@1452 669 unsigned long flags;
kaf24@1452 670 __save_flags(flags);
kaf24@1452 671 __sti();
kaf24@1452 672 __setup_APIC_LVTT(0);
kaf24@1452 673 __restore_flags(flags);
kaf24@1452 674 }
kaf24@1452 675
kaf24@1452 676 /*
kaf24@1452 677 * In this function we calibrate APIC bus clocks to the external timer.
kaf24@1452 678 *
iap10@4548 679 * As a result we have the Bus Speed and CPU speed in Hz.
kaf24@1452 680 *
kaf24@1452 681 * We want to do the calibration only once (for CPU0). CPUs connected by the
kaf24@1452 682 * same APIC bus have the very same bus frequency.
kaf24@1452 683 *
kaf24@1452 684 * This bit is a bit shoddy since we use the very same periodic timer interrupt
kaf24@1452 685 * we try to eliminate to calibrate the APIC.
kaf24@1452 686 */
kaf24@1452 687
kaf24@1452 688 int __init calibrate_APIC_clock(void)
kaf24@1452 689 {
kaf24@1452 690 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 691 long tt1, tt2;
kaf24@1452 692 long result;
kaf24@1452 693 int i;
kaf24@1452 694 const int LOOPS = HZ/10;
kaf24@1452 695
kaf24@1452 696 printk("Calibrating APIC timer for CPU%d...\n", smp_processor_id());
kaf24@1452 697
iap10@4548 698 /*
iap10@4548 699 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 700 * value into the APIC clock, we just want to get the
iap10@4548 701 * counter running for calibration.
iap10@4548 702 */
kaf24@1452 703 __setup_APIC_LVTT(1000000000);
kaf24@1452 704
iap10@4548 705 /*
iap10@4548 706 * The timer chip counts down to zero. Let's wait
kaf24@1452 707 * for a wraparound to start exact measurement:
iap10@4548 708 * (the current tick might have been already half done)
iap10@4548 709 */
iap10@4548 710 wait_timer_tick();
iap10@4548 711
iap10@4548 712 /*
iap10@4548 713 * We wrapped around just now. Let's start:
iap10@4548 714 */
iap10@4548 715 if (cpu_has_tsc)
kaf24@4619 716 rdtscll(t1);
kaf24@1452 717 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 718
iap10@4548 719 /*
iap10@4548 720 * Let's wait LOOPS wraprounds:
iap10@4548 721 */
kaf24@1452 722 for (i = 0; i < LOOPS; i++)
iap10@4548 723 wait_timer_tick();
kaf24@1452 724
kaf24@1452 725 tt2 = apic_read(APIC_TMCCT);
iap10@4548 726 if (cpu_has_tsc)
kaf24@4619 727 rdtscll(t2);
kaf24@1452 728
iap10@4548 729 /*
iap10@4548 730 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 731 * might have overflown, but note that we use signed
kaf24@1452 732 * longs, thus no extra care needed.
kaf24@4619 733 * [underflown to be exact, as the timer counts down ;)]
iap10@4548 734 */
iap10@4548 735
kaf24@1452 736 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 737
iap10@4548 738 if (cpu_has_tsc)
iap10@4548 739 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
iap10@4548 740 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
iap10@4548 741 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 742
iap10@4548 743 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
iap10@4548 744 result/(1000000/HZ),
iap10@4548 745 result%(1000000/HZ));
kaf24@1452 746
kaf24@1452 747 /* set up multipliers for accurate timer code */
kaf24@1452 748 bus_freq = result*HZ;
kaf24@1452 749 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 750 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 751
kaf24@1452 752 printk("..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 753 /* reset APIC to zero timeout value */
kaf24@1452 754 __setup_APIC_LVTT(0);
iap10@4548 755
kaf24@1452 756 return result;
kaf24@1452 757 }
kaf24@1452 758
kaf24@1452 759 /*
kaf24@1452 760 * initialise the APIC timers for all CPUs
kaf24@1452 761 * we start with the first and find out processor frequency and bus speed
kaf24@1452 762 */
kaf24@1452 763 void __init setup_APIC_clocks (void)
kaf24@1452 764 {
kaf24@1452 765 printk("Using local APIC timer interrupts.\n");
kaf24@1452 766 using_apic_timer = 1;
kaf24@1452 767 __cli();
kaf24@1452 768 /* calibrate CPU0 for CPU speed and BUS speed */
kaf24@1452 769 bus_freq = calibrate_APIC_clock();
kaf24@1452 770 /* Now set up the timer for real. */
kaf24@1452 771 setup_APIC_timer((void *)bus_freq);
kaf24@1452 772 __sti();
kaf24@1452 773 /* and update all other cpus */
kaf24@1452 774 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
kaf24@1452 775 }
kaf24@1452 776
kaf24@1452 777 #undef APIC_DIVISOR
kaf24@1452 778
kaf24@1452 779 /*
kaf24@1452 780 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 781 * returns 1 on success
kaf24@1452 782 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 783 */
kaf24@1452 784 int reprogram_ac_timer(s_time_t timeout)
kaf24@1452 785 {
kaf24@1452 786 s_time_t now;
kaf24@1452 787 s_time_t expire;
kaf24@1452 788 u64 apic_tmict;
kaf24@1452 789
kaf24@1452 790 /*
kaf24@1452 791 * We use this value because we don't trust zero (we think it may just
kaf24@1452 792 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 793 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 794 */
kaf24@1452 795 if ( timeout == 0 )
kaf24@1452 796 {
kaf24@1452 797 apic_tmict = 0xffffffff;
kaf24@1452 798 goto reprogram;
kaf24@1452 799 }
kaf24@1452 800
kaf24@1452 801 now = NOW();
kaf24@1452 802 expire = timeout - now; /* value from now */
kaf24@1452 803
kaf24@1452 804 if ( expire <= 0 )
kaf24@1452 805 {
kaf24@1452 806 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 807 smp_processor_id(), (u32)(now>>32),
kaf24@1452 808 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 809 return 0;
kaf24@1452 810 }
kaf24@1452 811
kaf24@1452 812 /*
kaf24@1452 813 * If we don't have local APIC then we just poll the timer list off the
kaf24@1452 814 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
kaf24@1452 815 */
kaf24@1452 816 if ( !cpu_has_apic )
kaf24@1452 817 return 1;
kaf24@1452 818
kaf24@1452 819 /* conversion to bus units */
kaf24@1452 820 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 821
kaf24@1452 822 if ( apic_tmict >= 0xffffffff )
kaf24@1452 823 {
kaf24@1452 824 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 825 apic_tmict = 0xffffffff;
kaf24@1452 826 }
kaf24@1452 827
kaf24@1452 828 if ( apic_tmict == 0 )
kaf24@1452 829 {
kaf24@1452 830 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 831 return 0;
kaf24@1452 832 }
kaf24@1452 833
kaf24@1452 834 reprogram:
kaf24@1452 835 /* Program the timer. */
kaf24@1452 836 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 837
kaf24@1452 838 return 1;
kaf24@1452 839 }
kaf24@1452 840
kaf24@4683 841 void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 842 {
kaf24@1452 843 ack_APIC_irq();
kaf24@1452 844 perfc_incrc(apic_timer);
kaf24@1506 845 raise_softirq(AC_TIMER_SOFTIRQ);
kaf24@1452 846 }
kaf24@1452 847
kaf24@1452 848 /*
kaf24@1452 849 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 850 */
kaf24@4683 851 asmlinkage void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 852 {
kaf24@1452 853 unsigned long v;
kaf24@1452 854
kaf24@1452 855 /*
kaf24@1452 856 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 857 * if it is a vectored one. Just in case...
kaf24@1452 858 * Spurious interrupts should not be ACKed.
kaf24@1452 859 */
kaf24@1452 860 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 861 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 862 ack_APIC_irq();
kaf24@1452 863
kaf24@1452 864 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@1452 865 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 866 smp_processor_id());
kaf24@1452 867 }
kaf24@1452 868
kaf24@1452 869 /*
kaf24@1452 870 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 871 */
kaf24@1452 872
kaf24@4683 873 asmlinkage void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 874 {
kaf24@1452 875 unsigned long v, v1;
kaf24@1452 876
kaf24@1452 877 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 878 v = apic_read(APIC_ESR);
kaf24@1452 879 apic_write(APIC_ESR, 0);
kaf24@1452 880 v1 = apic_read(APIC_ESR);
kaf24@1452 881 ack_APIC_irq();
kaf24@1452 882 atomic_inc(&irq_err_count);
kaf24@1452 883
kaf24@1452 884 /* Here is what the APIC error bits mean:
kaf24@1452 885 0: Send CS error
kaf24@1452 886 1: Receive CS error
kaf24@1452 887 2: Send accept error
kaf24@1452 888 3: Receive accept error
kaf24@1452 889 4: Reserved
kaf24@1452 890 5: Send illegal vector
kaf24@1452 891 6: Received illegal vector
kaf24@1452 892 7: Illegal register address
kaf24@1452 893 */
kaf24@4619 894 printk("APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@4619 895 smp_processor_id(), v, v1);
kaf24@1452 896 }
kaf24@1452 897
kaf24@1452 898 /*
kaf24@1452 899 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 900 * a UP kernel.
kaf24@1452 901 */
kaf24@1452 902 int __init APIC_init_uniprocessor (void)
kaf24@1452 903 {
kaf24@1452 904 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 905 return -1;
kaf24@1452 906
kaf24@1452 907 /*
kaf24@1452 908 * Complain if the BIOS pretends there is one.
kaf24@1452 909 */
iap10@4548 910 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@1452 911 printk("BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 912 boot_cpu_physical_apicid);
kaf24@1452 913 return -1;
kaf24@1452 914 }
kaf24@1452 915
kaf24@1452 916 verify_local_APIC();
kaf24@1452 917
kaf24@1452 918 connect_bsp_APIC();
kaf24@1452 919
kaf24@1452 920 #ifdef CONFIG_SMP
kaf24@1452 921 cpu_online_map = 1;
kaf24@1452 922 #endif
kaf24@4804 923 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 924 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
kaf24@1452 925
kaf24@1452 926 setup_local_APIC();
kaf24@1452 927
kaf24@1452 928 #ifdef CONFIG_X86_IO_APIC
iap10@4548 929 if (smp_found_config)
iap10@4548 930 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 931 setup_IO_APIC();
iap10@4548 932 #endif
kaf24@1452 933 setup_APIC_clocks();
kaf24@1452 934
kaf24@1452 935 return 0;
kaf24@1452 936 }