ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 4888:2bc4d7e40d11

bitkeeper revision 1.1389.1.52 (42839937dfdfndUpTNENRU4pLS6XDw)

Add 'apic={verbose,debug}' option to Xen. Same meaning as on Linux
command line, and automatically propagated to domain0 command line.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu May 12 17:58:15 2005 +0000 (2005-05-12)
parents 487de0451d2b
children bb2558cbc4f8
rev   line source
kaf24@1452 1 /*
kaf24@4888 2 * based on linux-2.6.11/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kaf24@1452 13 * Maciej W. Rozycki : Various updates and fixes.
kaf24@1452 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@4888 41 * Debug level
kaf24@4888 42 */
kaf24@4888 43 int apic_verbosity;
kaf24@4888 44
kaf24@1452 45 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 46 int using_apic_timer = 0;
kaf24@1452 47
kaf24@1452 48 static int enabled_via_apicbase;
kaf24@1452 49
kaf24@4804 50 int get_physical_broadcast(void)
kaf24@4804 51 {
kaf24@4804 52 unsigned int lvr, version;
kaf24@4804 53 lvr = apic_read(APIC_LVR);
kaf24@4804 54 version = GET_APIC_VERSION(lvr);
kaf24@4804 55 if (!APIC_INTEGRATED(version) || version >= 0x14)
kaf24@4804 56 return 0xff;
kaf24@4804 57 else
kaf24@4804 58 return 0xf;
kaf24@4804 59 }
kaf24@4804 60
kaf24@1452 61 int get_maxlvt(void)
kaf24@1452 62 {
kaf24@1452 63 unsigned int v, ver, maxlvt;
kaf24@1452 64
kaf24@1452 65 v = apic_read(APIC_LVR);
kaf24@1452 66 ver = GET_APIC_VERSION(v);
kaf24@1452 67 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 68 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 69 return maxlvt;
kaf24@1452 70 }
kaf24@1452 71
kaf24@1452 72 void clear_local_APIC(void)
kaf24@1452 73 {
kaf24@1452 74 int maxlvt;
kaf24@1452 75 unsigned long v;
kaf24@1452 76
kaf24@1452 77 maxlvt = get_maxlvt();
kaf24@1452 78
kaf24@1452 79 /*
kaf24@1452 80 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 81 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 82 */
kaf24@1452 83 if (maxlvt >= 3) {
kaf24@1452 84 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 85 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 86 }
kaf24@1452 87 /*
kaf24@1452 88 * Careful: we have to set masks only first to deassert
kaf24@1452 89 * any level-triggered sources.
kaf24@1452 90 */
kaf24@1452 91 v = apic_read(APIC_LVTT);
kaf24@1452 92 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 93 v = apic_read(APIC_LVT0);
kaf24@1452 94 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 95 v = apic_read(APIC_LVT1);
kaf24@1452 96 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 97 if (maxlvt >= 4) {
kaf24@1452 98 v = apic_read(APIC_LVTPC);
kaf24@1452 99 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 100 }
kaf24@1452 101
kaf24@1452 102 /*
kaf24@1452 103 * Clean APIC state for other OSs:
kaf24@1452 104 */
kaf24@1452 105 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 106 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 107 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 108 if (maxlvt >= 3)
kaf24@1452 109 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 110 if (maxlvt >= 4)
kaf24@1452 111 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 112
kaf24@1452 113 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@1452 114 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 115 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 116 apic_write(APIC_ESR, 0);
kaf24@1452 117 apic_read(APIC_ESR);
kaf24@1452 118 }
kaf24@1452 119 }
kaf24@1452 120
kaf24@1452 121 void __init connect_bsp_APIC(void)
kaf24@1452 122 {
kaf24@1452 123 if (pic_mode) {
kaf24@1452 124 /*
kaf24@1452 125 * Do not trust the local APIC being empty at bootup.
kaf24@1452 126 */
kaf24@1452 127 clear_local_APIC();
kaf24@1452 128 /*
kaf24@1452 129 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 130 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 131 */
kaf24@4888 132 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 133 "enabling APIC mode.\n");
kaf24@1452 134 outb(0x70, 0x22);
kaf24@1452 135 outb(0x01, 0x23);
kaf24@1452 136 }
kaf24@1452 137 }
kaf24@1452 138
kaf24@1452 139 void disconnect_bsp_APIC(void)
kaf24@1452 140 {
kaf24@1452 141 if (pic_mode) {
kaf24@1452 142 /*
kaf24@1452 143 * Put the board back into PIC mode (has an effect
kaf24@1452 144 * only on certain older boards). Note that APIC
kaf24@1452 145 * interrupts, including IPIs, won't work beyond
kaf24@1452 146 * this point! The only exception are INIT IPIs.
kaf24@1452 147 */
kaf24@4888 148 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 149 "entering PIC mode.\n");
kaf24@1452 150 outb(0x70, 0x22);
kaf24@1452 151 outb(0x00, 0x23);
kaf24@1452 152 }
kaf24@1452 153 }
kaf24@1452 154
kaf24@1452 155 void disable_local_APIC(void)
kaf24@1452 156 {
kaf24@1452 157 unsigned long value;
kaf24@1452 158
kaf24@1452 159 clear_local_APIC();
kaf24@1452 160
kaf24@1452 161 /*
kaf24@1452 162 * Disable APIC (implies clearing of registers
kaf24@1452 163 * for 82489DX!).
kaf24@1452 164 */
kaf24@1452 165 value = apic_read(APIC_SPIV);
kaf24@1452 166 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 167 apic_write_around(APIC_SPIV, value);
kaf24@1452 168
kaf24@1452 169 if (enabled_via_apicbase) {
kaf24@1452 170 unsigned int l, h;
kaf24@1452 171 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 172 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 173 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 174 }
kaf24@1452 175 }
kaf24@1452 176
kaf24@1452 177 /*
kaf24@1452 178 * This is to verify that we're looking at a real local APIC.
kaf24@1452 179 * Check these against your board if the CPUs aren't getting
kaf24@1452 180 * started for no apparent reason.
kaf24@1452 181 */
kaf24@1452 182 int __init verify_local_APIC(void)
kaf24@1452 183 {
kaf24@1452 184 unsigned int reg0, reg1;
kaf24@1452 185
kaf24@1452 186 /*
kaf24@1452 187 * The version register is read-only in a real APIC.
kaf24@1452 188 */
kaf24@1452 189 reg0 = apic_read(APIC_LVR);
kaf24@4888 190 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
kaf24@1452 191 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 192 reg1 = apic_read(APIC_LVR);
kaf24@4888 193 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 194
kaf24@1452 195 /*
kaf24@1452 196 * The two version reads above should print the same
kaf24@1452 197 * numbers. If the second one is different, then we
kaf24@1452 198 * poke at a non-APIC.
kaf24@1452 199 */
kaf24@1452 200 if (reg1 != reg0)
kaf24@1452 201 return 0;
kaf24@1452 202
kaf24@1452 203 /*
kaf24@1452 204 * Check if the version looks reasonably.
kaf24@1452 205 */
kaf24@1452 206 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 207 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 208 return 0;
kaf24@1452 209 reg1 = get_maxlvt();
kaf24@1452 210 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 211 return 0;
kaf24@1452 212
kaf24@1452 213 /*
kaf24@1452 214 * The ID register is read/write in a real APIC.
kaf24@1452 215 */
kaf24@1452 216 reg0 = apic_read(APIC_ID);
kaf24@4888 217 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 218
kaf24@1452 219 /*
kaf24@1452 220 * The next two are just to see if we have sane values.
kaf24@1452 221 * They're only really relevant if we're in Virtual Wire
kaf24@1452 222 * compatibility mode, but most boxes are anymore.
kaf24@1452 223 */
kaf24@1452 224 reg0 = apic_read(APIC_LVT0);
kaf24@4888 225 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 226 reg1 = apic_read(APIC_LVT1);
kaf24@4888 227 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 228
kaf24@1452 229 return 1;
kaf24@1452 230 }
kaf24@1452 231
kaf24@1452 232 void __init sync_Arb_IDs(void)
kaf24@1452 233 {
iap10@4548 234 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
iap10@4548 235 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
iap10@4548 236 if (ver >= 0x14) /* P4 or higher */
iap10@4548 237 return;
kaf24@1452 238 /*
kaf24@1452 239 * Wait for idle.
kaf24@1452 240 */
kaf24@1452 241 apic_wait_icr_idle();
kaf24@1452 242
kaf24@4888 243 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 244 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 245 | APIC_DM_INIT);
kaf24@1452 246 }
kaf24@1452 247
kaf24@1452 248 extern void __error_in_apic_c (void);
kaf24@1452 249
kaf24@4888 250 /*
kaf24@4888 251 * An initial setup of the virtual wire mode.
kaf24@4888 252 */
kaf24@1452 253 void __init init_bsp_APIC(void)
kaf24@1452 254 {
kaf24@4620 255 unsigned long value, ver;
kaf24@4620 256
kaf24@4620 257 /*
kaf24@4888 258 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 259 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 260 */
kaf24@4620 261 if (smp_found_config || !cpu_has_apic)
kaf24@4620 262 return;
kaf24@4620 263
kaf24@4620 264 value = apic_read(APIC_LVR);
kaf24@4620 265 ver = GET_APIC_VERSION(value);
kaf24@4620 266
kaf24@4620 267 /*
kaf24@4620 268 * Do not trust the local APIC being empty at bootup.
kaf24@4620 269 */
kaf24@4620 270 clear_local_APIC();
kaf24@4620 271
kaf24@4620 272 /*
kaf24@4620 273 * Enable APIC.
kaf24@4620 274 */
kaf24@4620 275 value = apic_read(APIC_SPIV);
kaf24@4620 276 value &= ~APIC_VECTOR_MASK;
kaf24@4620 277 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 278
kaf24@4620 279 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 280 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 281 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 282 else
kaf24@4620 283 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 284 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 285 apic_write_around(APIC_SPIV, value);
kaf24@4620 286
kaf24@4620 287 /*
kaf24@4620 288 * Set up the virtual wire mode.
kaf24@4620 289 */
kaf24@4620 290 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 291 value = APIC_DM_NMI;
kaf24@4620 292 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 293 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 294 apic_write_around(APIC_LVT1, value);
kaf24@1452 295 }
kaf24@1452 296
kaf24@1452 297 void __init setup_local_APIC (void)
kaf24@1452 298 {
iap10@4548 299 unsigned long oldvalue, value, ver, maxlvt;
iap10@4548 300
iap10@4548 301 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 302 if (esr_disable) {
iap10@4548 303 apic_write(APIC_ESR, 0);
iap10@4548 304 apic_write(APIC_ESR, 0);
iap10@4548 305 apic_write(APIC_ESR, 0);
iap10@4548 306 apic_write(APIC_ESR, 0);
iap10@4548 307 }
kaf24@1452 308
kaf24@1452 309 value = apic_read(APIC_LVR);
kaf24@1452 310 ver = GET_APIC_VERSION(value);
kaf24@1452 311
kaf24@1452 312 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 313 __error_in_apic_c();
kaf24@1452 314
iap10@4548 315 /*
iap10@4548 316 * Double-check whether this APIC is really registered.
iap10@4548 317 */
iap10@4548 318 if (!apic_id_registered())
kaf24@1452 319 BUG();
kaf24@1452 320
kaf24@1452 321 /*
kaf24@1452 322 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 323 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 324 * document number 292116). So here it goes...
kaf24@1452 325 */
iap10@4548 326 init_apic_ldr();
kaf24@1452 327
kaf24@1452 328 /*
kaf24@1452 329 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 330 * later on.
kaf24@1452 331 */
kaf24@1452 332 value = apic_read(APIC_TASKPRI);
kaf24@1452 333 value &= ~APIC_TPRI_MASK;
kaf24@1452 334 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 335
kaf24@1452 336 /*
kaf24@1452 337 * Now that we are all set up, enable the APIC
kaf24@1452 338 */
kaf24@1452 339 value = apic_read(APIC_SPIV);
kaf24@1452 340 value &= ~APIC_VECTOR_MASK;
kaf24@1452 341 /*
kaf24@1452 342 * Enable APIC
kaf24@1452 343 */
kaf24@1452 344 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 345
iap10@4548 346 /*
iap10@4548 347 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 348 * certain networking cards. If high frequency interrupts are
iap10@4548 349 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 350 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 351 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 352 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 353 * away, oh well :-(
iap10@4548 354 *
iap10@4548 355 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 356 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 357 * BX chipset. ]
iap10@4548 358 */
iap10@4548 359 /*
iap10@4548 360 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 361 * frequent as it makes the interrupt distributon model be more
iap10@4548 362 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 363 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 364 */
iap10@4548 365 #if 1
kaf24@1452 366 /* Enable focus processor (bit==0) */
kaf24@1452 367 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 368 #else
iap10@4548 369 /* Disable focus processor (bit==1) */
iap10@4548 370 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 371 #endif
iap10@4548 372 /*
iap10@4548 373 * Set spurious IRQ vector
iap10@4548 374 */
kaf24@1452 375 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 376 apic_write_around(APIC_SPIV, value);
kaf24@1452 377
kaf24@1452 378 /*
kaf24@1452 379 * Set up LVT0, LVT1:
kaf24@1452 380 *
kaf24@1452 381 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 382 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 383 * we delegate interrupts to the 8259A.
kaf24@1452 384 */
kaf24@1452 385 /*
kaf24@1452 386 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 387 */
kaf24@1452 388 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 389 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 390 value = APIC_DM_EXTINT;
kaf24@4888 391 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 392 smp_processor_id());
kaf24@1452 393 } else {
kaf24@1452 394 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 395 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 396 smp_processor_id());
kaf24@1452 397 }
kaf24@1452 398 apic_write_around(APIC_LVT0, value);
kaf24@1452 399
kaf24@1452 400 /*
kaf24@1452 401 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 402 */
kaf24@1452 403 if (!smp_processor_id())
kaf24@1452 404 value = APIC_DM_NMI;
kaf24@1452 405 else
kaf24@1452 406 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 407 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 408 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 409 apic_write_around(APIC_LVT1, value);
kaf24@1452 410
iap10@4548 411 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 412 maxlvt = get_maxlvt();
kaf24@1452 413 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 414 apic_write(APIC_ESR, 0);
iap10@4548 415 oldvalue = apic_read(APIC_ESR);
kaf24@1452 416
iap10@4548 417 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 418 apic_write_around(APIC_LVTERR, value);
iap10@4548 419 /*
iap10@4548 420 * spec says clear errors after enabling vector.
iap10@4548 421 */
kaf24@1452 422 if (maxlvt > 3)
kaf24@1452 423 apic_write(APIC_ESR, 0);
kaf24@1452 424 value = apic_read(APIC_ESR);
iap10@4548 425 if (value != oldvalue)
kaf24@4888 426 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 427 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 428 oldvalue, value);
kaf24@1452 429 } else {
iap10@4548 430 if (esr_disable)
iap10@4548 431 /*
iap10@4548 432 * Something untraceble is creating bad interrupts on
iap10@4548 433 * secondary quads ... for the moment, just leave the
iap10@4548 434 * ESR disabled - we can't do anything useful with the
iap10@4548 435 * errors anyway - mbligh
iap10@4548 436 */
iap10@4548 437 printk("Leaving ESR disabled.\n");
kaf24@4888 438 else
kaf24@4888 439 printk("No ESR for 82489DX.\n");
kaf24@1452 440 }
kaf24@1452 441
iap10@4548 442 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@1452 443 setup_apic_nmi_watchdog();
kaf24@1452 444 }
kaf24@1452 445
kaf24@1452 446 /*
kaf24@1452 447 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 448 * Original code written by Keir Fraser.
kaf24@1452 449 */
kaf24@1452 450
kaf24@4888 451 static void __init apic_set_verbosity(char *str)
kaf24@4888 452 {
kaf24@4888 453 if (strcmp("debug", str) == 0)
kaf24@4888 454 apic_verbosity = APIC_DEBUG;
kaf24@4888 455 else if (strcmp("verbose", str) == 0)
kaf24@4888 456 apic_verbosity = APIC_VERBOSE;
kaf24@4888 457 else
kaf24@4888 458 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@4888 459 " use apic=verbose or apic=debug", str);
kaf24@4888 460 }
kaf24@4888 461 custom_param("apic", apic_set_verbosity);
kaf24@4888 462
kaf24@1452 463 static int __init detect_init_APIC (void)
kaf24@1452 464 {
kaf24@1452 465 u32 h, l, features;
kaf24@1452 466 extern void get_cpu_vendor(struct cpuinfo_x86*);
kaf24@1452 467
kaf24@1452 468 /* Workaround for us being called before identify_cpu(). */
kaf24@1452 469 get_cpu_vendor(&boot_cpu_data);
kaf24@1452 470
kaf24@1452 471 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 472 case X86_VENDOR_AMD:
iap10@4548 473 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 474 (boot_cpu_data.x86 == 15))
kaf24@1452 475 break;
kaf24@1452 476 goto no_apic;
kaf24@1452 477 case X86_VENDOR_INTEL:
iap10@4548 478 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 479 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 480 break;
kaf24@1452 481 goto no_apic;
kaf24@1452 482 default:
kaf24@1452 483 goto no_apic;
kaf24@1452 484 }
kaf24@1452 485
kaf24@1452 486 if (!cpu_has_apic) {
kaf24@1452 487 /*
kaf24@1452 488 * Some BIOSes disable the local APIC in the
kaf24@1452 489 * APIC_BASE MSR. This can only be done in
iap10@4548 490 * software for Intel P6 or later and AMD K7
iap10@4548 491 * (Model > 1) or later.
kaf24@1452 492 */
kaf24@1452 493 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 494 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 495 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 496 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 497 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 498 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 499 enabled_via_apicbase = 1;
kaf24@1452 500 }
kaf24@1452 501 }
kaf24@4888 502 /*
kaf24@4888 503 * The APIC feature bit should now be enabled
kaf24@4888 504 * in `cpuid'
kaf24@4888 505 */
kaf24@1452 506 features = cpuid_edx(1);
kaf24@1452 507 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 508 printk("Could not enable APIC!\n");
kaf24@1452 509 return -1;
kaf24@1452 510 }
kaf24@4619 511
iap10@4548 512 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 513 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 514
kaf24@1452 515 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 516 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 517 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 518 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 519
kaf24@4619 520 if (nmi_watchdog != NMI_NONE)
kaf24@4619 521 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 522
kaf24@1452 523 printk("Found and enabled local APIC!\n");
iap10@4548 524
kaf24@1452 525 return 0;
kaf24@1452 526
iap10@4548 527 no_apic:
kaf24@1452 528 printk("No local APIC present or hardware disabled\n");
kaf24@1452 529 return -1;
kaf24@1452 530 }
kaf24@1452 531
kaf24@1452 532 void __init init_apic_mappings(void)
kaf24@1452 533 {
iap10@4548 534 unsigned long apic_phys;
kaf24@1452 535
kaf24@1452 536 /*
iap10@4548 537 * If no local APIC can be found then set up a fake all
iap10@4548 538 * zeroes page to simulate the local APIC and another
iap10@4548 539 * one for the IO-APIC.
kaf24@1452 540 */
kaf24@1452 541 if (!smp_found_config && detect_init_APIC()) {
kaf24@1920 542 apic_phys = alloc_xenheap_page();
kaf24@1452 543 apic_phys = __pa(apic_phys);
kaf24@1452 544 } else
kaf24@1452 545 apic_phys = mp_lapic_addr;
kaf24@1452 546
kaf24@1452 547 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 548 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 549 apic_phys);
kaf24@1452 550
kaf24@1452 551 /*
kaf24@1452 552 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 553 * default configuration (or the MP table is broken).
kaf24@1452 554 */
kaf24@1452 555 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 556 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 557
kaf24@1452 558 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 559 {
iap10@4548 560 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 561 int i;
kaf24@1452 562
kaf24@1452 563 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 564 if (smp_found_config) {
kaf24@1452 565 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 566 if (!ioapic_phys) {
iap10@4548 567 printk(KERN_ERR
iap10@4548 568 "WARNING: bogus zero IO-APIC "
iap10@4548 569 "address found in MPTABLE, "
iap10@4548 570 "disabling IO/APIC support!\n");
iap10@4548 571 smp_found_config = 0;
iap10@4548 572 skip_ioapic_setup = 1;
iap10@4548 573 goto fake_ioapic_page;
iap10@4548 574 }
iap10@4548 575 } else {
iap10@4548 576 fake_ioapic_page:
iap10@4548 577 ioapic_phys = alloc_xenheap_page();
iap10@4548 578 ioapic_phys = __pa(ioapic_phys);
iap10@4548 579 }
kaf24@1452 580 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 581 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 582 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 583 idx++;
kaf24@1452 584 }
kaf24@1452 585 }
kaf24@1452 586 #endif
kaf24@1452 587 }
kaf24@1452 588
kaf24@1452 589 /*****************************************************************************
kaf24@1452 590 * APIC calibration
kaf24@1452 591 *
kaf24@1452 592 * The APIC is programmed in bus cycles.
kaf24@1452 593 * Timeout values should specified in real time units.
kaf24@1452 594 * The "cheapest" time source is the cyclecounter.
kaf24@1452 595 *
kaf24@1452 596 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 597 *
kaf24@1452 598 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 599 * timer chip to generate periodic timer interupts.
kaf24@1452 600 *****************************************************************************/
kaf24@1452 601
kaf24@1452 602 /* used for system time scaling */
kaf24@1672 603 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 604 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 605 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 606
kaf24@1452 607 /*
kaf24@1452 608 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 609 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 610 * to calibrate.
kaf24@1452 611 */
kaf24@1452 612 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 613 {
kaf24@1452 614 /*extern spinlock_t i8253_lock;*/
kaf24@1452 615 /*unsigned long flags;*/
iap10@4548 616
kaf24@1452 617 unsigned int count;
iap10@4548 618
kaf24@1452 619 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 620
iap10@4548 621 outb_p(0x00, PIT_MODE);
iap10@4548 622 count = inb_p(PIT_CH0);
iap10@4548 623 count |= inb_p(PIT_CH0) << 8;
iap10@4548 624
kaf24@1452 625 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 626
kaf24@1452 627 return count;
kaf24@1452 628 }
kaf24@1452 629
iap10@4548 630 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 631 static void __init wait_8254_wraparound(void)
kaf24@1452 632 {
kaf24@4888 633 unsigned int curr_count, prev_count;
kaf24@4888 634
kaf24@1452 635 curr_count = get_8254_timer_count();
kaf24@1452 636 do {
kaf24@1452 637 prev_count = curr_count;
kaf24@1452 638 curr_count = get_8254_timer_count();
iap10@4548 639
kaf24@4888 640 /* workaround for broken Mercury/Neptune */
kaf24@4888 641 if (prev_count >= curr_count + 0x100)
kaf24@4888 642 curr_count = get_8254_timer_count();
kaf24@4888 643
kaf24@4888 644 } while (prev_count >= curr_count);
kaf24@1452 645 }
kaf24@1452 646
kaf24@1452 647 /*
iap10@4548 648 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 649 * we override this later
iap10@4548 650 */
kaf24@4888 651 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 652
iap10@4548 653 /*
kaf24@1452 654 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 655 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 656 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 657 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 658 * call this function only once, with the real, calibrated value.
kaf24@1452 659 *
kaf24@1452 660 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 661 * P5 APIC double write bug.
kaf24@1452 662 */
iap10@4548 663
kaf24@1452 664 #define APIC_DIVISOR 1
iap10@4548 665
kaf24@1452 666 static void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 667 {
iap10@4548 668 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 669
iap10@4548 670 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 671 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 672 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 673 if (!APIC_INTEGRATED(ver))
iap10@4548 674 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 675 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 676
kaf24@1452 677 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 678 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 679
kaf24@1452 680 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 681 }
kaf24@1452 682
kaf24@1452 683 /*
kaf24@1452 684 * this is done for every CPU from setup_APIC_clocks() below.
kaf24@1452 685 * We setup each local APIC with a zero timeout value for now.
kaf24@1452 686 * Unlike Linux, we don't have to wait for slices etc.
kaf24@1452 687 */
kaf24@1452 688 void setup_APIC_timer(void * data)
kaf24@1452 689 {
kaf24@1452 690 unsigned long flags;
kaf24@1452 691 __save_flags(flags);
kaf24@1452 692 __sti();
kaf24@1452 693 __setup_APIC_LVTT(0);
kaf24@1452 694 __restore_flags(flags);
kaf24@1452 695 }
kaf24@1452 696
kaf24@1452 697 /*
kaf24@1452 698 * In this function we calibrate APIC bus clocks to the external timer.
kaf24@1452 699 *
iap10@4548 700 * As a result we have the Bus Speed and CPU speed in Hz.
kaf24@1452 701 *
kaf24@1452 702 * We want to do the calibration only once (for CPU0). CPUs connected by the
kaf24@1452 703 * same APIC bus have the very same bus frequency.
kaf24@1452 704 *
kaf24@1452 705 * This bit is a bit shoddy since we use the very same periodic timer interrupt
kaf24@1452 706 * we try to eliminate to calibrate the APIC.
kaf24@1452 707 */
kaf24@1452 708
kaf24@1452 709 int __init calibrate_APIC_clock(void)
kaf24@1452 710 {
kaf24@1452 711 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 712 long tt1, tt2;
kaf24@1452 713 long result;
kaf24@1452 714 int i;
kaf24@1452 715 const int LOOPS = HZ/10;
kaf24@1452 716
kaf24@4888 717 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 718
iap10@4548 719 /*
iap10@4548 720 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 721 * value into the APIC clock, we just want to get the
iap10@4548 722 * counter running for calibration.
iap10@4548 723 */
kaf24@1452 724 __setup_APIC_LVTT(1000000000);
kaf24@1452 725
iap10@4548 726 /*
iap10@4548 727 * The timer chip counts down to zero. Let's wait
kaf24@1452 728 * for a wraparound to start exact measurement:
iap10@4548 729 * (the current tick might have been already half done)
iap10@4548 730 */
iap10@4548 731 wait_timer_tick();
iap10@4548 732
iap10@4548 733 /*
iap10@4548 734 * We wrapped around just now. Let's start:
iap10@4548 735 */
iap10@4548 736 if (cpu_has_tsc)
kaf24@4619 737 rdtscll(t1);
kaf24@1452 738 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 739
iap10@4548 740 /*
iap10@4548 741 * Let's wait LOOPS wraprounds:
iap10@4548 742 */
kaf24@1452 743 for (i = 0; i < LOOPS; i++)
iap10@4548 744 wait_timer_tick();
kaf24@1452 745
kaf24@1452 746 tt2 = apic_read(APIC_TMCCT);
iap10@4548 747 if (cpu_has_tsc)
kaf24@4619 748 rdtscll(t2);
kaf24@1452 749
iap10@4548 750 /*
iap10@4548 751 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 752 * might have overflown, but note that we use signed
kaf24@1452 753 * longs, thus no extra care needed.
kaf24@4888 754 *
kaf24@4888 755 * underflown to be exact, as the timer counts down ;)
iap10@4548 756 */
iap10@4548 757
kaf24@1452 758 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 759
iap10@4548 760 if (cpu_has_tsc)
kaf24@4888 761 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 762 "%ld.%04ld MHz.\n",
kaf24@4888 763 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 764 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 765
kaf24@4888 766 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kaf24@4888 767 "%ld.%04ld MHz.\n",
kaf24@4888 768 result/(1000000/HZ),
kaf24@4888 769 result%(1000000/HZ));
kaf24@1452 770
kaf24@1452 771 /* set up multipliers for accurate timer code */
kaf24@1452 772 bus_freq = result*HZ;
kaf24@1452 773 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 774 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 775
kaf24@4888 776 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 777 /* reset APIC to zero timeout value */
kaf24@1452 778 __setup_APIC_LVTT(0);
iap10@4548 779
kaf24@1452 780 return result;
kaf24@1452 781 }
kaf24@1452 782
kaf24@1452 783 /*
kaf24@1452 784 * initialise the APIC timers for all CPUs
kaf24@1452 785 * we start with the first and find out processor frequency and bus speed
kaf24@1452 786 */
kaf24@1452 787 void __init setup_APIC_clocks (void)
kaf24@1452 788 {
kaf24@1452 789 using_apic_timer = 1;
kaf24@1452 790 __cli();
kaf24@1452 791 /* calibrate CPU0 for CPU speed and BUS speed */
kaf24@1452 792 bus_freq = calibrate_APIC_clock();
kaf24@1452 793 /* Now set up the timer for real. */
kaf24@1452 794 setup_APIC_timer((void *)bus_freq);
kaf24@1452 795 __sti();
kaf24@1452 796 /* and update all other cpus */
kaf24@1452 797 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
kaf24@1452 798 }
kaf24@1452 799
kaf24@1452 800 #undef APIC_DIVISOR
kaf24@1452 801
kaf24@1452 802 /*
kaf24@1452 803 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 804 * returns 1 on success
kaf24@1452 805 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 806 */
kaf24@1452 807 int reprogram_ac_timer(s_time_t timeout)
kaf24@1452 808 {
kaf24@1452 809 s_time_t now;
kaf24@1452 810 s_time_t expire;
kaf24@1452 811 u64 apic_tmict;
kaf24@1452 812
kaf24@1452 813 /*
kaf24@1452 814 * We use this value because we don't trust zero (we think it may just
kaf24@1452 815 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 816 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 817 */
kaf24@1452 818 if ( timeout == 0 )
kaf24@1452 819 {
kaf24@1452 820 apic_tmict = 0xffffffff;
kaf24@1452 821 goto reprogram;
kaf24@1452 822 }
kaf24@1452 823
kaf24@1452 824 now = NOW();
kaf24@1452 825 expire = timeout - now; /* value from now */
kaf24@1452 826
kaf24@1452 827 if ( expire <= 0 )
kaf24@1452 828 {
kaf24@1452 829 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 830 smp_processor_id(), (u32)(now>>32),
kaf24@1452 831 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 832 return 0;
kaf24@1452 833 }
kaf24@1452 834
kaf24@1452 835 /*
kaf24@1452 836 * If we don't have local APIC then we just poll the timer list off the
kaf24@1452 837 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
kaf24@1452 838 */
kaf24@1452 839 if ( !cpu_has_apic )
kaf24@1452 840 return 1;
kaf24@1452 841
kaf24@1452 842 /* conversion to bus units */
kaf24@1452 843 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 844
kaf24@1452 845 if ( apic_tmict >= 0xffffffff )
kaf24@1452 846 {
kaf24@1452 847 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 848 apic_tmict = 0xffffffff;
kaf24@1452 849 }
kaf24@1452 850
kaf24@1452 851 if ( apic_tmict == 0 )
kaf24@1452 852 {
kaf24@1452 853 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 854 return 0;
kaf24@1452 855 }
kaf24@1452 856
kaf24@1452 857 reprogram:
kaf24@1452 858 /* Program the timer. */
kaf24@1452 859 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 860
kaf24@1452 861 return 1;
kaf24@1452 862 }
kaf24@1452 863
kaf24@4683 864 void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 865 {
kaf24@1452 866 ack_APIC_irq();
kaf24@1452 867 perfc_incrc(apic_timer);
kaf24@1506 868 raise_softirq(AC_TIMER_SOFTIRQ);
kaf24@1452 869 }
kaf24@1452 870
kaf24@1452 871 /*
kaf24@1452 872 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 873 */
kaf24@4683 874 asmlinkage void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 875 {
kaf24@1452 876 unsigned long v;
kaf24@1452 877
kaf24@1452 878 /*
kaf24@1452 879 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 880 * if it is a vectored one. Just in case...
kaf24@1452 881 * Spurious interrupts should not be ACKed.
kaf24@1452 882 */
kaf24@1452 883 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 884 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 885 ack_APIC_irq();
kaf24@1452 886
kaf24@1452 887 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@1452 888 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 889 smp_processor_id());
kaf24@1452 890 }
kaf24@1452 891
kaf24@1452 892 /*
kaf24@1452 893 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 894 */
kaf24@1452 895
kaf24@4683 896 asmlinkage void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 897 {
kaf24@1452 898 unsigned long v, v1;
kaf24@1452 899
kaf24@1452 900 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 901 v = apic_read(APIC_ESR);
kaf24@1452 902 apic_write(APIC_ESR, 0);
kaf24@1452 903 v1 = apic_read(APIC_ESR);
kaf24@1452 904 ack_APIC_irq();
kaf24@1452 905 atomic_inc(&irq_err_count);
kaf24@1452 906
kaf24@1452 907 /* Here is what the APIC error bits mean:
kaf24@1452 908 0: Send CS error
kaf24@1452 909 1: Receive CS error
kaf24@1452 910 2: Send accept error
kaf24@1452 911 3: Receive accept error
kaf24@1452 912 4: Reserved
kaf24@1452 913 5: Send illegal vector
kaf24@1452 914 6: Received illegal vector
kaf24@1452 915 7: Illegal register address
kaf24@1452 916 */
kaf24@4619 917 printk("APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@4619 918 smp_processor_id(), v, v1);
kaf24@1452 919 }
kaf24@1452 920
kaf24@1452 921 /*
kaf24@1452 922 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 923 * a UP kernel.
kaf24@1452 924 */
kaf24@1452 925 int __init APIC_init_uniprocessor (void)
kaf24@1452 926 {
kaf24@1452 927 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 928 return -1;
kaf24@1452 929
kaf24@1452 930 /*
kaf24@1452 931 * Complain if the BIOS pretends there is one.
kaf24@1452 932 */
iap10@4548 933 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 934 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 935 boot_cpu_physical_apicid);
kaf24@1452 936 return -1;
kaf24@1452 937 }
kaf24@1452 938
kaf24@1452 939 verify_local_APIC();
kaf24@1452 940
kaf24@1452 941 connect_bsp_APIC();
kaf24@1452 942
kaf24@1452 943 #ifdef CONFIG_SMP
kaf24@1452 944 cpu_online_map = 1;
kaf24@1452 945 #endif
kaf24@4804 946 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 947 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
kaf24@1452 948
kaf24@1452 949 setup_local_APIC();
kaf24@1452 950
kaf24@1452 951 #ifdef CONFIG_X86_IO_APIC
iap10@4548 952 if (smp_found_config)
iap10@4548 953 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 954 setup_IO_APIC();
iap10@4548 955 #endif
kaf24@1452 956 setup_APIC_clocks();
kaf24@1452 957
kaf24@1452 958 return 0;
kaf24@1452 959 }