ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 14340:215b799fa181

xen: New vcpu_op commands for setting periodic and single-shot timers.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Fri Mar 09 18:26:47 2007 +0000 (2007-03-09)
parents f07cf18343f1
children ea0b50ca4999
rev   line source
kaf24@1452 1 /*
kfraser@11541 2 * based on linux-2.6.17.13/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kfraser@11204 13 * Maciej W. Rozycki : Various updates and fixes.
kfraser@11204 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@8847 41 * Knob to control our willingness to enable the local APIC.
kaf24@8847 42 */
kaf24@8847 43 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
kaf24@8847 44
kaf24@8847 45 /*
kaf24@4888 46 * Debug level
kaf24@4888 47 */
kaf24@4888 48 int apic_verbosity;
kaf24@4888 49
kaf24@8847 50
kaf24@8847 51 static void apic_pm_activate(void);
kaf24@8847 52
kfraser@11541 53 int modern_apic(void)
kfraser@11541 54 {
kfraser@11541 55 unsigned int lvr, version;
kfraser@11541 56 /* AMD systems use old APIC versions, so check the CPU */
kfraser@11541 57 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
kfraser@11541 58 boot_cpu_data.x86 >= 0xf)
kfraser@11541 59 return 1;
kfraser@11541 60 lvr = apic_read(APIC_LVR);
kfraser@11541 61 version = GET_APIC_VERSION(lvr);
kfraser@11541 62 return version >= 0x14;
kfraser@11541 63 }
kfraser@11541 64
kaf24@8847 65 /*
kaf24@8847 66 * 'what should we do if we get a hw irq event on an illegal vector'.
kaf24@8847 67 * each architecture has to answer this themselves.
kaf24@8847 68 */
kaf24@8847 69 void ack_bad_irq(unsigned int irq)
kaf24@8847 70 {
kaf24@8847 71 printk("unexpected IRQ trap at vector %02x\n", irq);
kaf24@8847 72 /*
kaf24@8847 73 * Currently unexpected vectors happen only on SMP and APIC.
kaf24@8847 74 * We _must_ ack these because every local APIC has only N
kaf24@8847 75 * irq slots per priority level, and a 'hanging, unacked' IRQ
kaf24@8847 76 * holds up an irq slot - in excessive cases (when multiple
kaf24@8847 77 * unexpected vectors occur) that might lock up the APIC
kaf24@8847 78 * completely.
kfraser@11541 79 * But only ack when the APIC is enabled -AK
kaf24@8847 80 */
kfraser@11541 81 if (cpu_has_apic)
kfraser@11541 82 ack_APIC_irq();
kaf24@8847 83 }
kaf24@8847 84
kaf24@8847 85 void __init apic_intr_init(void)
kaf24@8847 86 {
kaf24@8847 87 #ifdef CONFIG_SMP
kaf24@8847 88 smp_intr_init();
kaf24@8847 89 #endif
kaf24@8847 90 /* self generated IPI for local APIC timer */
kaf24@8847 91 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
kaf24@8847 92
kaf24@8847 93 /* IPI vectors for APIC spurious and error interrupts */
kaf24@8847 94 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
kaf24@8847 95 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
kaf24@8847 96
kaf24@8847 97 /* thermal monitor LVT interrupt */
kaf24@8847 98 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@8847 99 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
kaf24@8847 100 #endif
kaf24@8847 101 }
kaf24@8847 102
kaf24@1452 103 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 104 int using_apic_timer = 0;
kaf24@1452 105
kaf24@1452 106 static int enabled_via_apicbase;
kaf24@1452 107
kfraser@11541 108 void enable_NMI_through_LVT0 (void * dummy)
kfraser@11541 109 {
kfraser@11541 110 unsigned int v, ver;
kfraser@11541 111
kfraser@11541 112 ver = apic_read(APIC_LVR);
kfraser@11541 113 ver = GET_APIC_VERSION(ver);
kfraser@11541 114 v = APIC_DM_NMI; /* unmask and set to NMI */
kfraser@11541 115 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kfraser@11541 116 v |= APIC_LVT_LEVEL_TRIGGER;
kfraser@11541 117 apic_write_around(APIC_LVT0, v);
kfraser@11541 118 }
kfraser@11541 119
kaf24@4804 120 int get_physical_broadcast(void)
kaf24@4804 121 {
kfraser@11541 122 if (modern_apic())
kaf24@4804 123 return 0xff;
kaf24@4804 124 else
kaf24@4804 125 return 0xf;
kaf24@4804 126 }
kaf24@4804 127
kaf24@1452 128 int get_maxlvt(void)
kaf24@1452 129 {
kaf24@1452 130 unsigned int v, ver, maxlvt;
kaf24@1452 131
kaf24@1452 132 v = apic_read(APIC_LVR);
kaf24@1452 133 ver = GET_APIC_VERSION(v);
kaf24@1452 134 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 135 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 136 return maxlvt;
kaf24@1452 137 }
kaf24@1452 138
kaf24@1452 139 void clear_local_APIC(void)
kaf24@1452 140 {
kaf24@1452 141 int maxlvt;
kaf24@1452 142 unsigned long v;
kaf24@1452 143
kaf24@1452 144 maxlvt = get_maxlvt();
kaf24@1452 145
kaf24@1452 146 /*
kaf24@1452 147 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 148 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 149 */
kaf24@1452 150 if (maxlvt >= 3) {
kaf24@1452 151 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 152 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 153 }
kaf24@1452 154 /*
kaf24@1452 155 * Careful: we have to set masks only first to deassert
kaf24@1452 156 * any level-triggered sources.
kaf24@1452 157 */
kaf24@1452 158 v = apic_read(APIC_LVTT);
kaf24@1452 159 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 160 v = apic_read(APIC_LVT0);
kaf24@1452 161 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 162 v = apic_read(APIC_LVT1);
kaf24@1452 163 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 164 if (maxlvt >= 4) {
kaf24@1452 165 v = apic_read(APIC_LVTPC);
kaf24@1452 166 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 167 }
kaf24@1452 168
kaf24@5211 169 /* lets not touch this if we didn't frob it */
kaf24@5211 170 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 171 if (maxlvt >= 5) {
kaf24@5211 172 v = apic_read(APIC_LVTTHMR);
kaf24@5211 173 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
kaf24@5211 174 }
kaf24@5211 175 #endif
kaf24@1452 176 /*
kaf24@1452 177 * Clean APIC state for other OSs:
kaf24@1452 178 */
kaf24@1452 179 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 180 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 181 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 182 if (maxlvt >= 3)
kaf24@1452 183 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 184 if (maxlvt >= 4)
kaf24@1452 185 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 186
kaf24@5211 187 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 188 if (maxlvt >= 5)
kaf24@5211 189 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
kaf24@5211 190 #endif
kaf24@1452 191 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kfraser@11204 192 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 193 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 194 apic_write(APIC_ESR, 0);
kaf24@1452 195 apic_read(APIC_ESR);
kaf24@1452 196 }
kaf24@1452 197 }
kaf24@1452 198
kaf24@1452 199 void __init connect_bsp_APIC(void)
kaf24@1452 200 {
kaf24@1452 201 if (pic_mode) {
kaf24@1452 202 /*
kaf24@1452 203 * Do not trust the local APIC being empty at bootup.
kaf24@1452 204 */
kaf24@1452 205 clear_local_APIC();
kaf24@1452 206 /*
kaf24@1452 207 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 208 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 209 */
kaf24@4888 210 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 211 "enabling APIC mode.\n");
kaf24@1452 212 outb(0x70, 0x22);
kaf24@1452 213 outb(0x01, 0x23);
kaf24@1452 214 }
kaf24@5211 215 enable_apic_mode();
kaf24@1452 216 }
kaf24@1452 217
kaf24@8847 218 void disconnect_bsp_APIC(int virt_wire_setup)
kaf24@1452 219 {
kaf24@1452 220 if (pic_mode) {
kaf24@1452 221 /*
kaf24@1452 222 * Put the board back into PIC mode (has an effect
kaf24@1452 223 * only on certain older boards). Note that APIC
kaf24@1452 224 * interrupts, including IPIs, won't work beyond
kaf24@1452 225 * this point! The only exception are INIT IPIs.
kaf24@1452 226 */
kaf24@4888 227 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 228 "entering PIC mode.\n");
kaf24@1452 229 outb(0x70, 0x22);
kaf24@1452 230 outb(0x00, 0x23);
kaf24@1452 231 }
kaf24@8847 232 else {
kaf24@8847 233 /* Go back to Virtual Wire compatibility mode */
kaf24@8847 234 unsigned long value;
kaf24@8847 235
kaf24@8847 236 /* For the spurious interrupt use vector F, and enable it */
kaf24@8847 237 value = apic_read(APIC_SPIV);
kaf24@8847 238 value &= ~APIC_VECTOR_MASK;
kaf24@8847 239 value |= APIC_SPIV_APIC_ENABLED;
kaf24@8847 240 value |= 0xf;
kaf24@8847 241 apic_write_around(APIC_SPIV, value);
kaf24@8847 242
kaf24@8847 243 if (!virt_wire_setup) {
kaf24@8847 244 /* For LVT0 make it edge triggered, active high, external and enabled */
kaf24@8847 245 value = apic_read(APIC_LVT0);
kaf24@8847 246 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 247 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 248 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
kaf24@8847 249 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 250 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
kaf24@8847 251 apic_write_around(APIC_LVT0, value);
kaf24@8847 252 }
kaf24@8847 253 else {
kaf24@8847 254 /* Disable LVT0 */
kaf24@8847 255 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@8847 256 }
kaf24@8847 257
kaf24@8847 258 /* For LVT1 make it edge triggered, active high, nmi and enabled */
kaf24@8847 259 value = apic_read(APIC_LVT1);
kaf24@8847 260 value &= ~(
kaf24@8847 261 APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 262 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 263 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
kaf24@8847 264 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 265 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
kaf24@8847 266 apic_write_around(APIC_LVT1, value);
kaf24@8847 267 }
kaf24@1452 268 }
kaf24@1452 269
kaf24@1452 270 void disable_local_APIC(void)
kaf24@1452 271 {
kaf24@1452 272 unsigned long value;
kaf24@1452 273
kaf24@1452 274 clear_local_APIC();
kaf24@1452 275
kaf24@1452 276 /*
kaf24@1452 277 * Disable APIC (implies clearing of registers
kaf24@1452 278 * for 82489DX!).
kaf24@1452 279 */
kaf24@1452 280 value = apic_read(APIC_SPIV);
kaf24@1452 281 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 282 apic_write_around(APIC_SPIV, value);
kaf24@1452 283
kaf24@1452 284 if (enabled_via_apicbase) {
kaf24@1452 285 unsigned int l, h;
kaf24@1452 286 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 287 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 288 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 289 }
kaf24@1452 290 }
kaf24@1452 291
kaf24@1452 292 /*
kaf24@1452 293 * This is to verify that we're looking at a real local APIC.
kaf24@1452 294 * Check these against your board if the CPUs aren't getting
kaf24@1452 295 * started for no apparent reason.
kaf24@1452 296 */
kaf24@1452 297 int __init verify_local_APIC(void)
kaf24@1452 298 {
kaf24@1452 299 unsigned int reg0, reg1;
kaf24@1452 300
kaf24@1452 301 /*
kaf24@1452 302 * The version register is read-only in a real APIC.
kaf24@1452 303 */
kaf24@1452 304 reg0 = apic_read(APIC_LVR);
kaf24@4888 305 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
kaf24@1452 306 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 307 reg1 = apic_read(APIC_LVR);
kaf24@4888 308 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 309
kaf24@1452 310 /*
kaf24@1452 311 * The two version reads above should print the same
kaf24@1452 312 * numbers. If the second one is different, then we
kaf24@1452 313 * poke at a non-APIC.
kaf24@1452 314 */
kaf24@1452 315 if (reg1 != reg0)
kaf24@1452 316 return 0;
kaf24@1452 317
kaf24@1452 318 /*
kaf24@1452 319 * Check if the version looks reasonably.
kaf24@1452 320 */
kaf24@1452 321 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 322 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 323 return 0;
kaf24@1452 324 reg1 = get_maxlvt();
kaf24@1452 325 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 326 return 0;
kaf24@1452 327
kaf24@1452 328 /*
kaf24@1452 329 * The ID register is read/write in a real APIC.
kaf24@1452 330 */
kaf24@1452 331 reg0 = apic_read(APIC_ID);
kaf24@4888 332 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 333
kaf24@1452 334 /*
kaf24@1452 335 * The next two are just to see if we have sane values.
kaf24@1452 336 * They're only really relevant if we're in Virtual Wire
kaf24@1452 337 * compatibility mode, but most boxes are anymore.
kaf24@1452 338 */
kaf24@1452 339 reg0 = apic_read(APIC_LVT0);
kaf24@4888 340 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 341 reg1 = apic_read(APIC_LVT1);
kaf24@4888 342 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 343
kaf24@1452 344 return 1;
kaf24@1452 345 }
kaf24@1452 346
kaf24@1452 347 void __init sync_Arb_IDs(void)
kaf24@1452 348 {
kfraser@11541 349 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
kfraser@11541 350 And not needed on AMD */
kfraser@11541 351 if (modern_apic())
iap10@4548 352 return;
kaf24@1452 353 /*
kaf24@1452 354 * Wait for idle.
kaf24@1452 355 */
kaf24@1452 356 apic_wait_icr_idle();
kaf24@1452 357
kaf24@4888 358 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 359 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 360 | APIC_DM_INIT);
kaf24@1452 361 }
kaf24@1452 362
kaf24@1452 363 extern void __error_in_apic_c (void);
kaf24@1452 364
kaf24@4888 365 /*
kaf24@4888 366 * An initial setup of the virtual wire mode.
kaf24@4888 367 */
kaf24@1452 368 void __init init_bsp_APIC(void)
kaf24@1452 369 {
kaf24@4620 370 unsigned long value, ver;
kaf24@4620 371
kaf24@4620 372 /*
kaf24@4888 373 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 374 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 375 */
kaf24@4620 376 if (smp_found_config || !cpu_has_apic)
kaf24@4620 377 return;
kaf24@4620 378
kaf24@4620 379 value = apic_read(APIC_LVR);
kaf24@4620 380 ver = GET_APIC_VERSION(value);
kaf24@4620 381
kaf24@4620 382 /*
kaf24@4620 383 * Do not trust the local APIC being empty at bootup.
kaf24@4620 384 */
kaf24@4620 385 clear_local_APIC();
kaf24@4620 386
kaf24@4620 387 /*
kaf24@4620 388 * Enable APIC.
kaf24@4620 389 */
kaf24@4620 390 value = apic_read(APIC_SPIV);
kaf24@4620 391 value &= ~APIC_VECTOR_MASK;
kaf24@4620 392 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 393
kaf24@4620 394 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 395 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 396 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 397 else
kaf24@4620 398 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 399 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 400 apic_write_around(APIC_SPIV, value);
kaf24@4620 401
kaf24@4620 402 /*
kaf24@4620 403 * Set up the virtual wire mode.
kaf24@4620 404 */
kaf24@4620 405 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 406 value = APIC_DM_NMI;
kaf24@4620 407 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 408 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 409 apic_write_around(APIC_LVT1, value);
kaf24@1452 410 }
kaf24@1452 411
kaf24@8847 412 void __devinit setup_local_APIC(void)
kaf24@1452 413 {
iap10@4548 414 unsigned long oldvalue, value, ver, maxlvt;
kfraser@11541 415 int i, j;
iap10@4548 416
iap10@4548 417 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 418 if (esr_disable) {
iap10@4548 419 apic_write(APIC_ESR, 0);
iap10@4548 420 apic_write(APIC_ESR, 0);
iap10@4548 421 apic_write(APIC_ESR, 0);
iap10@4548 422 apic_write(APIC_ESR, 0);
iap10@4548 423 }
kaf24@1452 424
kaf24@1452 425 value = apic_read(APIC_LVR);
kaf24@1452 426 ver = GET_APIC_VERSION(value);
kaf24@1452 427
kaf24@1452 428 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 429 __error_in_apic_c();
kaf24@1452 430
iap10@4548 431 /*
iap10@4548 432 * Double-check whether this APIC is really registered.
iap10@4548 433 */
iap10@4548 434 if (!apic_id_registered())
kaf24@1452 435 BUG();
kaf24@1452 436
kaf24@1452 437 /*
kaf24@1452 438 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 439 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 440 * document number 292116). So here it goes...
kaf24@1452 441 */
iap10@4548 442 init_apic_ldr();
kaf24@1452 443
kaf24@1452 444 /*
kaf24@1452 445 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 446 * later on.
kaf24@1452 447 */
kaf24@1452 448 value = apic_read(APIC_TASKPRI);
kaf24@1452 449 value &= ~APIC_TPRI_MASK;
kaf24@1452 450 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 451
kaf24@1452 452 /*
kfraser@11541 453 * After a crash, we no longer service the interrupts and a pending
kfraser@11541 454 * interrupt from previous kernel might still have ISR bit set.
kfraser@11541 455 *
kfraser@11541 456 * Most probably by now CPU has serviced that pending interrupt and
kfraser@11541 457 * it might not have done the ack_APIC_irq() because it thought,
kfraser@11541 458 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
kfraser@11541 459 * does not clear the ISR bit and cpu thinks it has already serivced
kfraser@11541 460 * the interrupt. Hence a vector might get locked. It was noticed
kfraser@11541 461 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
kfraser@11541 462 */
kfraser@11541 463 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
kfraser@11541 464 value = apic_read(APIC_ISR + i*0x10);
kfraser@11541 465 for (j = 31; j >= 0; j--) {
kfraser@11541 466 if (value & (1<<j))
kfraser@11541 467 ack_APIC_irq();
kfraser@11541 468 }
kfraser@11541 469 }
kfraser@11541 470
kfraser@11541 471 /*
kaf24@1452 472 * Now that we are all set up, enable the APIC
kaf24@1452 473 */
kaf24@1452 474 value = apic_read(APIC_SPIV);
kaf24@1452 475 value &= ~APIC_VECTOR_MASK;
kaf24@1452 476 /*
kaf24@1452 477 * Enable APIC
kaf24@1452 478 */
kaf24@1452 479 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 480
iap10@4548 481 /*
iap10@4548 482 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 483 * certain networking cards. If high frequency interrupts are
iap10@4548 484 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 485 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 486 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 487 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 488 * away, oh well :-(
iap10@4548 489 *
iap10@4548 490 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 491 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 492 * BX chipset. ]
iap10@4548 493 */
iap10@4548 494 /*
iap10@4548 495 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 496 * frequent as it makes the interrupt distributon model be more
iap10@4548 497 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 498 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 499 */
iap10@4548 500 #if 1
kaf24@1452 501 /* Enable focus processor (bit==0) */
kaf24@1452 502 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 503 #else
iap10@4548 504 /* Disable focus processor (bit==1) */
iap10@4548 505 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 506 #endif
iap10@4548 507 /*
iap10@4548 508 * Set spurious IRQ vector
iap10@4548 509 */
kaf24@1452 510 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 511 apic_write_around(APIC_SPIV, value);
kaf24@1452 512
kaf24@1452 513 /*
kaf24@1452 514 * Set up LVT0, LVT1:
kaf24@1452 515 *
kaf24@1452 516 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 517 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 518 * we delegate interrupts to the 8259A.
kaf24@1452 519 */
kaf24@1452 520 /*
kaf24@1452 521 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 522 */
kaf24@1452 523 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 524 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 525 value = APIC_DM_EXTINT;
kaf24@4888 526 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 527 smp_processor_id());
kaf24@1452 528 } else {
kaf24@1452 529 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 530 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 531 smp_processor_id());
kaf24@1452 532 }
kaf24@1452 533 apic_write_around(APIC_LVT0, value);
kaf24@1452 534
kaf24@1452 535 /*
kaf24@1452 536 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 537 */
kaf24@1452 538 if (!smp_processor_id())
kaf24@1452 539 value = APIC_DM_NMI;
kaf24@1452 540 else
kaf24@1452 541 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 542 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 543 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 544 apic_write_around(APIC_LVT1, value);
kaf24@1452 545
iap10@4548 546 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 547 maxlvt = get_maxlvt();
kaf24@1452 548 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 549 apic_write(APIC_ESR, 0);
iap10@4548 550 oldvalue = apic_read(APIC_ESR);
kaf24@1452 551
iap10@4548 552 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 553 apic_write_around(APIC_LVTERR, value);
iap10@4548 554 /*
iap10@4548 555 * spec says clear errors after enabling vector.
iap10@4548 556 */
kaf24@1452 557 if (maxlvt > 3)
kaf24@1452 558 apic_write(APIC_ESR, 0);
kaf24@1452 559 value = apic_read(APIC_ESR);
iap10@4548 560 if (value != oldvalue)
kaf24@4888 561 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 562 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 563 oldvalue, value);
kaf24@1452 564 } else {
iap10@4548 565 if (esr_disable)
iap10@4548 566 /*
iap10@4548 567 * Something untraceble is creating bad interrupts on
iap10@4548 568 * secondary quads ... for the moment, just leave the
iap10@4548 569 * ESR disabled - we can't do anything useful with the
iap10@4548 570 * errors anyway - mbligh
iap10@4548 571 */
iap10@4548 572 printk("Leaving ESR disabled.\n");
kaf24@4888 573 else
kaf24@4888 574 printk("No ESR for 82489DX.\n");
kaf24@1452 575 }
kaf24@1452 576
kaf24@8594 577 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@8594 578 setup_apic_nmi_watchdog();
kaf24@8847 579 apic_pm_activate();
kaf24@1452 580 }
kaf24@1452 581
kfraser@11541 582 /*
kfraser@11541 583 * If Linux enabled the LAPIC against the BIOS default
kfraser@11541 584 * disable it down before re-entering the BIOS on shutdown.
kfraser@11541 585 * Otherwise the BIOS may get confused and not power-off.
kfraser@11541 586 * Additionally clear all LVT entries before disable_local_APIC
kfraser@11541 587 * for the case where Linux didn't enable the LAPIC.
kfraser@11541 588 */
kfraser@11541 589 void lapic_shutdown(void)
kfraser@11541 590 {
kfraser@11541 591 unsigned long flags;
kfraser@11541 592
kfraser@11541 593 if (!cpu_has_apic)
kfraser@11541 594 return;
kfraser@11541 595
kfraser@11541 596 local_irq_save(flags);
kfraser@11541 597 clear_local_APIC();
kfraser@11541 598
kfraser@11541 599 if (enabled_via_apicbase)
kfraser@11541 600 disable_local_APIC();
kfraser@11541 601
kfraser@11541 602 local_irq_restore(flags);
kfraser@11541 603 }
kfraser@11541 604
kaf24@8847 605 static void apic_pm_activate(void) { }
kaf24@8847 606
kaf24@1452 607 /*
kaf24@1452 608 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 609 * Original code written by Keir Fraser.
kaf24@1452 610 */
kaf24@1452 611
kaf24@5211 612 static void __init lapic_disable(char *str)
kaf24@5211 613 {
kaf24@5211 614 enable_local_apic = -1;
kaf24@5211 615 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 616 }
kaf24@5211 617 custom_param("nolapic", lapic_disable);
kaf24@5211 618
kaf24@5211 619 static void __init lapic_enable(char *str)
kaf24@5211 620 {
kaf24@5211 621 enable_local_apic = 1;
kaf24@5211 622 }
kaf24@5211 623 custom_param("lapic", lapic_enable);
kaf24@5211 624
kaf24@4888 625 static void __init apic_set_verbosity(char *str)
kaf24@4888 626 {
kaf24@4888 627 if (strcmp("debug", str) == 0)
kaf24@4888 628 apic_verbosity = APIC_DEBUG;
kaf24@4888 629 else if (strcmp("verbose", str) == 0)
kaf24@4888 630 apic_verbosity = APIC_VERBOSE;
kaf24@5211 631 else
kaf24@5211 632 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@5211 633 " use apic_verbosity=verbose or apic_verbosity=debug", str);
kaf24@4888 634 }
kaf24@5211 635 custom_param("apic_verbosity", apic_set_verbosity);
kaf24@4888 636
kaf24@1452 637 static int __init detect_init_APIC (void)
kaf24@1452 638 {
kaf24@1452 639 u32 h, l, features;
kaf24@1452 640
kaf24@5211 641 /* Disabled by kernel option? */
kaf24@5211 642 if (enable_local_apic < 0)
kaf24@5211 643 return -1;
kaf24@5211 644
kaf24@1452 645 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 646 case X86_VENDOR_AMD:
iap10@4548 647 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 648 (boot_cpu_data.x86 == 15))
kaf24@1452 649 break;
kaf24@1452 650 goto no_apic;
kaf24@1452 651 case X86_VENDOR_INTEL:
iap10@4548 652 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 653 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 654 break;
kaf24@1452 655 goto no_apic;
kaf24@1452 656 default:
kaf24@1452 657 goto no_apic;
kaf24@1452 658 }
kaf24@1452 659
kaf24@1452 660 if (!cpu_has_apic) {
kaf24@1452 661 /*
kaf24@5211 662 * Over-ride BIOS and try to enable the local
kaf24@5211 663 * APIC only if "lapic" specified.
kaf24@5211 664 */
kaf24@5211 665 if (enable_local_apic <= 0) {
kaf24@5211 666 printk("Local APIC disabled by BIOS -- "
kaf24@5211 667 "you can enable it with \"lapic\"\n");
kaf24@5211 668 return -1;
kaf24@5211 669 }
kaf24@5211 670 /*
kaf24@1452 671 * Some BIOSes disable the local APIC in the
kaf24@1452 672 * APIC_BASE MSR. This can only be done in
iap10@4548 673 * software for Intel P6 or later and AMD K7
iap10@4548 674 * (Model > 1) or later.
kaf24@1452 675 */
kaf24@1452 676 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 677 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 678 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 679 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 680 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 681 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 682 enabled_via_apicbase = 1;
kaf24@1452 683 }
kaf24@1452 684 }
kaf24@4888 685 /*
kaf24@4888 686 * The APIC feature bit should now be enabled
kaf24@4888 687 * in `cpuid'
kaf24@4888 688 */
kaf24@1452 689 features = cpuid_edx(1);
kaf24@1452 690 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 691 printk("Could not enable APIC!\n");
kaf24@1452 692 return -1;
kaf24@1452 693 }
kaf24@4619 694
iap10@4548 695 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 696 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 697
kaf24@1452 698 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 699 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 700 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 701 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 702
kaf24@4619 703 if (nmi_watchdog != NMI_NONE)
kaf24@4619 704 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 705
kaf24@1452 706 printk("Found and enabled local APIC!\n");
iap10@4548 707
kaf24@8847 708 apic_pm_activate();
kaf24@8847 709
kaf24@1452 710 return 0;
kaf24@1452 711
iap10@4548 712 no_apic:
kaf24@1452 713 printk("No local APIC present or hardware disabled\n");
kaf24@1452 714 return -1;
kaf24@1452 715 }
kaf24@1452 716
kaf24@1452 717 void __init init_apic_mappings(void)
kaf24@1452 718 {
iap10@4548 719 unsigned long apic_phys;
kaf24@1452 720
kaf24@1452 721 /*
iap10@4548 722 * If no local APIC can be found then set up a fake all
iap10@4548 723 * zeroes page to simulate the local APIC and another
iap10@4548 724 * one for the IO-APIC.
kaf24@1452 725 */
kaf24@9582 726 if (!smp_found_config && detect_init_APIC()) {
kaf24@5398 727 apic_phys = __pa(alloc_xenheap_page());
kaf24@9582 728 memset(__va(apic_phys), 0, PAGE_SIZE);
kaf24@9582 729 } else
kaf24@1452 730 apic_phys = mp_lapic_addr;
kaf24@1452 731
kaf24@1452 732 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 733 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 734 apic_phys);
kaf24@1452 735
kaf24@1452 736 /*
kaf24@1452 737 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 738 * default configuration (or the MP table is broken).
kaf24@1452 739 */
kaf24@1452 740 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 741 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 742
kaf24@1452 743 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 744 {
iap10@4548 745 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 746 int i;
kaf24@1452 747
kaf24@1452 748 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 749 if (smp_found_config) {
kaf24@1452 750 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 751 if (!ioapic_phys) {
iap10@4548 752 printk(KERN_ERR
iap10@4548 753 "WARNING: bogus zero IO-APIC "
iap10@4548 754 "address found in MPTABLE, "
iap10@4548 755 "disabling IO/APIC support!\n");
iap10@4548 756 smp_found_config = 0;
iap10@4548 757 skip_ioapic_setup = 1;
iap10@4548 758 goto fake_ioapic_page;
iap10@4548 759 }
iap10@4548 760 } else {
iap10@4548 761 fake_ioapic_page:
kaf24@5398 762 ioapic_phys = __pa(alloc_xenheap_page());
kaf24@9582 763 memset(__va(ioapic_phys), 0, PAGE_SIZE);
iap10@4548 764 }
kaf24@1452 765 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 766 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 767 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 768 idx++;
kaf24@1452 769 }
kaf24@1452 770 }
kaf24@1452 771 #endif
kaf24@1452 772 }
kaf24@1452 773
kaf24@1452 774 /*****************************************************************************
kaf24@1452 775 * APIC calibration
kaf24@1452 776 *
kaf24@1452 777 * The APIC is programmed in bus cycles.
kaf24@1452 778 * Timeout values should specified in real time units.
kaf24@1452 779 * The "cheapest" time source is the cyclecounter.
kaf24@1452 780 *
kaf24@1452 781 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 782 *
kaf24@1452 783 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 784 * timer chip to generate periodic timer interupts.
kaf24@1452 785 *****************************************************************************/
kaf24@1452 786
kaf24@1452 787 /* used for system time scaling */
kaf24@1672 788 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 789 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 790 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 791
kaf24@1452 792 /*
kaf24@1452 793 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 794 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 795 * to calibrate.
kaf24@1452 796 */
kaf24@1452 797 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 798 {
kaf24@1452 799 /*extern spinlock_t i8253_lock;*/
kaf24@1452 800 /*unsigned long flags;*/
iap10@4548 801
kaf24@1452 802 unsigned int count;
iap10@4548 803
kaf24@1452 804 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 805
iap10@4548 806 outb_p(0x00, PIT_MODE);
iap10@4548 807 count = inb_p(PIT_CH0);
iap10@4548 808 count |= inb_p(PIT_CH0) << 8;
iap10@4548 809
kaf24@1452 810 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 811
kaf24@1452 812 return count;
kaf24@1452 813 }
kaf24@1452 814
iap10@4548 815 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 816 static void __init wait_8254_wraparound(void)
kaf24@1452 817 {
kaf24@4888 818 unsigned int curr_count, prev_count;
kaf24@4888 819
kaf24@1452 820 curr_count = get_8254_timer_count();
kaf24@1452 821 do {
kaf24@1452 822 prev_count = curr_count;
kaf24@1452 823 curr_count = get_8254_timer_count();
iap10@4548 824
kaf24@4888 825 /* workaround for broken Mercury/Neptune */
kaf24@4888 826 if (prev_count >= curr_count + 0x100)
kaf24@4888 827 curr_count = get_8254_timer_count();
kaf24@4888 828
kaf24@4888 829 } while (prev_count >= curr_count);
kaf24@1452 830 }
kaf24@1452 831
kaf24@1452 832 /*
iap10@4548 833 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 834 * we override this later
iap10@4548 835 */
kaf24@4888 836 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 837
iap10@4548 838 /*
kaf24@1452 839 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 840 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 841 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 842 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 843 * call this function only once, with the real, calibrated value.
kaf24@1452 844 *
kaf24@1452 845 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 846 * P5 APIC double write bug.
kaf24@1452 847 */
iap10@4548 848
kaf24@1452 849 #define APIC_DIVISOR 1
iap10@4548 850
kaf24@5146 851 void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 852 {
iap10@4548 853 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 854
iap10@4548 855 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 856 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 857 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 858 if (!APIC_INTEGRATED(ver))
iap10@4548 859 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 860 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 861
kaf24@1452 862 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 863 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 864
kaf24@1452 865 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 866 }
kaf24@1452 867
kaf24@5146 868 static void __init setup_APIC_timer(unsigned int clocks)
kaf24@1452 869 {
kaf24@1452 870 unsigned long flags;
kaf24@5146 871 local_irq_save(flags);
kaf24@5146 872 __setup_APIC_LVTT(clocks);
kaf24@5146 873 local_irq_restore(flags);
kaf24@1452 874 }
kaf24@1452 875
kaf24@1452 876 /*
kaf24@5146 877 * In this function we calibrate APIC bus clocks to the external
kaf24@5146 878 * timer. Unfortunately we cannot use jiffies and the timer irq
kaf24@5146 879 * to calibrate, since some later bootup code depends on getting
kaf24@5146 880 * the first irq? Ugh.
kaf24@1452 881 *
kaf24@5146 882 * We want to do the calibration only once since we
kaf24@5146 883 * want to have local timer irqs syncron. CPUs connected
kaf24@5146 884 * by the same APIC bus have the very same bus frequency.
kaf24@5146 885 * And we want to have irqs off anyways, no accidental
kaf24@5146 886 * APIC irq that way.
kaf24@1452 887 */
kaf24@1452 888
kaf24@1452 889 int __init calibrate_APIC_clock(void)
kaf24@1452 890 {
kaf24@1452 891 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 892 long tt1, tt2;
kaf24@1452 893 long result;
kaf24@1452 894 int i;
kaf24@1452 895 const int LOOPS = HZ/10;
kaf24@1452 896
kaf24@4888 897 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 898
iap10@4548 899 /*
iap10@4548 900 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 901 * value into the APIC clock, we just want to get the
iap10@4548 902 * counter running for calibration.
iap10@4548 903 */
kaf24@1452 904 __setup_APIC_LVTT(1000000000);
kaf24@1452 905
iap10@4548 906 /*
iap10@4548 907 * The timer chip counts down to zero. Let's wait
kaf24@1452 908 * for a wraparound to start exact measurement:
iap10@4548 909 * (the current tick might have been already half done)
iap10@4548 910 */
iap10@4548 911 wait_timer_tick();
iap10@4548 912
iap10@4548 913 /*
iap10@4548 914 * We wrapped around just now. Let's start:
iap10@4548 915 */
iap10@4548 916 if (cpu_has_tsc)
kaf24@4619 917 rdtscll(t1);
kaf24@1452 918 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 919
iap10@4548 920 /*
iap10@4548 921 * Let's wait LOOPS wraprounds:
iap10@4548 922 */
kaf24@1452 923 for (i = 0; i < LOOPS; i++)
iap10@4548 924 wait_timer_tick();
kaf24@1452 925
kaf24@1452 926 tt2 = apic_read(APIC_TMCCT);
iap10@4548 927 if (cpu_has_tsc)
kaf24@4619 928 rdtscll(t2);
kaf24@1452 929
iap10@4548 930 /*
iap10@4548 931 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 932 * might have overflown, but note that we use signed
kaf24@1452 933 * longs, thus no extra care needed.
kaf24@4888 934 *
kaf24@4888 935 * underflown to be exact, as the timer counts down ;)
iap10@4548 936 */
iap10@4548 937
kaf24@1452 938 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 939
iap10@4548 940 if (cpu_has_tsc)
kaf24@4888 941 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 942 "%ld.%04ld MHz.\n",
kaf24@4888 943 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 944 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 945
kaf24@4888 946 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kfraser@11204 947 "%ld.%04ld MHz.\n",
kfraser@11204 948 result/(1000000/HZ),
kfraser@11204 949 result%(1000000/HZ));
kaf24@1452 950
kaf24@1452 951 /* set up multipliers for accurate timer code */
kaf24@1452 952 bus_freq = result*HZ;
kaf24@1452 953 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 954 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 955
kaf24@4888 956 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 957 /* reset APIC to zero timeout value */
kaf24@1452 958 __setup_APIC_LVTT(0);
iap10@4548 959
kaf24@1452 960 return result;
kaf24@1452 961 }
kaf24@1452 962
kaf24@9184 963 u32 get_apic_bus_cycle(void)
kaf24@7546 964 {
kaf24@9184 965 return bus_cycle;
kaf24@7546 966 }
kaf24@5146 967
kaf24@5146 968 static unsigned int calibration_result;
kaf24@5146 969
kaf24@5146 970 void __init setup_boot_APIC_clock(void)
kaf24@1452 971 {
kaf24@8847 972 unsigned long flags;
kaf24@5146 973 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
kaf24@1452 974 using_apic_timer = 1;
kaf24@5146 975
kaf24@8847 976 local_irq_save(flags);
kaf24@8847 977
kaf24@5146 978 calibration_result = calibrate_APIC_clock();
kaf24@5146 979 /*
kaf24@5146 980 * Now set up the timer for real.
kaf24@5146 981 */
kaf24@5146 982 setup_APIC_timer(calibration_result);
kaf24@5146 983
kaf24@8847 984 local_irq_restore(flags);
kaf24@5146 985 }
kaf24@5146 986
kaf24@8847 987 void __devinit setup_secondary_APIC_clock(void)
kaf24@5146 988 {
kaf24@5146 989 setup_APIC_timer(calibration_result);
kaf24@5146 990 }
kaf24@5146 991
kaf24@8847 992 void disable_APIC_timer(void)
kaf24@5146 993 {
kaf24@5146 994 if (using_apic_timer) {
kaf24@5146 995 unsigned long v;
kaf24@5146 996
kaf24@5146 997 v = apic_read(APIC_LVTT);
kaf24@5146 998 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@5146 999 }
kaf24@5146 1000 }
kaf24@5146 1001
kaf24@5146 1002 void enable_APIC_timer(void)
kaf24@5146 1003 {
kaf24@5146 1004 if (using_apic_timer) {
kaf24@5146 1005 unsigned long v;
kaf24@5146 1006
kaf24@5146 1007 v = apic_read(APIC_LVTT);
kaf24@5146 1008 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
kaf24@5146 1009 }
kaf24@1452 1010 }
kaf24@1452 1011
kaf24@1452 1012 #undef APIC_DIVISOR
kaf24@1452 1013
kaf24@1452 1014 /*
kaf24@1452 1015 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 1016 * returns 1 on success
kaf24@1452 1017 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 1018 */
kaf24@8586 1019 int reprogram_timer(s_time_t timeout)
kaf24@1452 1020 {
kaf24@1452 1021 s_time_t now;
kaf24@1452 1022 s_time_t expire;
kaf24@1452 1023 u64 apic_tmict;
kaf24@1452 1024
kaf24@1452 1025 /*
kfraser@14340 1026 * If we don't have local APIC then we just poll the timer list off the
kfraser@14340 1027 * PIT interrupt.
kfraser@14340 1028 */
kfraser@14340 1029 if ( !cpu_has_apic )
kfraser@14340 1030 return 1;
kfraser@14340 1031
kfraser@14340 1032 /*
kaf24@1452 1033 * We use this value because we don't trust zero (we think it may just
kaf24@1452 1034 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 1035 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 1036 */
kaf24@1452 1037 if ( timeout == 0 )
kaf24@1452 1038 {
kaf24@1452 1039 apic_tmict = 0xffffffff;
kaf24@1452 1040 goto reprogram;
kaf24@1452 1041 }
kaf24@1452 1042
kaf24@1452 1043 now = NOW();
kaf24@1452 1044 expire = timeout - now; /* value from now */
kaf24@1452 1045
kaf24@1452 1046 if ( expire <= 0 )
kaf24@1452 1047 {
kaf24@1452 1048 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 1049 smp_processor_id(), (u32)(now>>32),
kaf24@1452 1050 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 1051 return 0;
kaf24@1452 1052 }
kaf24@1452 1053
kaf24@1452 1054 /* conversion to bus units */
kaf24@1452 1055 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 1056
kaf24@1452 1057 if ( apic_tmict >= 0xffffffff )
kaf24@1452 1058 {
kaf24@1452 1059 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 1060 apic_tmict = 0xffffffff;
kaf24@1452 1061 }
kaf24@1452 1062
kaf24@1452 1063 if ( apic_tmict == 0 )
kaf24@1452 1064 {
kaf24@1452 1065 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 1066 return 0;
kaf24@1452 1067 }
kaf24@1452 1068
kaf24@1452 1069 reprogram:
kaf24@1452 1070 /* Program the timer. */
kaf24@1452 1071 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 1072
kaf24@1452 1073 return 1;
kaf24@1452 1074 }
kaf24@1452 1075
kaf24@8846 1076 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 1077 {
kaf24@1452 1078 ack_APIC_irq();
kaf24@1452 1079 perfc_incrc(apic_timer);
kaf24@8586 1080 raise_softirq(TIMER_SOFTIRQ);
kaf24@1452 1081 }
kaf24@1452 1082
kaf24@1452 1083 /*
kaf24@1452 1084 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 1085 */
kaf24@8846 1086 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1087 {
kaf24@1452 1088 unsigned long v;
kaf24@1452 1089
kaf24@8847 1090 irq_enter();
kaf24@1452 1091 /*
kaf24@1452 1092 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 1093 * if it is a vectored one. Just in case...
kaf24@1452 1094 * Spurious interrupts should not be ACKed.
kaf24@1452 1095 */
kaf24@1452 1096 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 1097 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 1098 ack_APIC_irq();
kaf24@1452 1099
kaf24@1452 1100 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@5146 1101 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 1102 smp_processor_id());
kaf24@8847 1103 irq_exit();
kaf24@1452 1104 }
kaf24@1452 1105
kaf24@1452 1106 /*
kaf24@1452 1107 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 1108 */
kaf24@1452 1109
kaf24@8846 1110 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1111 {
kaf24@1452 1112 unsigned long v, v1;
kaf24@1452 1113
kaf24@8847 1114 irq_enter();
kaf24@1452 1115 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 1116 v = apic_read(APIC_ESR);
kaf24@1452 1117 apic_write(APIC_ESR, 0);
kaf24@1452 1118 v1 = apic_read(APIC_ESR);
kaf24@1452 1119 ack_APIC_irq();
kaf24@1452 1120 atomic_inc(&irq_err_count);
kaf24@1452 1121
kaf24@1452 1122 /* Here is what the APIC error bits mean:
kaf24@1452 1123 0: Send CS error
kaf24@1452 1124 1: Receive CS error
kaf24@1452 1125 2: Send accept error
kaf24@1452 1126 3: Receive accept error
kaf24@1452 1127 4: Reserved
kaf24@1452 1128 5: Send illegal vector
kaf24@1452 1129 6: Received illegal vector
kaf24@1452 1130 7: Illegal register address
kaf24@1452 1131 */
kaf24@5146 1132 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@5146 1133 smp_processor_id(), v , v1);
kaf24@8847 1134 irq_exit();
kaf24@1452 1135 }
kaf24@1452 1136
kaf24@1452 1137 /*
kaf24@1452 1138 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 1139 * a UP kernel.
kaf24@1452 1140 */
kaf24@1452 1141 int __init APIC_init_uniprocessor (void)
kaf24@1452 1142 {
kaf24@5211 1143 if (enable_local_apic < 0)
kaf24@5211 1144 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 1145
kaf24@1452 1146 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 1147 return -1;
kaf24@1452 1148
kaf24@1452 1149 /*
kaf24@1452 1150 * Complain if the BIOS pretends there is one.
kaf24@1452 1151 */
iap10@4548 1152 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 1153 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 1154 boot_cpu_physical_apicid);
kfraser@11541 1155 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 1156 return -1;
kaf24@1452 1157 }
kaf24@1452 1158
kaf24@1452 1159 verify_local_APIC();
kaf24@1452 1160
kaf24@1452 1161 connect_bsp_APIC();
kaf24@1452 1162
kfraser@11541 1163 /*
kfraser@11541 1164 * Hack: In case of kdump, after a crash, kernel might be booting
kfraser@11541 1165 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
kfraser@11541 1166 * might be zero if read from MP tables. Get it from LAPIC.
kfraser@11541 1167 */
kfraser@11541 1168 #ifdef CONFIG_CRASH_DUMP
kfraser@11541 1169 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kfraser@11541 1170 #endif
kaf24@4804 1171 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 1172
kaf24@1452 1173 setup_local_APIC();
kaf24@1452 1174
kaf24@5146 1175 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@5146 1176 check_nmi_watchdog();
kaf24@1452 1177 #ifdef CONFIG_X86_IO_APIC
iap10@4548 1178 if (smp_found_config)
iap10@4548 1179 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 1180 setup_IO_APIC();
iap10@4548 1181 #endif
kaf24@5146 1182 setup_boot_APIC_clock();
kaf24@1452 1183
kaf24@1452 1184 return 0;
kaf24@1452 1185 }