ia64/xen-unstable

annotate xen/drivers/scsi/aacraid/aacraid.h @ 236:170eb7974e43

bitkeeper revision 1.94 (3e5a4f5fzVaxemjfCt0N0OH8PYPiuw)

Rename xen-2.4.16 to just "xen" to reflect that it hasn't got any
relation to the Linux kernel version.
author iap10@labyrinth.cl.cam.ac.uk
date Mon Feb 24 16:59:11 2003 +0000 (2003-02-24)
parents
children 7233489302e6 9888f92572ba
rev   line source
iap10@236 1
iap10@236 2 /* #define dprintk(x) */
iap10@236 3 // #define dprintk(x) printk x
iap10@236 4 #define dprintk(x)
iap10@236 5
iap10@236 6
iap10@236 7 #include <asm/byteorder.h>
iap10@236 8
iap10@236 9 #define TRY_TASKLET
iap10@236 10 #ifdef TRY_TASKLET
iap10@236 11 /* XXX SMH: trying to use softirqs to trigger stuff done prev by threads */
iap10@236 12 #include <xeno/interrupt.h> /* for tasklet/softirq stuff */
iap10@236 13 #endif
iap10@236 14
iap10@236 15 /*------------------------------------------------------------------------------
iap10@236 16 * D E F I N E S
iap10@236 17 *----------------------------------------------------------------------------*/
iap10@236 18
iap10@236 19 #define MAXIMUM_NUM_CONTAINERS 31
iap10@236 20 #define MAXIMUM_NUM_ADAPTERS 8
iap10@236 21
iap10@236 22 #define AAC_NUM_FIB 578
iap10@236 23 #define AAC_NUM_IO_FIB 512
iap10@236 24
iap10@236 25 #define AAC_MAX_TARGET (MAXIMUM_NUM_CONTAINERS+1)
iap10@236 26 //#define AAC_MAX_TARGET (16)
iap10@236 27 #define AAC_MAX_LUN (8)
iap10@236 28
iap10@236 29 /*
iap10@236 30 * These macros convert from physical channels to virtual channels
iap10@236 31 */
iap10@236 32 #define CONTAINER_CHANNEL (0)
iap10@236 33 #define aac_phys_to_logical(x) (x+1)
iap10@236 34 #define aac_logical_to_phys(x) (x?x-1:0)
iap10@236 35
iap10@236 36 #define AAC_DETAILED_STATUS_INFO
iap10@236 37
iap10@236 38 struct diskparm
iap10@236 39 {
iap10@236 40 int heads;
iap10@236 41 int sectors;
iap10@236 42 int cylinders;
iap10@236 43 };
iap10@236 44
iap10@236 45
iap10@236 46 /*
iap10@236 47 * DON'T CHANGE THE ORDER, this is set by the firmware
iap10@236 48 */
iap10@236 49
iap10@236 50 #define CT_NONE 0
iap10@236 51 #define CT_VOLUME 1
iap10@236 52 #define CT_MIRROR 2
iap10@236 53 #define CT_STRIPE 3
iap10@236 54 #define CT_RAID5 4
iap10@236 55 #define CT_SSRW 5
iap10@236 56 #define CT_SSRO 6
iap10@236 57 #define CT_MORPH 7
iap10@236 58 #define CT_PASSTHRU 8
iap10@236 59 #define CT_RAID4 9
iap10@236 60 #define CT_RAID10 10 /* stripe of mirror */
iap10@236 61 #define CT_RAID00 11 /* stripe of stripe */
iap10@236 62 #define CT_VOLUME_OF_MIRRORS 12 /* volume of mirror */
iap10@236 63 #define CT_PSEUDO_RAID 13 /* really raid4 */
iap10@236 64 #define CT_LAST_VOLUME_TYPE 14
iap10@236 65
iap10@236 66 /*
iap10@236 67 * Types of objects addressable in some fashion by the client.
iap10@236 68 * This is a superset of those objects handled just by the filesystem
iap10@236 69 * and includes "raw" objects that an administrator would use to
iap10@236 70 * configure containers and filesystems.
iap10@236 71 */
iap10@236 72
iap10@236 73 #define FT_REG 1 /* regular file */
iap10@236 74 #define FT_DIR 2 /* directory */
iap10@236 75 #define FT_BLK 3 /* "block" device - reserved */
iap10@236 76 #define FT_CHR 4 /* "character special" device - reserved */
iap10@236 77 #define FT_LNK 5 /* symbolic link */
iap10@236 78 #define FT_SOCK 6 /* socket */
iap10@236 79 #define FT_FIFO 7 /* fifo */
iap10@236 80 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
iap10@236 81 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/target/lun */
iap10@236 82 #define FT_SLICE 10 /* virtual disk - raw volume - slice */
iap10@236 83 #define FT_PARTITION 11 /* FSA partition - carved out of a slice - building block for containers */
iap10@236 84 #define FT_VOLUME 12 /* Container - Volume Set */
iap10@236 85 #define FT_STRIPE 13 /* Container - Stripe Set */
iap10@236 86 #define FT_MIRROR 14 /* Container - Mirror Set */
iap10@236 87 #define FT_RAID5 15 /* Container - Raid 5 Set */
iap10@236 88 #define FT_DATABASE 16 /* Storage object with "foreign" content manager */
iap10@236 89
iap10@236 90 /*
iap10@236 91 * Host side memory scatter gather list
iap10@236 92 * Used by the adapter for read, write, and readdirplus operations
iap10@236 93 * We have seperate 32 and 64 bit version because even
iap10@236 94 * on 64 bit systems not all cards support the 64 bit version
iap10@236 95 */
iap10@236 96 struct sgentry {
iap10@236 97 u32 addr; /* 32-bit address. */
iap10@236 98 u32 count; /* Length. */
iap10@236 99 };
iap10@236 100
iap10@236 101 struct sgentry64 {
iap10@236 102 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
iap10@236 103 u32 count; /* Length. */
iap10@236 104 };
iap10@236 105
iap10@236 106 /*
iap10@236 107 * SGMAP
iap10@236 108 *
iap10@236 109 * This is the SGMAP structure for all commands that use
iap10@236 110 * 32-bit addressing.
iap10@236 111 */
iap10@236 112
iap10@236 113 struct sgmap {
iap10@236 114 u32 count;
iap10@236 115 struct sgentry sg[1];
iap10@236 116 };
iap10@236 117
iap10@236 118 struct sgmap64 {
iap10@236 119 u32 count;
iap10@236 120 struct sgentry64 sg[1];
iap10@236 121 };
iap10@236 122
iap10@236 123 struct creation_info
iap10@236 124 {
iap10@236 125 u8 buildnum; /* e.g., 588 */
iap10@236 126 u8 usec; /* e.g., 588 */
iap10@236 127 u8 via; /* e.g., 1 = FSU,
iap10@236 128 * 2 = API
iap10@236 129 */
iap10@236 130 u8 year; /* e.g., 1997 = 97 */
iap10@236 131 u32 date; /*
iap10@236 132 * unsigned Month :4; // 1 - 12
iap10@236 133 * unsigned Day :6; // 1 - 32
iap10@236 134 * unsigned Hour :6; // 0 - 23
iap10@236 135 * unsigned Minute :6; // 0 - 60
iap10@236 136 * unsigned Second :6; // 0 - 60
iap10@236 137 */
iap10@236 138 u32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
iap10@236 139 };
iap10@236 140
iap10@236 141
iap10@236 142 /*
iap10@236 143 * Define all the constants needed for the communication interface
iap10@236 144 */
iap10@236 145
iap10@236 146 /*
iap10@236 147 * Define how many queue entries each queue will have and the total
iap10@236 148 * number of entries for the entire communication interface. Also define
iap10@236 149 * how many queues we support.
iap10@236 150 *
iap10@236 151 * This has to match the controller
iap10@236 152 */
iap10@236 153
iap10@236 154 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
iap10@236 155 #define HOST_HIGH_CMD_ENTRIES 4
iap10@236 156 #define HOST_NORM_CMD_ENTRIES 8
iap10@236 157 #define ADAP_HIGH_CMD_ENTRIES 4
iap10@236 158 #define ADAP_NORM_CMD_ENTRIES 512
iap10@236 159 #define HOST_HIGH_RESP_ENTRIES 4
iap10@236 160 #define HOST_NORM_RESP_ENTRIES 512
iap10@236 161 #define ADAP_HIGH_RESP_ENTRIES 4
iap10@236 162 #define ADAP_NORM_RESP_ENTRIES 8
iap10@236 163
iap10@236 164 #define TOTAL_QUEUE_ENTRIES \
iap10@236 165 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
iap10@236 166 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
iap10@236 167
iap10@236 168
iap10@236 169 /*
iap10@236 170 * Set the queues on a 16 byte alignment
iap10@236 171 */
iap10@236 172
iap10@236 173 #define QUEUE_ALIGNMENT 16
iap10@236 174
iap10@236 175 /*
iap10@236 176 * The queue headers define the Communication Region queues. These
iap10@236 177 * are physically contiguous and accessible by both the adapter and the
iap10@236 178 * host. Even though all queue headers are in the same contiguous block
iap10@236 179 * they will be represented as individual units in the data structures.
iap10@236 180 */
iap10@236 181
iap10@236 182 struct aac_entry {
iap10@236 183 u32 size; /* Size in bytes of Fib which this QE points to */
iap10@236 184 u32 addr; /* Receiver address of the FIB */
iap10@236 185 };
iap10@236 186
iap10@236 187 /*
iap10@236 188 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
iap10@236 189 * adjacently and in that order.
iap10@236 190 */
iap10@236 191
iap10@236 192 struct aac_qhdr {
iap10@236 193 u64 header_addr; /* Address to hand the adapter to access to this queue head */
iap10@236 194 u32 *producer; /* The producer index for this queue (host address) */
iap10@236 195 u32 *consumer; /* The consumer index for this queue (host address) */
iap10@236 196 };
iap10@236 197
iap10@236 198 /*
iap10@236 199 * Define all the events which the adapter would like to notify
iap10@236 200 * the host of.
iap10@236 201 */
iap10@236 202
iap10@236 203 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
iap10@236 204 #define HostHighCmdQue 2 /* Change in host high priority command queue */
iap10@236 205 #define HostNormRespQue 3 /* Change in host normal priority response queue */
iap10@236 206 #define HostHighRespQue 4 /* Change in host high priority response queue */
iap10@236 207 #define AdapNormRespNotFull 5
iap10@236 208 #define AdapHighRespNotFull 6
iap10@236 209 #define AdapNormCmdNotFull 7
iap10@236 210 #define AdapHighCmdNotFull 8
iap10@236 211 #define SynchCommandComplete 9
iap10@236 212 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
iap10@236 213
iap10@236 214 /*
iap10@236 215 * Define all the events the host wishes to notify the
iap10@236 216 * adapter of. The first four values much match the Qid the
iap10@236 217 * corresponding queue.
iap10@236 218 */
iap10@236 219
iap10@236 220 #define AdapNormCmdQue 2
iap10@236 221 #define AdapHighCmdQue 3
iap10@236 222 #define AdapNormRespQue 6
iap10@236 223 #define AdapHighRespQue 7
iap10@236 224 #define HostShutdown 8
iap10@236 225 #define HostPowerFail 9
iap10@236 226 #define FatalCommError 10
iap10@236 227 #define HostNormRespNotFull 11
iap10@236 228 #define HostHighRespNotFull 12
iap10@236 229 #define HostNormCmdNotFull 13
iap10@236 230 #define HostHighCmdNotFull 14
iap10@236 231 #define FastIo 15
iap10@236 232 #define AdapPrintfDone 16
iap10@236 233
iap10@236 234 /*
iap10@236 235 * Define all the queues that the adapter and host use to communicate
iap10@236 236 * Number them to match the physical queue layout.
iap10@236 237 */
iap10@236 238
iap10@236 239 enum aac_queue_types {
iap10@236 240 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
iap10@236 241 HostHighCmdQueue, /* Adapter to host high priority command traffic */
iap10@236 242 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
iap10@236 243 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
iap10@236 244 HostNormRespQueue, /* Adapter to host normal priority response traffic */
iap10@236 245 HostHighRespQueue, /* Adapter to host high priority response traffic */
iap10@236 246 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
iap10@236 247 AdapHighRespQueue /* Host to adapter high priority response traffic */
iap10@236 248 };
iap10@236 249
iap10@236 250 /*
iap10@236 251 * Assign type values to the FSA communication data structures
iap10@236 252 */
iap10@236 253
iap10@236 254 #define FIB_MAGIC 0x0001
iap10@236 255
iap10@236 256 /*
iap10@236 257 * Define the priority levels the FSA communication routines support.
iap10@236 258 */
iap10@236 259
iap10@236 260 #define FsaNormal 1
iap10@236 261 #define FsaHigh 2
iap10@236 262
iap10@236 263 /*
iap10@236 264 * Define the FIB. The FIB is the where all the requested data and
iap10@236 265 * command information are put to the application on the FSA adapter.
iap10@236 266 */
iap10@236 267
iap10@236 268 struct aac_fibhdr {
iap10@236 269 u32 XferState; // Current transfer state for this CCB
iap10@236 270 u16 Command; // Routing information for the destination
iap10@236 271 u8 StructType; // Type FIB
iap10@236 272 u8 Flags; // Flags for FIB
iap10@236 273 u16 Size; // Size of this FIB in bytes
iap10@236 274 u16 SenderSize; // Size of the FIB in the sender (for
iap10@236 275 // response sizing)
iap10@236 276 u32 SenderFibAddress; // Host defined data in the FIB
iap10@236 277 u32 ReceiverFibAddress; // Logical address of this FIB for the adapter
iap10@236 278 u32 SenderData; // Place holder for the sender to store data
iap10@236 279 union {
iap10@236 280 struct {
iap10@236 281 u32 _ReceiverTimeStart; // Timestamp for receipt of fib
iap10@236 282 u32 _ReceiverTimeDone; // Timestamp for completion of fib
iap10@236 283 } _s;
iap10@236 284 struct list_head _FibLinks; // Used to link Adapter Initiated
iap10@236 285 // Fibs on the host
iap10@236 286 } _u;
iap10@236 287 };
iap10@236 288
iap10@236 289 #define FibLinks _u._FibLinks
iap10@236 290
iap10@236 291 #define FIB_DATA_SIZE_IN_BYTES (512 - sizeof(struct aac_fibhdr))
iap10@236 292
iap10@236 293
iap10@236 294 struct hw_fib {
iap10@236 295 struct aac_fibhdr header;
iap10@236 296 u8 data[FIB_DATA_SIZE_IN_BYTES]; // Command specific data
iap10@236 297 };
iap10@236 298
iap10@236 299 /*
iap10@236 300 * FIB commands
iap10@236 301 */
iap10@236 302
iap10@236 303 #define TestCommandResponse 1
iap10@236 304 #define TestAdapterCommand 2
iap10@236 305 /*
iap10@236 306 * Lowlevel and comm commands
iap10@236 307 */
iap10@236 308 #define LastTestCommand 100
iap10@236 309 #define ReinitHostNormCommandQueue 101
iap10@236 310 #define ReinitHostHighCommandQueue 102
iap10@236 311 #define ReinitHostHighRespQueue 103
iap10@236 312 #define ReinitHostNormRespQueue 104
iap10@236 313 #define ReinitAdapNormCommandQueue 105
iap10@236 314 #define ReinitAdapHighCommandQueue 107
iap10@236 315 #define ReinitAdapHighRespQueue 108
iap10@236 316 #define ReinitAdapNormRespQueue 109
iap10@236 317 #define InterfaceShutdown 110
iap10@236 318 #define DmaCommandFib 120
iap10@236 319 #define StartProfile 121
iap10@236 320 #define TermProfile 122
iap10@236 321 #define SpeedTest 123
iap10@236 322 #define TakeABreakPt 124
iap10@236 323 #define RequestPerfData 125
iap10@236 324 #define SetInterruptDefTimer 126
iap10@236 325 #define SetInterruptDefCount 127
iap10@236 326 #define GetInterruptDefStatus 128
iap10@236 327 #define LastCommCommand 129
iap10@236 328 /*
iap10@236 329 * Filesystem commands
iap10@236 330 */
iap10@236 331 #define NuFileSystem 300
iap10@236 332 #define UFS 301
iap10@236 333 #define HostFileSystem 302
iap10@236 334 #define LastFileSystemCommand 303
iap10@236 335 /*
iap10@236 336 * Container Commands
iap10@236 337 */
iap10@236 338 #define ContainerCommand 500
iap10@236 339 #define ContainerCommand64 501
iap10@236 340 /*
iap10@236 341 * Cluster Commands
iap10@236 342 */
iap10@236 343 #define ClusterCommand 550
iap10@236 344 /*
iap10@236 345 * Scsi Port commands (scsi passthrough)
iap10@236 346 */
iap10@236 347 #define ScsiPortCommand 600
iap10@236 348 #define ScsiPortCommand64 601
iap10@236 349 /*
iap10@236 350 * Misc house keeping and generic adapter initiated commands
iap10@236 351 */
iap10@236 352 #define AifRequest 700
iap10@236 353 #define CheckRevision 701
iap10@236 354 #define FsaHostShutdown 702
iap10@236 355 #define RequestAdapterInfo 703
iap10@236 356 #define IsAdapterPaused 704
iap10@236 357 #define SendHostTime 705
iap10@236 358 #define LastMiscCommand 706
iap10@236 359
iap10@236 360 //
iap10@236 361 // Commands that will target the failover level on the FSA adapter
iap10@236 362 //
iap10@236 363
iap10@236 364 enum fib_xfer_state {
iap10@236 365 HostOwned = (1<<0),
iap10@236 366 AdapterOwned = (1<<1),
iap10@236 367 FibInitialized = (1<<2),
iap10@236 368 FibEmpty = (1<<3),
iap10@236 369 AllocatedFromPool = (1<<4),
iap10@236 370 SentFromHost = (1<<5),
iap10@236 371 SentFromAdapter = (1<<6),
iap10@236 372 ResponseExpected = (1<<7),
iap10@236 373 NoResponseExpected = (1<<8),
iap10@236 374 AdapterProcessed = (1<<9),
iap10@236 375 HostProcessed = (1<<10),
iap10@236 376 HighPriority = (1<<11),
iap10@236 377 NormalPriority = (1<<12),
iap10@236 378 Async = (1<<13),
iap10@236 379 AsyncIo = (1<<13), // rpbfix: remove with new regime
iap10@236 380 PageFileIo = (1<<14), // rpbfix: remove with new regime
iap10@236 381 ShutdownRequest = (1<<15),
iap10@236 382 LazyWrite = (1<<16), // rpbfix: remove with new regime
iap10@236 383 AdapterMicroFib = (1<<17),
iap10@236 384 BIOSFibPath = (1<<18),
iap10@236 385 FastResponseCapable = (1<<19),
iap10@236 386 ApiFib = (1<<20) // Its an API Fib.
iap10@236 387 };
iap10@236 388
iap10@236 389 /*
iap10@236 390 * The following defines needs to be updated any time there is an
iap10@236 391 * incompatible change made to the aac_init structure.
iap10@236 392 */
iap10@236 393
iap10@236 394 #define ADAPTER_INIT_STRUCT_REVISION 3
iap10@236 395
iap10@236 396 struct aac_init
iap10@236 397 {
iap10@236 398 u32 InitStructRevision;
iap10@236 399 u32 MiniPortRevision;
iap10@236 400 u32 fsrev;
iap10@236 401 u32 CommHeaderAddress;
iap10@236 402 u32 FastIoCommAreaAddress;
iap10@236 403 u32 AdapterFibsPhysicalAddress;
iap10@236 404 u32 AdapterFibsVirtualAddress;
iap10@236 405 u32 AdapterFibsSize;
iap10@236 406 u32 AdapterFibAlign;
iap10@236 407 u32 printfbuf;
iap10@236 408 u32 printfbufsiz;
iap10@236 409 u32 HostPhysMemPages; // number of 4k pages of host physical memory
iap10@236 410 u32 HostElapsedSeconds; // number of seconds since 1970.
iap10@236 411 };
iap10@236 412
iap10@236 413 enum aac_log_level {
iap10@236 414 LOG_INIT = 10,
iap10@236 415 LOG_INFORMATIONAL = 20,
iap10@236 416 LOG_WARNING = 30,
iap10@236 417 LOG_LOW_ERROR = 40,
iap10@236 418 LOG_MEDIUM_ERROR = 50,
iap10@236 419 LOG_HIGH_ERROR = 60,
iap10@236 420 LOG_PANIC = 70,
iap10@236 421 LOG_DEBUG = 80,
iap10@236 422 LOG_WINDBG_PRINT = 90
iap10@236 423 };
iap10@236 424
iap10@236 425 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
iap10@236 426 #define FSAFS_NTC_FIB_CONTEXT 0x030c
iap10@236 427
iap10@236 428 struct aac_dev;
iap10@236 429
iap10@236 430 struct adapter_ops
iap10@236 431 {
iap10@236 432 void (*adapter_interrupt)(struct aac_dev *dev);
iap10@236 433 void (*adapter_notify)(struct aac_dev *dev, u32 event);
iap10@236 434 void (*adapter_enable_int)(struct aac_dev *dev, u32 event);
iap10@236 435 void (*adapter_disable_int)(struct aac_dev *dev, u32 event);
iap10@236 436 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 *status);
iap10@236 437 };
iap10@236 438
iap10@236 439 /*
iap10@236 440 * Define which interrupt handler needs to be installed
iap10@236 441 */
iap10@236 442
iap10@236 443 struct aac_driver_ident
iap10@236 444 {
iap10@236 445 u16 vendor;
iap10@236 446 u16 device;
iap10@236 447 u16 subsystem_vendor;
iap10@236 448 u16 subsystem_device;
iap10@236 449 int (*init)(struct aac_dev *dev, unsigned long num);
iap10@236 450 char * name;
iap10@236 451 char * vname;
iap10@236 452 char * model;
iap10@236 453 u16 channels;
iap10@236 454 };
iap10@236 455
iap10@236 456 /*
iap10@236 457 * The adapter interface specs all queues to be located in the same
iap10@236 458 * physically contigous block. The host structure that defines the
iap10@236 459 * commuication queues will assume they are each a seperate physically
iap10@236 460 * contigous memory region that will support them all being one big
iap10@236 461 * contigous block.
iap10@236 462 * There is a command and response queue for each level and direction of
iap10@236 463 * commuication. These regions are accessed by both the host and adapter.
iap10@236 464 */
iap10@236 465
iap10@236 466 struct aac_queue {
iap10@236 467 u64 logical; /* This is the address we give the adapter */
iap10@236 468 struct aac_entry *base; /* This is the system virtual address */
iap10@236 469 struct aac_qhdr headers; /* A pointer to the producer and consumer queue headers for this queue */
iap10@236 470 u32 entries; /* Number of queue entries on this queue */
iap10@236 471 #if 0
iap10@236 472 wait_queue_head_t qfull; /* Event to wait on if the queue is full */
iap10@236 473 wait_queue_head_t cmdready; /* Indicates there is a Command ready from the adapter on this queue. */
iap10@236 474 #endif
iap10@236 475 /* This is only valid for adapter to host command queues. */
iap10@236 476 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
iap10@236 477 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
iap10@236 478 unsigned long SavedIrql; /* Previous IRQL when the spin lock is taken */
iap10@236 479 u32 padding; /* Padding - FIXME - can remove I believe */
iap10@236 480 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
iap10@236 481 /* only valid for command queues which receive entries from the adapter. */
iap10@236 482 struct list_head pendingq; /* A queue of outstanding fib's to the adapter. */
iap10@236 483 unsigned long numpending; /* Number of entries on outstanding queue. */
iap10@236 484 struct aac_dev * dev; /* Back pointer to adapter structure */
iap10@236 485 };
iap10@236 486
iap10@236 487 /*
iap10@236 488 * Message queues. The order here is important, see also the
iap10@236 489 * queue type ordering
iap10@236 490 */
iap10@236 491
iap10@236 492 struct aac_queue_block
iap10@236 493 {
iap10@236 494 struct aac_queue queue[8];
iap10@236 495 };
iap10@236 496
iap10@236 497 /*
iap10@236 498 * SaP1 Message Unit Registers
iap10@236 499 */
iap10@236 500
iap10@236 501 struct sa_drawbridge_CSR {
iap10@236 502 // Offset | Name
iap10@236 503 u32 reserved[10]; // 00h-27h | Reserved
iap10@236 504 u8 LUT_Offset; // 28h | Looup Table Offset
iap10@236 505 u8 reserved1[3]; // 29h-2bh | Reserved
iap10@236 506 u32 LUT_Data; // 2ch | Looup Table Data
iap10@236 507 u32 reserved2[26]; // 30h-97h | Reserved
iap10@236 508 u16 PRICLEARIRQ; // 98h | Primary Clear Irq
iap10@236 509 u16 SECCLEARIRQ; // 9ah | Secondary Clear Irq
iap10@236 510 u16 PRISETIRQ; // 9ch | Primary Set Irq
iap10@236 511 u16 SECSETIRQ; // 9eh | Secondary Set Irq
iap10@236 512 u16 PRICLEARIRQMASK; // a0h | Primary Clear Irq Mask
iap10@236 513 u16 SECCLEARIRQMASK; // a2h | Secondary Clear Irq Mask
iap10@236 514 u16 PRISETIRQMASK; // a4h | Primary Set Irq Mask
iap10@236 515 u16 SECSETIRQMASK; // a6h | Secondary Set Irq Mask
iap10@236 516 u32 MAILBOX0; // a8h | Scratchpad 0
iap10@236 517 u32 MAILBOX1; // ach | Scratchpad 1
iap10@236 518 u32 MAILBOX2; // b0h | Scratchpad 2
iap10@236 519 u32 MAILBOX3; // b4h | Scratchpad 3
iap10@236 520 u32 MAILBOX4; // b8h | Scratchpad 4
iap10@236 521 u32 MAILBOX5; // bch | Scratchpad 5
iap10@236 522 u32 MAILBOX6; // c0h | Scratchpad 6
iap10@236 523 u32 MAILBOX7; // c4h | Scratchpad 7
iap10@236 524
iap10@236 525 u32 ROM_Setup_Data; // c8h | Rom Setup and Data
iap10@236 526 u32 ROM_Control_Addr; // cch | Rom Control and Address
iap10@236 527
iap10@236 528 u32 reserved3[12]; // d0h-ffh | reserved
iap10@236 529 u32 LUT[64]; // 100h-1ffh| Lookup Table Entries
iap10@236 530
iap10@236 531 //
iap10@236 532 // TO DO
iap10@236 533 // need to add DMA, I2O, UART, etc registers form 80h to 364h
iap10@236 534 //
iap10@236 535
iap10@236 536 };
iap10@236 537
iap10@236 538 #define Mailbox0 SaDbCSR.MAILBOX0
iap10@236 539 #define Mailbox1 SaDbCSR.MAILBOX1
iap10@236 540 #define Mailbox2 SaDbCSR.MAILBOX2
iap10@236 541 #define Mailbox3 SaDbCSR.MAILBOX3
iap10@236 542 #define Mailbox4 SaDbCSR.MAILBOX4
iap10@236 543 #define Mailbox5 SaDbCSR.MAILBOX5
iap10@236 544 #define Mailbox7 SaDbCSR.MAILBOX7
iap10@236 545
iap10@236 546 #define DoorbellReg_p SaDbCSR.PRISETIRQ
iap10@236 547 #define DoorbellReg_s SaDbCSR.SECSETIRQ
iap10@236 548 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
iap10@236 549
iap10@236 550
iap10@236 551 #define DOORBELL_0 cpu_to_le16(0x0001)
iap10@236 552 #define DOORBELL_1 cpu_to_le16(0x0002)
iap10@236 553 #define DOORBELL_2 cpu_to_le16(0x0004)
iap10@236 554 #define DOORBELL_3 cpu_to_le16(0x0008)
iap10@236 555 #define DOORBELL_4 cpu_to_le16(0x0010)
iap10@236 556 #define DOORBELL_5 cpu_to_le16(0x0020)
iap10@236 557 #define DOORBELL_6 cpu_to_le16(0x0040)
iap10@236 558
iap10@236 559
iap10@236 560 #define PrintfReady DOORBELL_5
iap10@236 561 #define PrintfDone DOORBELL_5
iap10@236 562
iap10@236 563 struct sa_registers {
iap10@236 564 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
iap10@236 565 };
iap10@236 566
iap10@236 567
iap10@236 568 #define Sa_MINIPORT_REVISION 1
iap10@236 569
iap10@236 570 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
iap10@236 571 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
iap10@236 572 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
iap10@236 573 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
iap10@236 574
iap10@236 575 /*
iap10@236 576 * Rx Message Unit Registers
iap10@236 577 */
iap10@236 578
iap10@236 579 struct rx_mu_registers {
iap10@236 580 // Local | PCI* | Name
iap10@236 581 // | |
iap10@236 582 u32 ARSR; // 1300h | 00h | APIC Register Select Register
iap10@236 583 u32 reserved0; // 1304h | 04h | Reserved
iap10@236 584 u32 AWR; // 1308h | 08h | APIC Window Register
iap10@236 585 u32 reserved1; // 130Ch | 0Ch | Reserved
iap10@236 586 u32 IMRx[2]; // 1310h | 10h | Inbound Message Registers
iap10@236 587 u32 OMRx[2]; // 1318h | 18h | Outbound Message Registers
iap10@236 588 u32 IDR; // 1320h | 20h | Inbound Doorbell Register
iap10@236 589 u32 IISR; // 1324h | 24h | Inbound Interrupt Status Register
iap10@236 590 u32 IIMR; // 1328h | 28h | Inbound Interrupt Mask Register
iap10@236 591 u32 ODR; // 132Ch | 2Ch | Outbound Doorbell Register
iap10@236 592 u32 OISR; // 1330h | 30h | Outbound Interrupt Status Register
iap10@236 593 u32 OIMR; // 1334h | 34h | Outbound Interrupt Mask Register
iap10@236 594 // * Must access through ATU Inbound Translation Window
iap10@236 595 };
iap10@236 596
iap10@236 597 struct rx_inbound {
iap10@236 598 u32 Mailbox[8];
iap10@236 599 };
iap10@236 600
iap10@236 601 #define InboundMailbox0 IndexRegs.Mailbox[0]
iap10@236 602 #define InboundMailbox1 IndexRegs.Mailbox[1]
iap10@236 603 #define InboundMailbox2 IndexRegs.Mailbox[2]
iap10@236 604 #define InboundMailbox3 IndexRegs.Mailbox[3]
iap10@236 605 #define InboundMailbox4 IndexRegs.Mailbox[4]
iap10@236 606
iap10@236 607 #define INBOUNDDOORBELL_0 cpu_to_le32(0x00000001)
iap10@236 608 #define INBOUNDDOORBELL_1 cpu_to_le32(0x00000002)
iap10@236 609 #define INBOUNDDOORBELL_2 cpu_to_le32(0x00000004)
iap10@236 610 #define INBOUNDDOORBELL_3 cpu_to_le32(0x00000008)
iap10@236 611 #define INBOUNDDOORBELL_4 cpu_to_le32(0x00000010)
iap10@236 612 #define INBOUNDDOORBELL_5 cpu_to_le32(0x00000020)
iap10@236 613 #define INBOUNDDOORBELL_6 cpu_to_le32(0x00000040)
iap10@236 614
iap10@236 615 #define OUTBOUNDDOORBELL_0 cpu_to_le32(0x00000001)
iap10@236 616 #define OUTBOUNDDOORBELL_1 cpu_to_le32(0x00000002)
iap10@236 617 #define OUTBOUNDDOORBELL_2 cpu_to_le32(0x00000004)
iap10@236 618 #define OUTBOUNDDOORBELL_3 cpu_to_le32(0x00000008)
iap10@236 619 #define OUTBOUNDDOORBELL_4 cpu_to_le32(0x00000010)
iap10@236 620
iap10@236 621 #define InboundDoorbellReg MUnit.IDR
iap10@236 622 #define OutboundDoorbellReg MUnit.ODR
iap10@236 623
iap10@236 624 struct rx_registers {
iap10@236 625 struct rx_mu_registers MUnit; // 1300h - 1334h
iap10@236 626 u32 reserved1[6]; // 1338h - 134ch
iap10@236 627 struct rx_inbound IndexRegs;
iap10@236 628 };
iap10@236 629
iap10@236 630 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
iap10@236 631 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
iap10@236 632 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
iap10@236 633 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
iap10@236 634
iap10@236 635 struct fib;
iap10@236 636
iap10@236 637 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
iap10@236 638
iap10@236 639 struct aac_fib_context {
iap10@236 640 s16 type; // used for verification of structure
iap10@236 641 s16 size;
iap10@236 642 ulong jiffies; // used for cleanup - dmb changed to ulong
iap10@236 643 struct list_head next; // used to link context's into a linked list
iap10@236 644 #if 0
iap10@236 645 struct semaphore wait_sem; // this is used to wait for the next fib to arrive.
iap10@236 646 #endif
iap10@236 647 int wait; // Set to true when thread is in WaitForSingleObject
iap10@236 648 unsigned long count; // total number of FIBs on FibList
iap10@236 649 struct list_head fibs;
iap10@236 650 };
iap10@236 651
iap10@236 652 struct fsa_scsi_hba {
iap10@236 653 u32 size[MAXIMUM_NUM_CONTAINERS];
iap10@236 654 u32 type[MAXIMUM_NUM_CONTAINERS];
iap10@236 655 u8 valid[MAXIMUM_NUM_CONTAINERS];
iap10@236 656 u8 ro[MAXIMUM_NUM_CONTAINERS];
iap10@236 657 u8 locked[MAXIMUM_NUM_CONTAINERS];
iap10@236 658 u8 deleted[MAXIMUM_NUM_CONTAINERS];
iap10@236 659 u32 devno[MAXIMUM_NUM_CONTAINERS];
iap10@236 660 };
iap10@236 661
iap10@236 662 struct fib {
iap10@236 663 void *next; /* this is used by the allocator */
iap10@236 664 s16 type;
iap10@236 665 s16 size;
iap10@236 666 /*
iap10@236 667 * The Adapter that this I/O is destined for.
iap10@236 668 */
iap10@236 669 struct aac_dev *dev;
iap10@236 670 u64 logicaladdr; /* 64 bit */
iap10@236 671 #if 0
iap10@236 672 /*
iap10@236 673 * This is the event the sendfib routine will wait on if the
iap10@236 674 * caller did not pass one and this is synch io.
iap10@236 675 */
iap10@236 676 struct semaphore event_wait;
iap10@236 677 #endif
iap10@236 678 spinlock_t event_lock;
iap10@236 679
iap10@236 680 u32 done; /* gets set to 1 when fib is complete */
iap10@236 681 fib_callback callback;
iap10@236 682 void *callback_data;
iap10@236 683 u32 flags; // u32 dmb was ulong
iap10@236 684 /*
iap10@236 685 * The following is used to put this fib context onto the
iap10@236 686 * Outstanding I/O queue.
iap10@236 687 */
iap10@236 688 struct list_head queue;
iap10@236 689
iap10@236 690 void *data;
iap10@236 691 struct hw_fib *fib; /* Actual shared object */
iap10@236 692 };
iap10@236 693
iap10@236 694 /*
iap10@236 695 * Adapter Information Block
iap10@236 696 *
iap10@236 697 * This is returned by the RequestAdapterInfo block
iap10@236 698 */
iap10@236 699
iap10@236 700 struct aac_adapter_info
iap10@236 701 {
iap10@236 702 u32 platform;
iap10@236 703 u32 cpu;
iap10@236 704 u32 subcpu;
iap10@236 705 u32 clock;
iap10@236 706 u32 execmem;
iap10@236 707 u32 buffermem;
iap10@236 708 u32 totalmem;
iap10@236 709 u32 kernelrev;
iap10@236 710 u32 kernelbuild;
iap10@236 711 u32 monitorrev;
iap10@236 712 u32 monitorbuild;
iap10@236 713 u32 hwrev;
iap10@236 714 u32 hwbuild;
iap10@236 715 u32 biosrev;
iap10@236 716 u32 biosbuild;
iap10@236 717 u32 cluster;
iap10@236 718 u32 serial[2];
iap10@236 719 u32 battery;
iap10@236 720 u32 options;
iap10@236 721 u32 OEM;
iap10@236 722 };
iap10@236 723
iap10@236 724 /*
iap10@236 725 * Battery platforms
iap10@236 726 */
iap10@236 727 #define AAC_BAT_REQ_PRESENT (1)
iap10@236 728 #define AAC_BAT_REQ_NOTPRESENT (2)
iap10@236 729 #define AAC_BAT_OPT_PRESENT (3)
iap10@236 730 #define AAC_BAT_OPT_NOTPRESENT (4)
iap10@236 731 #define AAC_BAT_NOT_SUPPORTED (5)
iap10@236 732 /*
iap10@236 733 * cpu types
iap10@236 734 */
iap10@236 735 #define AAC_CPU_SIMULATOR (1)
iap10@236 736 #define AAC_CPU_I960 (2)
iap10@236 737 #define AAC_CPU_STRONGARM (3)
iap10@236 738
iap10@236 739 /*
iap10@236 740 * Supported Options
iap10@236 741 */
iap10@236 742 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
iap10@236 743 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
iap10@236 744 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
iap10@236 745 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
iap10@236 746 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
iap10@236 747 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
iap10@236 748 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
iap10@236 749 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
iap10@236 750 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
iap10@236 751 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
iap10@236 752 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
iap10@236 753 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
iap10@236 754 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
iap10@236 755
iap10@236 756 struct aac_dev
iap10@236 757 {
iap10@236 758 struct aac_dev *next;
iap10@236 759 const char *name;
iap10@236 760 int id;
iap10@236 761
iap10@236 762 u16 irq_mask;
iap10@236 763 /*
iap10@236 764 * Map for 128 fib objects (64k)
iap10@236 765 */
iap10@236 766 dma_addr_t hw_fib_pa;
iap10@236 767 struct hw_fib *hw_fib_va;
iap10@236 768 #if BITS_PER_LONG >= 64
iap10@236 769 ulong fib_base_va;
iap10@236 770 #endif
iap10@236 771 /*
iap10@236 772 * Fib Headers
iap10@236 773 */
iap10@236 774 struct fib fibs[AAC_NUM_FIB];
iap10@236 775 struct fib *free_fib;
iap10@236 776 struct fib *timeout_fib;
iap10@236 777 spinlock_t fib_lock;
iap10@236 778
iap10@236 779 struct aac_queue_block *queues;
iap10@236 780 /*
iap10@236 781 * The user API will use an IOCTL to register itself to receive
iap10@236 782 * FIBs from the adapter. The following list is used to keep
iap10@236 783 * track of all the threads that have requested these FIBs. The
iap10@236 784 * mutex is used to synchronize access to all data associated
iap10@236 785 * with the adapter fibs.
iap10@236 786 */
iap10@236 787 struct list_head fib_list;
iap10@236 788
iap10@236 789 struct adapter_ops a_ops;
iap10@236 790 unsigned long fsrev; /* Main driver's revision number */
iap10@236 791
iap10@236 792 struct aac_init *init; /* Holds initialization info to communicate with adapter */
iap10@236 793 dma_addr_t init_pa; /* Holds physical address of the init struct */
iap10@236 794
iap10@236 795 struct pci_dev *pdev; /* Our PCI interface */
iap10@236 796 void * printfbuf; /* pointer to buffer used for printf's from the adapter */
iap10@236 797 void * comm_addr; /* Base address of Comm area */
iap10@236 798 dma_addr_t comm_phys; /* Physical Address of Comm area */
iap10@236 799 size_t comm_size;
iap10@236 800
iap10@236 801 struct Scsi_Host *scsi_host_ptr;
iap10@236 802 struct fsa_scsi_hba fsa_dev;
iap10@236 803 int thread_pid;
iap10@236 804 int cardtype;
iap10@236 805
iap10@236 806 /*
iap10@236 807 * The following is the device specific extension.
iap10@236 808 */
iap10@236 809 union
iap10@236 810 {
iap10@236 811 struct sa_registers *sa;
iap10@236 812 struct rx_registers *rx;
iap10@236 813 } regs;
iap10@236 814 /*
iap10@236 815 * The following is the number of the individual adapter
iap10@236 816 */
iap10@236 817 u32 devnum;
iap10@236 818 u32 aif_thread;
iap10@236 819 #if 0
iap10@236 820 struct completion aif_completion;
iap10@236 821 #endif
iap10@236 822 struct aac_adapter_info adapter_info;
iap10@236 823 /* These are in adapter info but they are in the io flow so
iap10@236 824 * lets break them out so we don't have to do an AND to check them
iap10@236 825 */
iap10@236 826 u8 nondasd_support;
iap10@236 827 u8 pae_support;
iap10@236 828 };
iap10@236 829
iap10@236 830 #define aac_adapter_interrupt(dev) \
iap10@236 831 dev->a_ops.adapter_interrupt(dev)
iap10@236 832
iap10@236 833 #define aac_adapter_notify(dev, event) \
iap10@236 834 dev->a_ops.adapter_notify(dev, event)
iap10@236 835
iap10@236 836 #define aac_adapter_enable_int(dev, event) \
iap10@236 837 dev->a_ops.adapter_enable_int(dev, event)
iap10@236 838
iap10@236 839 #define aac_adapter_disable_int(dev, event) \
iap10@236 840 dev->a_ops.adapter_disable_int(dev, event)
iap10@236 841
iap10@236 842
iap10@236 843
iap10@236 844 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
iap10@236 845
iap10@236 846 /*
iap10@236 847 * Define the command values
iap10@236 848 */
iap10@236 849
iap10@236 850 #define Null 0
iap10@236 851 #define GetAttributes 1
iap10@236 852 #define SetAttributes 2
iap10@236 853 #define Lookup 3
iap10@236 854 #define ReadLink 4
iap10@236 855 #define Read 5
iap10@236 856 #define Write 6
iap10@236 857 #define Create 7
iap10@236 858 #define MakeDirectory 8
iap10@236 859 #define SymbolicLink 9
iap10@236 860 #define MakeNode 10
iap10@236 861 #define Removex 11
iap10@236 862 #define RemoveDirectoryx 12
iap10@236 863 #define Rename 13
iap10@236 864 #define Link 14
iap10@236 865 #define ReadDirectory 15
iap10@236 866 #define ReadDirectoryPlus 16
iap10@236 867 #define FileSystemStatus 17
iap10@236 868 #define FileSystemInfo 18
iap10@236 869 #define PathConfigure 19
iap10@236 870 #define Commit 20
iap10@236 871 #define Mount 21
iap10@236 872 #define UnMount 22
iap10@236 873 #define Newfs 23
iap10@236 874 #define FsCheck 24
iap10@236 875 #define FsSync 25
iap10@236 876 #define SimReadWrite 26
iap10@236 877 #define SetFileSystemStatus 27
iap10@236 878 #define BlockRead 28
iap10@236 879 #define BlockWrite 29
iap10@236 880 #define NvramIoctl 30
iap10@236 881 #define FsSyncWait 31
iap10@236 882 #define ClearArchiveBit 32
iap10@236 883 #define SetAcl 33
iap10@236 884 #define GetAcl 34
iap10@236 885 #define AssignAcl 35
iap10@236 886 #define FaultInsertion 36 /* Fault Insertion Command */
iap10@236 887 #define CrazyCache 37 /* Crazycache */
iap10@236 888
iap10@236 889 #define MAX_FSACOMMAND_NUM 38
iap10@236 890
iap10@236 891
iap10@236 892 /*
iap10@236 893 * Define the status returns. These are very unixlike although
iap10@236 894 * most are not in fact used
iap10@236 895 */
iap10@236 896
iap10@236 897 #define ST_OK 0
iap10@236 898 #define ST_PERM 1
iap10@236 899 #define ST_NOENT 2
iap10@236 900 #define ST_IO 5
iap10@236 901 #define ST_NXIO 6
iap10@236 902 #define ST_E2BIG 7
iap10@236 903 #define ST_ACCES 13
iap10@236 904 #define ST_EXIST 17
iap10@236 905 #define ST_XDEV 18
iap10@236 906 #define ST_NODEV 19
iap10@236 907 #define ST_NOTDIR 20
iap10@236 908 #define ST_ISDIR 21
iap10@236 909 #define ST_INVAL 22
iap10@236 910 #define ST_FBIG 27
iap10@236 911 #define ST_NOSPC 28
iap10@236 912 #define ST_ROFS 30
iap10@236 913 #define ST_MLINK 31
iap10@236 914 #define ST_WOULDBLOCK 35
iap10@236 915 #define ST_NAMETOOLONG 63
iap10@236 916 #define ST_NOTEMPTY 66
iap10@236 917 #define ST_DQUOT 69
iap10@236 918 #define ST_STALE 70
iap10@236 919 #define ST_REMOTE 71
iap10@236 920 #define ST_BADHANDLE 10001
iap10@236 921 #define ST_NOT_SYNC 10002
iap10@236 922 #define ST_BAD_COOKIE 10003
iap10@236 923 #define ST_NOTSUPP 10004
iap10@236 924 #define ST_TOOSMALL 10005
iap10@236 925 #define ST_SERVERFAULT 10006
iap10@236 926 #define ST_BADTYPE 10007
iap10@236 927 #define ST_JUKEBOX 10008
iap10@236 928 #define ST_NOTMOUNTED 10009
iap10@236 929 #define ST_MAINTMODE 10010
iap10@236 930 #define ST_STALEACL 10011
iap10@236 931
iap10@236 932 /*
iap10@236 933 * On writes how does the client want the data written.
iap10@236 934 */
iap10@236 935
iap10@236 936 #define CACHE_CSTABLE 1
iap10@236 937 #define CACHE_UNSTABLE 2
iap10@236 938
iap10@236 939 /*
iap10@236 940 * Lets the client know at which level the data was commited on
iap10@236 941 * a write request
iap10@236 942 */
iap10@236 943
iap10@236 944 #define CMFILE_SYNCH_NVRAM 1
iap10@236 945 #define CMDATA_SYNCH_NVRAM 2
iap10@236 946 #define CMFILE_SYNCH 3
iap10@236 947 #define CMDATA_SYNCH 4
iap10@236 948 #define CMUNSTABLE 5
iap10@236 949
iap10@236 950 struct aac_read
iap10@236 951 {
iap10@236 952 u32 command;
iap10@236 953 u32 cid;
iap10@236 954 u32 block;
iap10@236 955 u32 count;
iap10@236 956 struct sgmap sg; // Must be last in struct because it is variable
iap10@236 957 };
iap10@236 958
iap10@236 959 struct aac_read64
iap10@236 960 {
iap10@236 961 u32 command;
iap10@236 962 u16 cid;
iap10@236 963 u16 sector_count;
iap10@236 964 u32 block;
iap10@236 965 u16 pad;
iap10@236 966 u16 flags;
iap10@236 967 struct sgmap64 sg; // Must be last in struct because it is variable
iap10@236 968 };
iap10@236 969
iap10@236 970 struct aac_read_reply
iap10@236 971 {
iap10@236 972 u32 status;
iap10@236 973 u32 count;
iap10@236 974 };
iap10@236 975
iap10@236 976 struct aac_write
iap10@236 977 {
iap10@236 978 u32 command;
iap10@236 979 u32 cid;
iap10@236 980 u32 block;
iap10@236 981 u32 count;
iap10@236 982 u32 stable; // Not used
iap10@236 983 struct sgmap sg; // Must be last in struct because it is variable
iap10@236 984 };
iap10@236 985
iap10@236 986 struct aac_write64
iap10@236 987 {
iap10@236 988 u32 command;
iap10@236 989 u16 cid;
iap10@236 990 u16 sector_count;
iap10@236 991 u32 block;
iap10@236 992 u16 pad;
iap10@236 993 u16 flags;
iap10@236 994 struct sgmap64 sg; // Must be last in struct because it is variable
iap10@236 995 };
iap10@236 996 struct aac_write_reply
iap10@236 997 {
iap10@236 998 u32 status;
iap10@236 999 u32 count;
iap10@236 1000 u32 committed;
iap10@236 1001 };
iap10@236 1002
iap10@236 1003 struct aac_srb
iap10@236 1004 {
iap10@236 1005 u32 function;
iap10@236 1006 u32 channel;
iap10@236 1007 u32 target;
iap10@236 1008 u32 lun;
iap10@236 1009 u32 timeout;
iap10@236 1010 u32 flags;
iap10@236 1011 u32 count; // Data xfer size
iap10@236 1012 u32 retry_limit;
iap10@236 1013 u32 cdb_size;
iap10@236 1014 u8 cdb[16];
iap10@236 1015 struct sgmap sg;
iap10@236 1016 };
iap10@236 1017
iap10@236 1018
iap10@236 1019
iap10@236 1020 #define AAC_SENSE_BUFFERSIZE 30
iap10@236 1021
iap10@236 1022 struct aac_srb_reply
iap10@236 1023 {
iap10@236 1024 u32 status;
iap10@236 1025 u32 srb_status;
iap10@236 1026 u32 scsi_status;
iap10@236 1027 u32 data_xfer_length;
iap10@236 1028 u32 sense_data_size;
iap10@236 1029 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
iap10@236 1030 };
iap10@236 1031 /*
iap10@236 1032 * SRB Flags
iap10@236 1033 */
iap10@236 1034 #define SRB_NoDataXfer 0x0000
iap10@236 1035 #define SRB_DisableDisconnect 0x0004
iap10@236 1036 #define SRB_DisableSynchTransfer 0x0008
iap10@236 1037 #define SRB_BypassFrozenQueue 0x0010
iap10@236 1038 #define SRB_DisableAutosense 0x0020
iap10@236 1039 #define SRB_DataIn 0x0040
iap10@236 1040 #define SRB_DataOut 0x0080
iap10@236 1041
iap10@236 1042 /*
iap10@236 1043 * SRB Functions - set in aac_srb->function
iap10@236 1044 */
iap10@236 1045 #define SRBF_ExecuteScsi 0x0000
iap10@236 1046 #define SRBF_ClaimDevice 0x0001
iap10@236 1047 #define SRBF_IO_Control 0x0002
iap10@236 1048 #define SRBF_ReceiveEvent 0x0003
iap10@236 1049 #define SRBF_ReleaseQueue 0x0004
iap10@236 1050 #define SRBF_AttachDevice 0x0005
iap10@236 1051 #define SRBF_ReleaseDevice 0x0006
iap10@236 1052 #define SRBF_Shutdown 0x0007
iap10@236 1053 #define SRBF_Flush 0x0008
iap10@236 1054 #define SRBF_AbortCommand 0x0010
iap10@236 1055 #define SRBF_ReleaseRecovery 0x0011
iap10@236 1056 #define SRBF_ResetBus 0x0012
iap10@236 1057 #define SRBF_ResetDevice 0x0013
iap10@236 1058 #define SRBF_TerminateIO 0x0014
iap10@236 1059 #define SRBF_FlushQueue 0x0015
iap10@236 1060 #define SRBF_RemoveDevice 0x0016
iap10@236 1061 #define SRBF_DomainValidation 0x0017
iap10@236 1062
iap10@236 1063 /*
iap10@236 1064 * SRB SCSI Status - set in aac_srb->scsi_status
iap10@236 1065 */
iap10@236 1066 #define SRB_STATUS_PENDING 0x00
iap10@236 1067 #define SRB_STATUS_SUCCESS 0x01
iap10@236 1068 #define SRB_STATUS_ABORTED 0x02
iap10@236 1069 #define SRB_STATUS_ABORT_FAILED 0x03
iap10@236 1070 #define SRB_STATUS_ERROR 0x04
iap10@236 1071 #define SRB_STATUS_BUSY 0x05
iap10@236 1072 #define SRB_STATUS_INVALID_REQUEST 0x06
iap10@236 1073 #define SRB_STATUS_INVALID_PATH_ID 0x07
iap10@236 1074 #define SRB_STATUS_NO_DEVICE 0x08
iap10@236 1075 #define SRB_STATUS_TIMEOUT 0x09
iap10@236 1076 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
iap10@236 1077 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
iap10@236 1078 #define SRB_STATUS_MESSAGE_REJECTED 0x0D
iap10@236 1079 #define SRB_STATUS_BUS_RESET 0x0E
iap10@236 1080 #define SRB_STATUS_PARITY_ERROR 0x0F
iap10@236 1081 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
iap10@236 1082 #define SRB_STATUS_NO_HBA 0x11
iap10@236 1083 #define SRB_STATUS_DATA_OVERRUN 0x12
iap10@236 1084 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
iap10@236 1085 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
iap10@236 1086 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
iap10@236 1087 #define SRB_STATUS_REQUEST_FLUSHED 0x16
iap10@236 1088 #define SRB_STATUS_DELAYED_RETRY 0x17
iap10@236 1089 #define SRB_STATUS_INVALID_LUN 0x20
iap10@236 1090 #define SRB_STATUS_INVALID_TARGET_ID 0x21
iap10@236 1091 #define SRB_STATUS_BAD_FUNCTION 0x22
iap10@236 1092 #define SRB_STATUS_ERROR_RECOVERY 0x23
iap10@236 1093 #define SRB_STATUS_NOT_STARTED 0x24
iap10@236 1094 #define SRB_STATUS_NOT_IN_USE 0x30
iap10@236 1095 #define SRB_STATUS_FORCE_ABORT 0x31
iap10@236 1096 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
iap10@236 1097
iap10@236 1098 /*
iap10@236 1099 * Object-Server / Volume-Manager Dispatch Classes
iap10@236 1100 */
iap10@236 1101
iap10@236 1102 #define VM_Null 0
iap10@236 1103 #define VM_NameServe 1
iap10@236 1104 #define VM_ContainerConfig 2
iap10@236 1105 #define VM_Ioctl 3
iap10@236 1106 #define VM_FilesystemIoctl 4
iap10@236 1107 #define VM_CloseAll 5
iap10@236 1108 #define VM_CtBlockRead 6
iap10@236 1109 #define VM_CtBlockWrite 7
iap10@236 1110 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
iap10@236 1111 #define VM_SliceBlockWrite 9
iap10@236 1112 #define VM_DriveBlockRead 10 /* raw access to physical devices */
iap10@236 1113 #define VM_DriveBlockWrite 11
iap10@236 1114 #define VM_EnclosureMgt 12 /* enclosure management */
iap10@236 1115 #define VM_Unused 13 /* used to be diskset management */
iap10@236 1116 #define VM_CtBlockVerify 14
iap10@236 1117 #define VM_CtPerf 15 /* performance test */
iap10@236 1118 #define VM_CtBlockRead64 16
iap10@236 1119 #define VM_CtBlockWrite64 17
iap10@236 1120 #define VM_CtBlockVerify64 18
iap10@236 1121 #define VM_CtHostRead64 19
iap10@236 1122 #define VM_CtHostWrite64 20
iap10@236 1123
iap10@236 1124 #define MAX_VMCOMMAND_NUM 21 /* used for sizing stats array - leave last */
iap10@236 1125
iap10@236 1126 /*
iap10@236 1127 * Descriptive information (eg, vital stats)
iap10@236 1128 * that a content manager might report. The
iap10@236 1129 * FileArray filesystem component is one example
iap10@236 1130 * of a content manager. Raw mode might be
iap10@236 1131 * another.
iap10@236 1132 */
iap10@236 1133
iap10@236 1134 struct aac_fsinfo {
iap10@236 1135 u32 fsTotalSize; /* Consumed by fs, incl. metadata */
iap10@236 1136 u32 fsBlockSize;
iap10@236 1137 u32 fsFragSize;
iap10@236 1138 u32 fsMaxExtendSize;
iap10@236 1139 u32 fsSpaceUnits;
iap10@236 1140 u32 fsMaxNumFiles;
iap10@236 1141 u32 fsNumFreeFiles;
iap10@236 1142 u32 fsInodeDensity;
iap10@236 1143 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
iap10@236 1144
iap10@236 1145 union aac_contentinfo {
iap10@236 1146 struct aac_fsinfo filesys; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
iap10@236 1147 };
iap10@236 1148
iap10@236 1149 /*
iap10@236 1150 * Query for "mountable" objects, ie, objects that are typically
iap10@236 1151 * associated with a drive letter on the client (host) side.
iap10@236 1152 */
iap10@236 1153
iap10@236 1154 struct aac_mntent {
iap10@236 1155 u32 oid;
iap10@236 1156 u8 name[16]; // if applicable
iap10@236 1157 struct creation_info create_info; // if applicable
iap10@236 1158 u32 capacity;
iap10@236 1159 u32 vol; // substrate structure
iap10@236 1160 u32 obj; // FT_FILESYS, FT_DATABASE, etc.
iap10@236 1161 u32 state; // unready for mounting, readonly, etc.
iap10@236 1162 union aac_contentinfo fileinfo; // Info specific to content manager (eg, filesystem)
iap10@236 1163 u32 altoid; // != oid <==> snapshot or broken mirror exists
iap10@236 1164 };
iap10@236 1165
iap10@236 1166 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
iap10@236 1167
iap10@236 1168 struct aac_query_mount {
iap10@236 1169 u32 command;
iap10@236 1170 u32 type;
iap10@236 1171 u32 count;
iap10@236 1172 };
iap10@236 1173
iap10@236 1174 struct aac_mount {
iap10@236 1175 u32 status;
iap10@236 1176 u32 type; /* should be same as that requested */
iap10@236 1177 u32 count;
iap10@236 1178 struct aac_mntent mnt[1];
iap10@236 1179 };
iap10@236 1180
iap10@236 1181 /*
iap10@236 1182 * The following command is sent to shut down each container.
iap10@236 1183 */
iap10@236 1184
iap10@236 1185 struct aac_close {
iap10@236 1186 u32 command;
iap10@236 1187 u32 cid;
iap10@236 1188 };
iap10@236 1189
iap10@236 1190 struct aac_query_disk
iap10@236 1191 {
iap10@236 1192 s32 cnum;
iap10@236 1193 s32 bus;
iap10@236 1194 s32 target;
iap10@236 1195 s32 lun;
iap10@236 1196 u32 valid;
iap10@236 1197 u32 locked;
iap10@236 1198 u32 deleted;
iap10@236 1199 s32 instance;
iap10@236 1200 s8 name[10];
iap10@236 1201 u32 unmapped;
iap10@236 1202 };
iap10@236 1203
iap10@236 1204 struct aac_delete_disk {
iap10@236 1205 u32 disknum;
iap10@236 1206 u32 cnum;
iap10@236 1207 };
iap10@236 1208
iap10@236 1209 struct fib_ioctl
iap10@236 1210 {
iap10@236 1211 char *fibctx;
iap10@236 1212 int wait;
iap10@236 1213 char *fib;
iap10@236 1214 };
iap10@236 1215
iap10@236 1216 struct revision
iap10@236 1217 {
iap10@236 1218 u32 compat;
iap10@236 1219 u32 version;
iap10@236 1220 u32 build;
iap10@236 1221 };
iap10@236 1222
iap10@236 1223 /*
iap10@236 1224 * Ugly - non Linux like ioctl coding for back compat.
iap10@236 1225 */
iap10@236 1226
iap10@236 1227 #define CTL_CODE(function, method) ( \
iap10@236 1228 (4<< 16) | ((function) << 2) | (method) \
iap10@236 1229 )
iap10@236 1230
iap10@236 1231 /*
iap10@236 1232 * Define the method codes for how buffers are passed for I/O and FS
iap10@236 1233 * controls
iap10@236 1234 */
iap10@236 1235
iap10@236 1236 #define METHOD_BUFFERED 0
iap10@236 1237 #define METHOD_NEITHER 3
iap10@236 1238
iap10@236 1239 /*
iap10@236 1240 * Filesystem ioctls
iap10@236 1241 */
iap10@236 1242
iap10@236 1243 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
iap10@236 1244 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
iap10@236 1245 #define FSACTL_DELETE_DISK 0x163
iap10@236 1246 #define FSACTL_QUERY_DISK 0x173
iap10@236 1247 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
iap10@236 1248 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
iap10@236 1249 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
iap10@236 1250 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
iap10@236 1251 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
iap10@236 1252 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
iap10@236 1253
iap10@236 1254
iap10@236 1255 struct aac_common
iap10@236 1256 {
iap10@236 1257 /*
iap10@236 1258 * If this value is set to 1 then interrupt moderation will occur
iap10@236 1259 * in the base commuication support.
iap10@236 1260 */
iap10@236 1261 u32 irq_mod;
iap10@236 1262 u32 peak_fibs;
iap10@236 1263 u32 zero_fibs;
iap10@236 1264 u32 fib_timeouts;
iap10@236 1265 /*
iap10@236 1266 * Statistical counters in debug mode
iap10@236 1267 */
iap10@236 1268 #ifdef DBG
iap10@236 1269 u32 FibsSent;
iap10@236 1270 u32 FibRecved;
iap10@236 1271 u32 NoResponseSent;
iap10@236 1272 u32 NoResponseRecved;
iap10@236 1273 u32 AsyncSent;
iap10@236 1274 u32 AsyncRecved;
iap10@236 1275 u32 NormalSent;
iap10@236 1276 u32 NormalRecved;
iap10@236 1277 #endif
iap10@236 1278 };
iap10@236 1279
iap10@236 1280 extern struct aac_common aac_config;
iap10@236 1281
iap10@236 1282
iap10@236 1283 /*
iap10@236 1284 * The following macro is used when sending and receiving FIBs. It is
iap10@236 1285 * only used for debugging.
iap10@236 1286 */
iap10@236 1287
iap10@236 1288 #if DBG
iap10@236 1289 #define FIB_COUNTER_INCREMENT(counter) (counter)++
iap10@236 1290 #else
iap10@236 1291 #define FIB_COUNTER_INCREMENT(counter)
iap10@236 1292 #endif
iap10@236 1293
iap10@236 1294 /*
iap10@236 1295 * Adapter direct commands
iap10@236 1296 * Monitor/Kernel API
iap10@236 1297 */
iap10@236 1298
iap10@236 1299 #define BREAKPOINT_REQUEST cpu_to_le32(0x00000004)
iap10@236 1300 #define INIT_STRUCT_BASE_ADDRESS cpu_to_le32(0x00000005)
iap10@236 1301 #define READ_PERMANENT_PARAMETERS cpu_to_le32(0x0000000a)
iap10@236 1302 #define WRITE_PERMANENT_PARAMETERS cpu_to_le32(0x0000000b)
iap10@236 1303 #define HOST_CRASHING cpu_to_le32(0x0000000d)
iap10@236 1304 #define SEND_SYNCHRONOUS_FIB cpu_to_le32(0x0000000c)
iap10@236 1305 #define GET_ADAPTER_PROPERTIES cpu_to_le32(0x00000019)
iap10@236 1306 #define RE_INIT_ADAPTER cpu_to_le32(0x000000ee)
iap10@236 1307
iap10@236 1308 /*
iap10@236 1309 * Adapter Status Register
iap10@236 1310 *
iap10@236 1311 * Phase Staus mailbox is 32bits:
iap10@236 1312 * <31:16> = Phase Status
iap10@236 1313 * <15:0> = Phase
iap10@236 1314 *
iap10@236 1315 * The adapter reports is present state through the phase. Only
iap10@236 1316 * a single phase should be ever be set. Each phase can have multiple
iap10@236 1317 * phase status bits to provide more detailed information about the
iap10@236 1318 * state of the board. Care should be taken to ensure that any phase
iap10@236 1319 * status bits that are set when changing the phase are also valid
iap10@236 1320 * for the new phase or be cleared out. Adapter software (monitor,
iap10@236 1321 * iflash, kernel) is responsible for properly maintining the phase
iap10@236 1322 * status mailbox when it is running.
iap10@236 1323 *
iap10@236 1324 * MONKER_API Phases
iap10@236 1325 *
iap10@236 1326 * Phases are bit oriented. It is NOT valid to have multiple bits set
iap10@236 1327 */
iap10@236 1328
iap10@236 1329 #define SELF_TEST_FAILED cpu_to_le32(0x00000004)
iap10@236 1330 #define KERNEL_UP_AND_RUNNING cpu_to_le32(0x00000080)
iap10@236 1331 #define KERNEL_PANIC cpu_to_le32(0x00000100)
iap10@236 1332
iap10@236 1333 /*
iap10@236 1334 * Doorbell bit defines
iap10@236 1335 */
iap10@236 1336
iap10@236 1337 #define DoorBellPrintfDone cpu_to_le32(1<<5) // Host -> Adapter
iap10@236 1338 #define DoorBellAdapterNormCmdReady cpu_to_le32(1<<1) // Adapter -> Host
iap10@236 1339 #define DoorBellAdapterNormRespReady cpu_to_le32(1<<2) // Adapter -> Host
iap10@236 1340 #define DoorBellAdapterNormCmdNotFull cpu_to_le32(1<<3) // Adapter -> Host
iap10@236 1341 #define DoorBellAdapterNormRespNotFull cpu_to_le32(1<<4) // Adapter -> Host
iap10@236 1342 #define DoorBellPrintfReady cpu_to_le32(1<<5) // Adapter -> Host
iap10@236 1343
iap10@236 1344 /*
iap10@236 1345 * For FIB communication, we need all of the following things
iap10@236 1346 * to send back to the user.
iap10@236 1347 */
iap10@236 1348
iap10@236 1349 #define AifCmdEventNotify 1 /* Notify of event */
iap10@236 1350 #define AifCmdJobProgress 2 /* Progress report */
iap10@236 1351 #define AifCmdAPIReport 3 /* Report from other user of API */
iap10@236 1352 #define AifCmdDriverNotify 4 /* Notify host driver of event */
iap10@236 1353 #define AifReqJobList 100 /* Gets back complete job list */
iap10@236 1354 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
iap10@236 1355 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
iap10@236 1356 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
iap10@236 1357 #define AifReqTerminateJob 104 /* Terminates job */
iap10@236 1358 #define AifReqSuspendJob 105 /* Suspends a job */
iap10@236 1359 #define AifReqResumeJob 106 /* Resumes a job */
iap10@236 1360 #define AifReqSendAPIReport 107 /* API generic report requests */
iap10@236 1361 #define AifReqAPIJobStart 108 /* Start a job from the API */
iap10@236 1362 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
iap10@236 1363 #define AifReqAPIJobFinish 110 /* Finish a job from the API */
iap10@236 1364
iap10@236 1365 /*
iap10@236 1366 * Adapter Initiated FIB command structures. Start with the adapter
iap10@236 1367 * initiated FIBs that really come from the adapter, and get responded
iap10@236 1368 * to by the host.
iap10@236 1369 */
iap10@236 1370
iap10@236 1371 struct aac_aifcmd {
iap10@236 1372 u32 command; /* Tell host what type of notify this is */
iap10@236 1373 u32 seqnum; /* To allow ordering of reports (if necessary) */
iap10@236 1374 u8 data[1]; /* Undefined length (from kernel viewpoint) */
iap10@236 1375 };
iap10@236 1376
iap10@236 1377 static inline u32 fib2addr(struct hw_fib *hw)
iap10@236 1378 {
iap10@236 1379 return (u32)hw;
iap10@236 1380 }
iap10@236 1381
iap10@236 1382 static inline struct hw_fib *addr2fib(u32 addr)
iap10@236 1383 {
iap10@236 1384 return (struct hw_fib *)addr;
iap10@236 1385 }
iap10@236 1386
iap10@236 1387 const char *aac_driverinfo(struct Scsi_Host *);
iap10@236 1388 struct fib *fib_alloc(struct aac_dev *dev);
iap10@236 1389 int fib_setup(struct aac_dev *dev);
iap10@236 1390 void fib_map_free(struct aac_dev *dev);
iap10@236 1391 void fib_free(struct fib * context);
iap10@236 1392 void fib_init(struct fib * context);
iap10@236 1393 void fib_dealloc(struct fib * context);
iap10@236 1394 void aac_printf(struct aac_dev *dev, u32 val);
iap10@236 1395 int fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
iap10@236 1396 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
iap10@236 1397 int aac_consumer_avail(struct aac_dev * dev, struct aac_queue * q);
iap10@236 1398 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
iap10@236 1399 int fib_complete(struct fib * context);
iap10@236 1400 #define fib_data(fibctx) ((void *)(fibctx)->fib->data)
iap10@236 1401 int aac_detach(struct aac_dev *dev);
iap10@236 1402 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
iap10@236 1403 int aac_get_containers(struct aac_dev *dev);
iap10@236 1404 int aac_scsi_cmd(Scsi_Cmnd *scsi_cmnd_ptr);
iap10@236 1405 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void *arg);
iap10@236 1406 int aac_do_ioctl(struct aac_dev * dev, int cmd, void *arg);
iap10@236 1407 int aac_rx_init(struct aac_dev *dev, unsigned long devNumber);
iap10@236 1408 int aac_sa_init(struct aac_dev *dev, unsigned long devNumber);
iap10@236 1409 unsigned int aac_response_normal(struct aac_queue * q);
iap10@236 1410 unsigned int aac_command_normal(struct aac_queue * q);
iap10@236 1411 #ifdef TRY_TASKLET
iap10@236 1412 extern struct tasklet_struct aac_command_tasklet;
iap10@236 1413 int aac_command_thread(unsigned long data);
iap10@236 1414 #else
iap10@236 1415 int aac_command_thread(struct aac_dev * dev);
iap10@236 1416 #endif
iap10@236 1417 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
iap10@236 1418 int fib_adapter_complete(struct fib * fibptr, unsigned short size);
iap10@236 1419 struct aac_driver_ident* aac_get_driver_ident(int devtype);
iap10@236 1420 int aac_get_adapter_info(struct aac_dev* dev);