ia64/xen-unstable

annotate xen/include/asm-ia64/xenprocessor.h @ 9756:14a34d811e81

[IA64] introduce P2M conversion

introduce P2M conversion functions necessary for dom0vp model.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@ldap.hp.com
date Tue Apr 25 13:06:57 2006 -0600 (2006-04-25)
parents e45666b8b05f
children 59e05ddfd0ad
rev   line source
adsharma@5046 1 #ifndef _ASM_IA64_XENPROCESSOR_H
adsharma@5046 2 #define _ASM_IA64_XENPROCESSOR_H
adsharma@5046 3 /*
adsharma@5046 4 * xen specific processor definition
adsharma@5046 5 *
adsharma@5046 6 * Copyright (C) 2005 Hewlett-Packard Co.
adsharma@5046 7 * Dan Magenheimer (dan.magenheimer@hp.com)
adsharma@5046 8 *
adsharma@5046 9 * Copyright (C) 2005 Intel Co.
adsharma@5046 10 * Kun Tian (Kevin Tian) <kevin.tian@intel.com>
adsharma@5046 11 *
adsharma@5046 12 */
adsharma@5046 13
adsharma@5046 14
adsharma@5046 15 #define ia64_is_local_fpu_owner(t) 0
adsharma@5046 16
adsharma@5046 17 /* like above but expressed as bitfields for more efficient access: */
adsharma@5046 18 struct ia64_psr {
adsharma@5046 19 __u64 reserved0 : 1;
adsharma@5046 20 __u64 be : 1;
adsharma@5046 21 __u64 up : 1;
adsharma@5046 22 __u64 ac : 1;
adsharma@5046 23 __u64 mfl : 1;
adsharma@5046 24 __u64 mfh : 1;
adsharma@5046 25 __u64 reserved1 : 7;
adsharma@5046 26 __u64 ic : 1;
adsharma@5046 27 __u64 i : 1;
adsharma@5046 28 __u64 pk : 1;
adsharma@5046 29 __u64 reserved2 : 1;
adsharma@5046 30 __u64 dt : 1;
adsharma@5046 31 __u64 dfl : 1;
adsharma@5046 32 __u64 dfh : 1;
adsharma@5046 33 __u64 sp : 1;
adsharma@5046 34 __u64 pp : 1;
adsharma@5046 35 __u64 di : 1;
adsharma@5046 36 __u64 si : 1;
adsharma@5046 37 __u64 db : 1;
adsharma@5046 38 __u64 lp : 1;
adsharma@5046 39 __u64 tb : 1;
adsharma@5046 40 __u64 rt : 1;
adsharma@5046 41 __u64 reserved3 : 4;
adsharma@5046 42 __u64 cpl : 2;
adsharma@5046 43 __u64 is : 1;
adsharma@5046 44 __u64 mc : 1;
adsharma@5046 45 __u64 it : 1;
adsharma@5046 46 __u64 id : 1;
adsharma@5046 47 __u64 da : 1;
adsharma@5046 48 __u64 dd : 1;
adsharma@5046 49 __u64 ss : 1;
adsharma@5046 50 __u64 ri : 2;
adsharma@5046 51 __u64 ed : 1;
adsharma@5046 52 __u64 bn : 1;
adsharma@5046 53 __u64 ia : 1;
adsharma@5046 54 __u64 vm : 1;
adsharma@5046 55 __u64 reserved5 : 17;
adsharma@5046 56 };
adsharma@5046 57
adsharma@5046 58 /* vmx like above but expressed as bitfields for more efficient access: */
adsharma@5046 59 typedef union{
adsharma@5046 60 __u64 val;
adsharma@5046 61 struct{
adsharma@5046 62 __u64 reserved0 : 1;
adsharma@5046 63 __u64 be : 1;
adsharma@5046 64 __u64 up : 1;
adsharma@5046 65 __u64 ac : 1;
adsharma@5046 66 __u64 mfl : 1;
adsharma@5046 67 __u64 mfh : 1;
adsharma@5046 68 __u64 reserved1 : 7;
adsharma@5046 69 __u64 ic : 1;
adsharma@5046 70 __u64 i : 1;
adsharma@5046 71 __u64 pk : 1;
adsharma@5046 72 __u64 reserved2 : 1;
adsharma@5046 73 __u64 dt : 1;
adsharma@5046 74 __u64 dfl : 1;
adsharma@5046 75 __u64 dfh : 1;
adsharma@5046 76 __u64 sp : 1;
adsharma@5046 77 __u64 pp : 1;
adsharma@5046 78 __u64 di : 1;
adsharma@5046 79 __u64 si : 1;
adsharma@5046 80 __u64 db : 1;
adsharma@5046 81 __u64 lp : 1;
adsharma@5046 82 __u64 tb : 1;
adsharma@5046 83 __u64 rt : 1;
adsharma@5046 84 __u64 reserved3 : 4;
adsharma@5046 85 __u64 cpl : 2;
adsharma@5046 86 __u64 is : 1;
adsharma@5046 87 __u64 mc : 1;
adsharma@5046 88 __u64 it : 1;
adsharma@5046 89 __u64 id : 1;
adsharma@5046 90 __u64 da : 1;
adsharma@5046 91 __u64 dd : 1;
adsharma@5046 92 __u64 ss : 1;
adsharma@5046 93 __u64 ri : 2;
adsharma@5046 94 __u64 ed : 1;
adsharma@5046 95 __u64 bn : 1;
adsharma@5046 96 __u64 reserved4 : 19;
adsharma@5046 97 };
adsharma@5046 98 } IA64_PSR;
adsharma@5046 99
adsharma@5046 100 typedef union {
adsharma@5046 101 __u64 val;
adsharma@5046 102 struct {
adsharma@5046 103 __u64 code : 16;
adsharma@5046 104 __u64 vector : 8;
adsharma@5046 105 __u64 reserved1 : 8;
adsharma@5046 106 __u64 x : 1;
adsharma@5046 107 __u64 w : 1;
adsharma@5046 108 __u64 r : 1;
adsharma@5046 109 __u64 na : 1;
adsharma@5046 110 __u64 sp : 1;
adsharma@5046 111 __u64 rs : 1;
adsharma@5046 112 __u64 ir : 1;
adsharma@5046 113 __u64 ni : 1;
adsharma@5046 114 __u64 so : 1;
adsharma@5046 115 __u64 ei : 2;
adsharma@5046 116 __u64 ed : 1;
adsharma@5046 117 __u64 reserved2 : 20;
adsharma@5046 118 };
adsharma@5046 119 } ISR;
adsharma@5046 120
adsharma@5046 121
adsharma@5046 122 typedef union {
adsharma@5046 123 __u64 val;
adsharma@5046 124 struct {
adsharma@5046 125 __u64 ve : 1;
adsharma@5046 126 __u64 reserved0 : 1;
adsharma@5046 127 __u64 size : 6;
adsharma@5046 128 __u64 vf : 1;
adsharma@5046 129 __u64 reserved1 : 6;
adsharma@5046 130 __u64 base : 49;
adsharma@5046 131 };
adsharma@5046 132 } PTA;
adsharma@5046 133
adsharma@5046 134 typedef union {
adsharma@5046 135 __u64 val;
adsharma@5046 136 struct {
adsharma@5046 137 __u64 rv : 16;
adsharma@5046 138 __u64 eid : 8;
adsharma@5046 139 __u64 id : 8;
adsharma@5046 140 __u64 ig : 32;
adsharma@5046 141 };
adsharma@5046 142 } LID;
adsharma@5046 143
adsharma@5046 144 typedef union{
adsharma@5046 145 __u64 val;
adsharma@5046 146 struct {
adsharma@5046 147 __u64 rv : 3;
adsharma@5046 148 __u64 ir : 1;
adsharma@5046 149 __u64 eid : 8;
adsharma@5046 150 __u64 id : 8;
adsharma@5046 151 __u64 ib_base : 44;
adsharma@5046 152 };
adsharma@5046 153 } ipi_a_t;
adsharma@5046 154
adsharma@5046 155 typedef union{
adsharma@5046 156 __u64 val;
adsharma@5046 157 struct {
adsharma@5046 158 __u64 vector : 8;
adsharma@5046 159 __u64 dm : 3;
adsharma@5046 160 __u64 ig : 53;
adsharma@5046 161 };
adsharma@5046 162 } ipi_d_t;
adsharma@5046 163
djm@5797 164 typedef union {
djm@5797 165 __u64 val;
djm@5797 166 struct {
djm@5797 167 __u64 ig0 : 4;
djm@5797 168 __u64 mic : 4;
djm@5797 169 __u64 rsv : 8;
djm@5797 170 __u64 mmi : 1;
djm@5797 171 __u64 ig1 : 47;
djm@5797 172 };
djm@5797 173 } tpr_t;
adsharma@5046 174
adsharma@5046 175 /* indirect register type */
adsharma@5046 176 enum {
adsharma@5046 177 IA64_CPUID, /* cpuid */
adsharma@5046 178 IA64_DBR, /* dbr */
adsharma@5046 179 IA64_IBR, /* ibr */
adsharma@5046 180 IA64_PKR, /* pkr */
adsharma@5046 181 IA64_PMC, /* pmc */
adsharma@5046 182 IA64_PMD, /* pmd */
adsharma@5046 183 IA64_RR /* rr */
adsharma@5046 184 };
adsharma@5046 185
adsharma@5046 186 /* instruction type */
adsharma@5046 187 enum {
adsharma@5046 188 IA64_INST_TPA=1,
adsharma@5046 189 IA64_INST_TAK
adsharma@5046 190 };
adsharma@5046 191
adsharma@5046 192 /* Generate Mask
adsharma@5046 193 * Parameter:
adsharma@5046 194 * bit -- starting bit
adsharma@5046 195 * len -- how many bits
adsharma@5046 196 */
adsharma@5046 197 #define MASK(bit,len) \
adsharma@5046 198 ({ \
adsharma@5046 199 __u64 ret; \
adsharma@5046 200 \
adsharma@5046 201 __asm __volatile("dep %0=-1, r0, %1, %2" \
adsharma@5046 202 : "=r" (ret): \
adsharma@5046 203 "M" (bit), \
adsharma@5046 204 "M" (len) ); \
adsharma@5046 205 ret; \
adsharma@5046 206 })
adsharma@5046 207
djm@6457 208 typedef union {
djm@6457 209 struct {
djm@6457 210 __u64 kr0;
djm@6457 211 __u64 kr1;
djm@6457 212 __u64 kr2;
djm@6457 213 __u64 kr3;
djm@6457 214 __u64 kr4;
djm@6457 215 __u64 kr5;
djm@6457 216 __u64 kr6;
djm@6457 217 __u64 kr7;
djm@6457 218 };
djm@6457 219 __u64 _kr[8];
djm@6457 220 } cpu_kr_ia64_t;
djm@6457 221
djm@6457 222 DECLARE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
djm@6457 223
awilliam@9756 224 typedef union {
awilliam@9756 225 struct {
awilliam@9756 226 u64 rv3 : 2; // 0-1
awilliam@9756 227 u64 ps : 6; // 2-7
awilliam@9756 228 u64 key : 24; // 8-31
awilliam@9756 229 u64 rv4 : 32; // 32-63
awilliam@9756 230 };
awilliam@9756 231 struct {
awilliam@9756 232 u64 __rv3 : 32; // 0-31
awilliam@9756 233 // next extension to rv4
awilliam@9756 234 u64 rid : 24; // 32-55
awilliam@9756 235 u64 __rv4 : 8; // 56-63
awilliam@9756 236 };
awilliam@9756 237 u64 itir;
awilliam@9756 238 } ia64_itir_t;
awilliam@9756 239
adsharma@5046 240 #endif // _ASM_IA64_XENPROCESSOR_H