ia64/xen-unstable

annotate tools/misc/xen_cpuperf.c @ 854:0cd58ce5a503

bitkeeper revision 1.531 (3f9da0175ZA8nMoVtg9tCQeXL4osyw)

time.c, xen_log.c, xen_cpuperf.c:
Add 'independent_wallclock' cmdline and sysctl options to xenolinux.
author kaf24@scramble.cl.cam.ac.uk
date Mon Oct 27 22:45:43 2003 +0000 (2003-10-27)
parents 399bb8faf92a
children b5c1b4c684f2
rev   line source
iap10@814 1 /*
iap10@814 2 * User mode program to prod MSR values through /proc/perfcntr
iap10@814 3 *
iap10@814 4 *
iap10@814 5 * $Id$
iap10@814 6 *
iap10@814 7 * $Log$
iap10@814 8 */
iap10@814 9
iap10@814 10 #include <sys/types.h>
iap10@814 11 #include <sched.h>
iap10@814 12 #include <error.h>
iap10@814 13 #include <stdio.h>
iap10@814 14 #include <unistd.h>
iap10@814 15 #include <stdlib.h>
iap10@814 16 #include <string.h>
iap10@814 17
iap10@814 18 #include "p4perf.h"
iap10@814 19 #include "dom0_defs.h"
iap10@814 20
iap10@814 21 void dom0_wrmsr( int cpu_mask, int msr, unsigned int low, unsigned int high )
iap10@814 22 {
iap10@814 23 dom0_op_t op;
iap10@814 24 op.cmd = DOM0_MSR;
iap10@814 25 op.u.msr.write = 1;
iap10@814 26 op.u.msr.msr = msr;
iap10@814 27 op.u.msr.cpu_mask = cpu_mask;
iap10@814 28 op.u.msr.in1 = low;
iap10@814 29 op.u.msr.in2 = high;
iap10@814 30 do_dom0_op(&op);
iap10@814 31 }
iap10@814 32
iap10@814 33 unsigned long long dom0_rdmsr( int cpu_mask, int msr )
iap10@814 34 {
iap10@814 35 dom0_op_t op;
iap10@814 36 op.cmd = DOM0_MSR;
iap10@814 37 op.u.msr.write = 0;
iap10@814 38 op.u.msr.msr = msr;
iap10@814 39 op.u.msr.cpu_mask = cpu_mask;
iap10@814 40 do_dom0_op(&op);
iap10@814 41 return (((unsigned long long)op.u.msr.out2)<<32) | op.u.msr.out1 ;
iap10@814 42 }
iap10@814 43
iap10@814 44 struct macros {
iap10@814 45 char *name;
iap10@814 46 unsigned long msr_addr;
iap10@814 47 int number;
iap10@814 48 };
iap10@814 49
iap10@814 50 struct macros msr[] = {
iap10@814 51 {"BPU_COUNTER0", 0x300, 0},
iap10@814 52 {"BPU_COUNTER1", 0x301, 1},
iap10@814 53 {"BPU_COUNTER2", 0x302, 2},
iap10@814 54 {"BPU_COUNTER3", 0x303, 3},
iap10@814 55 {"MS_COUNTER0", 0x304, 4},
iap10@814 56 {"MS_COUNTER1", 0x305, 5},
iap10@814 57 {"MS_COUNTER2", 0x306, 6},
iap10@814 58 {"MS_COUNTER3", 0x307, 7},
iap10@814 59 {"FLAME_COUNTER0", 0x308, 8},
iap10@814 60 {"FLAME_COUNTER1", 0x309, 9},
iap10@814 61 {"FLAME_COUNTER2", 0x30a, 10},
iap10@814 62 {"FLAME_COUNTER3", 0x30b, 11},
iap10@814 63 {"IQ_COUNTER0", 0x30c, 12},
iap10@814 64 {"IQ_COUNTER1", 0x30d, 13},
iap10@814 65 {"IQ_COUNTER2", 0x30e, 14},
iap10@814 66 {"IQ_COUNTER3", 0x30f, 15},
iap10@814 67 {"IQ_COUNTER4", 0x310, 16},
iap10@814 68 {"IQ_COUNTER5", 0x311, 17},
iap10@814 69 {"BPU_CCCR0", 0x360, 0},
iap10@814 70 {"BPU_CCCR1", 0x361, 1},
iap10@814 71 {"BPU_CCCR2", 0x362, 2},
iap10@814 72 {"BPU_CCCR3", 0x363, 3},
iap10@814 73 {"MS_CCCR0", 0x364, 4},
iap10@814 74 {"MS_CCCR1", 0x365, 5},
iap10@814 75 {"MS_CCCR2", 0x366, 6},
iap10@814 76 {"MS_CCCR3", 0x367, 7},
iap10@814 77 {"FLAME_CCCR0", 0x368, 8},
iap10@814 78 {"FLAME_CCCR1", 0x369, 9},
iap10@814 79 {"FLAME_CCCR2", 0x36a, 10},
iap10@814 80 {"FLAME_CCCR3", 0x36b, 11},
iap10@814 81 {"IQ_CCCR0", 0x36c, 12},
iap10@814 82 {"IQ_CCCR1", 0x36d, 13},
iap10@814 83 {"IQ_CCCR2", 0x36e, 14},
iap10@814 84 {"IQ_CCCR3", 0x36f, 15},
iap10@814 85 {"IQ_CCCR4", 0x370, 16},
iap10@814 86 {"IQ_CCCR5", 0x371, 17},
iap10@814 87 {"BSU_ESCR0", 0x3a0, 7},
iap10@814 88 {"BSU_ESCR1", 0x3a1, 7},
iap10@814 89 {"FSB_ESCR0", 0x3a2, 6},
iap10@814 90 {"FSB_ESCR1", 0x3a3, 6},
iap10@814 91 {"MOB_ESCR0", 0x3aa, 2},
iap10@814 92 {"MOB_ESCR1", 0x3ab, 2},
iap10@814 93 {"PMH_ESCR0", 0x3ac, 4},
iap10@814 94 {"PMH_ESCR1", 0x3ad, 4},
iap10@814 95 {"BPU_ESCR0", 0x3b2, 0},
iap10@814 96 {"BPU_ESCR1", 0x3b3, 0},
iap10@814 97 {"IS_ESCR0", 0x3b4, 1},
iap10@814 98 {"IS_ESCR1", 0x3b5, 1},
iap10@814 99 {"ITLB_ESCR0", 0x3b6, 3},
iap10@814 100 {"ITLB_ESCR1", 0x3b7, 3},
iap10@814 101 {"IX_ESCR0", 0x3c8, 5},
iap10@814 102 {"IX_ESCR1", 0x3c9, 5},
iap10@814 103 {"MS_ESCR0", 0x3c0, 0},
iap10@814 104 {"MS_ESCR1", 0x3c1, 0},
iap10@814 105 {"TBPU_ESCR0", 0x3c2, 2},
iap10@814 106 {"TBPU_ESCR1", 0x3c3, 2},
iap10@814 107 {"TC_ESCR0", 0x3c4, 1},
iap10@814 108 {"TC_ESCR1", 0x3c5, 1},
iap10@814 109 {"FIRM_ESCR0", 0x3a4, 1},
iap10@814 110 {"FIRM_ESCR1", 0x3a5, 1},
iap10@814 111 {"FLAME_ESCR0", 0x3a6, 0},
iap10@814 112 {"FLAME_ESCR1", 0x3a7, 0},
iap10@814 113 {"DAC_ESCR0", 0x3a8, 5},
iap10@814 114 {"DAC_ESCR1", 0x3a9, 5},
iap10@814 115 {"SAAT_ESCR0", 0x3ae, 2},
iap10@814 116 {"SAAT_ESCR1", 0x3af, 2},
iap10@814 117 {"U2L_ESCR0", 0x3b0, 3},
iap10@814 118 {"U2L_ESCR1", 0x3b1, 3},
iap10@814 119 {"CRU_ESCR0", 0x3b8, 4},
iap10@814 120 {"CRU_ESCR1", 0x3b9, 4},
iap10@814 121 {"CRU_ESCR2", 0x3cc, 5},
iap10@814 122 {"CRU_ESCR3", 0x3cd, 5},
iap10@814 123 {"CRU_ESCR4", 0x3e0, 6},
iap10@814 124 {"CRU_ESCR5", 0x3e1, 6},
iap10@814 125 {"IQ_ESCR0", 0x3ba, 0},
iap10@814 126 {"IQ_ESCR1", 0x3bb, 0},
iap10@814 127 {"RAT_ESCR0", 0x3bc, 2},
iap10@814 128 {"RAT_ESCR1", 0x3bd, 2},
iap10@814 129 {"SSU_ESCR0", 0x3be, 3},
iap10@814 130 {"SSU_ESCR1", 0x3bf, 3},
iap10@814 131 {"ALF_ESCR0", 0x3ca, 1},
iap10@814 132 {"ALF_ESCR1", 0x3cb, 1},
iap10@814 133 {"PEBS_ENABLE", 0x3f1, 0},
iap10@814 134 {"PEBS_MATRIX_VERT", 0x3f2, 0},
iap10@814 135 {NULL, 0, 0}
iap10@814 136 };
iap10@814 137
iap10@814 138 struct macros *lookup_macro(char *str)
iap10@814 139 {
iap10@814 140 struct macros *m;
iap10@814 141
iap10@814 142 m = msr;
iap10@814 143 while (m->name) {
iap10@814 144 if (strcmp(m->name, str) == 0)
iap10@814 145 return m;
iap10@814 146 m++;
iap10@814 147 }
iap10@814 148 return NULL;
iap10@814 149 }
iap10@814 150
iap10@814 151 int main(int argc, char **argv)
iap10@814 152 {
iap10@814 153 int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
iap10@814 154 unsigned int cpu_mask = 1;
iap10@814 155 struct macros *escr = NULL, *cccr = NULL;
iap10@814 156 unsigned long escr_val, cccr_val;
iap10@814 157 int debug = 0;
iap10@814 158 unsigned long pebs = 0, pebs_vert = 0;
iap10@814 159 int pebs_x = 0, pebs_vert_x = 0;
iap10@814 160 int read = 0;
iap10@814 161
iap10@814 162 while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:r")) != -1) {
iap10@814 163 switch((char)c) {
iap10@814 164 case 'P':
iap10@814 165 pebs |= 1 << atoi(optarg);
iap10@814 166 pebs_x = 1;
iap10@814 167 break;
iap10@814 168 case 'V':
iap10@814 169 pebs_vert |= 1 << atoi(optarg);
iap10@814 170 pebs_vert_x = 1;
iap10@814 171 break;
iap10@814 172 case 'd':
iap10@814 173 debug = 1;
iap10@814 174 break;
iap10@814 175 case 'c':
iap10@814 176 {
iap10@814 177 int cpu = atoi(optarg);
iap10@814 178 cpu_mask = (cpu == -1)?(~0):(1<<cpu);
iap10@814 179 break;
iap10@814 180 }
iap10@814 181 case 't': // ESCR thread bits
iap10@814 182 t = atoi(optarg);
iap10@814 183 break;
iap10@814 184 case 'e': // eventsel
iap10@814 185 es = atoi(optarg);
iap10@814 186 break;
iap10@814 187 case 'm': // eventmask
iap10@814 188 em = atoi(optarg);
iap10@814 189 break;
iap10@814 190 case 'T': // tag value
iap10@814 191 tv = atoi(optarg);
iap10@814 192 te = 1;
iap10@814 193 break;
iap10@814 194 case 'E':
iap10@814 195 escr = lookup_macro(optarg);
iap10@814 196 if (!escr) {
iap10@814 197 fprintf(stderr, "Macro '%s' not found.\n", optarg);
iap10@814 198 exit(1);
iap10@814 199 }
iap10@814 200 break;
iap10@814 201 case 'C':
iap10@814 202 cccr = lookup_macro(optarg);
iap10@814 203 if (!cccr) {
iap10@814 204 fprintf(stderr, "Macro '%s' not found.\n", optarg);
iap10@814 205 exit(1);
iap10@814 206 }
iap10@814 207 break;
iap10@814 208 case 'r':
iap10@814 209 read = 1;
iap10@814 210 break;
iap10@814 211 }
iap10@814 212 }
iap10@814 213
iap10@814 214 if (read) {
iap10@814 215 while((cpu_mask&1)) {
iap10@814 216 int i;
iap10@814 217 for (i=0x300;i<0x312;i++)
iap10@814 218 {
iap10@814 219 printf("%010llx ",dom0_rdmsr( cpu_mask, i ) );
iap10@814 220 }
iap10@814 221 printf("\n");
iap10@814 222 cpu_mask>>=1;
iap10@814 223 }
iap10@814 224 exit(1);
iap10@814 225 }
iap10@814 226
iap10@814 227 if (!escr) {
iap10@814 228 fprintf(stderr, "Need an ESCR.\n");
iap10@814 229 exit(1);
iap10@814 230 }
iap10@814 231 if (!cccr) {
iap10@814 232 fprintf(stderr, "Need a counter number.\n");
iap10@814 233 exit(1);
iap10@814 234 }
iap10@814 235
iap10@814 236 escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
iap10@814 237 P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
iap10@814 238 cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
iap10@814 239 P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
iap10@814 240
iap10@814 241 if (debug) {
iap10@814 242 fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
iap10@814 243 fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
iap10@814 244 cccr->msr_addr, cccr_val, cccr->number);
iap10@814 245 if (pebs_x)
iap10@814 246 fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
iap10@814 247 MSR_P4_PEBS_ENABLE, pebs);
iap10@814 248 if (pebs_vert_x)
iap10@814 249 fprintf(stderr, "PMV 0x%x <= 0x%08lx\n",
iap10@814 250 MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
iap10@814 251 }
iap10@814 252
iap10@814 253 dom0_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
iap10@814 254 dom0_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
iap10@814 255
iap10@814 256 if (pebs_x)
iap10@814 257 dom0_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
iap10@814 258
iap10@814 259 if (pebs_vert_x)
iap10@814 260 dom0_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
iap10@814 261
iap10@814 262 return 0;
iap10@814 263 }
iap10@814 264