ia64/xen-unstable

annotate xen/arch/x86/apic.c @ 8847:07a892f12609

More upgrades of Xen code to linux-2.6.16-rc2.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Tue Feb 14 18:25:10 2006 +0100 (2006-02-14)
parents b9b411b50587
children 503c4d8454e5
rev   line source
kaf24@1452 1 /*
kaf24@4888 2 * based on linux-2.6.11/arch/i386/kernel/apic.c
iap10@4548 3 *
kaf24@1452 4 * Local APIC handling, local APIC timers
kaf24@1452 5 *
kaf24@1452 6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
kaf24@1452 7 *
kaf24@1452 8 * Fixes
kaf24@1452 9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
kaf24@1452 10 * thanks to Eric Gilmore
kaf24@1452 11 * and Rolf G. Tews
kaf24@1452 12 * for testing these extensively.
kaf24@1452 13 * Maciej W. Rozycki : Various updates and fixes.
kaf24@1452 14 * Mikael Pettersson : Power Management for UP-APIC.
iap10@4548 15 * Pavel Machek and
iap10@4548 16 * Mikael Pettersson : PM converted to driver model.
kaf24@1452 17 */
kaf24@1452 18
kaf24@1452 19 #include <xen/config.h>
kaf24@1506 20 #include <xen/perfc.h>
kaf24@1506 21 #include <xen/errno.h>
kaf24@1452 22 #include <xen/init.h>
kaf24@1506 23 #include <xen/mm.h>
kaf24@1452 24 #include <xen/sched.h>
kaf24@1452 25 #include <xen/irq.h>
kaf24@1452 26 #include <xen/delay.h>
kaf24@1506 27 #include <xen/smp.h>
kaf24@1506 28 #include <xen/softirq.h>
kaf24@1452 29 #include <asm/mc146818rtc.h>
kaf24@1452 30 #include <asm/msr.h>
kaf24@1452 31 #include <asm/atomic.h>
kaf24@1452 32 #include <asm/mpspec.h>
kaf24@1452 33 #include <asm/flushtlb.h>
kaf24@1452 34 #include <asm/hardirq.h>
kaf24@1452 35 #include <asm/apic.h>
kaf24@1452 36 #include <asm/io_apic.h>
kaf24@4804 37 #include <mach_apic.h>
kaf24@4804 38 #include <io_ports.h>
kaf24@1452 39
kaf24@4888 40 /*
kaf24@8847 41 * Knob to control our willingness to enable the local APIC.
kaf24@8847 42 */
kaf24@8847 43 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
kaf24@8847 44
kaf24@8847 45 /*
kaf24@4888 46 * Debug level
kaf24@4888 47 */
kaf24@4888 48 int apic_verbosity;
kaf24@4888 49
kaf24@8847 50
kaf24@8847 51 static void apic_pm_activate(void);
kaf24@8847 52
kaf24@8847 53 /*
kaf24@8847 54 * 'what should we do if we get a hw irq event on an illegal vector'.
kaf24@8847 55 * each architecture has to answer this themselves.
kaf24@8847 56 */
kaf24@8847 57 void ack_bad_irq(unsigned int irq)
kaf24@8847 58 {
kaf24@8847 59 printk("unexpected IRQ trap at vector %02x\n", irq);
kaf24@8847 60 /*
kaf24@8847 61 * Currently unexpected vectors happen only on SMP and APIC.
kaf24@8847 62 * We _must_ ack these because every local APIC has only N
kaf24@8847 63 * irq slots per priority level, and a 'hanging, unacked' IRQ
kaf24@8847 64 * holds up an irq slot - in excessive cases (when multiple
kaf24@8847 65 * unexpected vectors occur) that might lock up the APIC
kaf24@8847 66 * completely.
kaf24@8847 67 */
kaf24@8847 68 ack_APIC_irq();
kaf24@8847 69 }
kaf24@8847 70
kaf24@8847 71 void __init apic_intr_init(void)
kaf24@8847 72 {
kaf24@8847 73 #ifdef CONFIG_SMP
kaf24@8847 74 smp_intr_init();
kaf24@8847 75 #endif
kaf24@8847 76 /* self generated IPI for local APIC timer */
kaf24@8847 77 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
kaf24@8847 78
kaf24@8847 79 /* IPI vectors for APIC spurious and error interrupts */
kaf24@8847 80 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
kaf24@8847 81 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
kaf24@8847 82
kaf24@8847 83 /* thermal monitor LVT interrupt */
kaf24@8847 84 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@8847 85 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
kaf24@8847 86 #endif
kaf24@8847 87 }
kaf24@8847 88
kaf24@1452 89 /* Using APIC to generate smp_local_timer_interrupt? */
kaf24@1452 90 int using_apic_timer = 0;
kaf24@1452 91
kaf24@1452 92 static int enabled_via_apicbase;
kaf24@1452 93
kaf24@4804 94 int get_physical_broadcast(void)
kaf24@4804 95 {
kaf24@4804 96 unsigned int lvr, version;
kaf24@4804 97 lvr = apic_read(APIC_LVR);
kaf24@4804 98 version = GET_APIC_VERSION(lvr);
kaf24@4804 99 if (!APIC_INTEGRATED(version) || version >= 0x14)
kaf24@4804 100 return 0xff;
kaf24@4804 101 else
kaf24@4804 102 return 0xf;
kaf24@4804 103 }
kaf24@4804 104
kaf24@1452 105 int get_maxlvt(void)
kaf24@1452 106 {
kaf24@1452 107 unsigned int v, ver, maxlvt;
kaf24@1452 108
kaf24@1452 109 v = apic_read(APIC_LVR);
kaf24@1452 110 ver = GET_APIC_VERSION(v);
kaf24@1452 111 /* 82489DXs do not report # of LVT entries. */
kaf24@1452 112 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
kaf24@1452 113 return maxlvt;
kaf24@1452 114 }
kaf24@1452 115
kaf24@1452 116 void clear_local_APIC(void)
kaf24@1452 117 {
kaf24@1452 118 int maxlvt;
kaf24@1452 119 unsigned long v;
kaf24@1452 120
kaf24@1452 121 maxlvt = get_maxlvt();
kaf24@1452 122
kaf24@1452 123 /*
kaf24@1452 124 * Masking an LVT entry on a P6 can trigger a local APIC error
kaf24@1452 125 * if the vector is zero. Mask LVTERR first to prevent this.
kaf24@1452 126 */
kaf24@1452 127 if (maxlvt >= 3) {
kaf24@1452 128 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
kaf24@1452 129 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
kaf24@1452 130 }
kaf24@1452 131 /*
kaf24@1452 132 * Careful: we have to set masks only first to deassert
kaf24@1452 133 * any level-triggered sources.
kaf24@1452 134 */
kaf24@1452 135 v = apic_read(APIC_LVTT);
kaf24@1452 136 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@1452 137 v = apic_read(APIC_LVT0);
kaf24@1452 138 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
kaf24@1452 139 v = apic_read(APIC_LVT1);
kaf24@1452 140 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
kaf24@1452 141 if (maxlvt >= 4) {
kaf24@1452 142 v = apic_read(APIC_LVTPC);
kaf24@1452 143 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
kaf24@1452 144 }
kaf24@1452 145
kaf24@5211 146 /* lets not touch this if we didn't frob it */
kaf24@5211 147 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 148 if (maxlvt >= 5) {
kaf24@5211 149 v = apic_read(APIC_LVTTHMR);
kaf24@5211 150 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
kaf24@5211 151 }
kaf24@5211 152 #endif
kaf24@1452 153 /*
kaf24@1452 154 * Clean APIC state for other OSs:
kaf24@1452 155 */
kaf24@1452 156 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
kaf24@1452 157 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@1452 158 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
kaf24@1452 159 if (maxlvt >= 3)
kaf24@1452 160 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
kaf24@1452 161 if (maxlvt >= 4)
kaf24@1452 162 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
iap10@4548 163
kaf24@5211 164 #ifdef CONFIG_X86_MCE_P4THERMAL
kaf24@5211 165 if (maxlvt >= 5)
kaf24@5211 166 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
kaf24@5211 167 #endif
kaf24@1452 168 v = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@1452 169 if (APIC_INTEGRATED(v)) { /* !82489DX */
iap10@4548 170 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
kaf24@1452 171 apic_write(APIC_ESR, 0);
kaf24@1452 172 apic_read(APIC_ESR);
kaf24@1452 173 }
kaf24@1452 174 }
kaf24@1452 175
kaf24@1452 176 void __init connect_bsp_APIC(void)
kaf24@1452 177 {
kaf24@1452 178 if (pic_mode) {
kaf24@1452 179 /*
kaf24@1452 180 * Do not trust the local APIC being empty at bootup.
kaf24@1452 181 */
kaf24@1452 182 clear_local_APIC();
kaf24@1452 183 /*
kaf24@1452 184 * PIC mode, enable APIC mode in the IMCR, i.e.
kaf24@1452 185 * connect BSP's local APIC to INT and NMI lines.
kaf24@1452 186 */
kaf24@4888 187 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
kaf24@4888 188 "enabling APIC mode.\n");
kaf24@1452 189 outb(0x70, 0x22);
kaf24@1452 190 outb(0x01, 0x23);
kaf24@1452 191 }
kaf24@5211 192 enable_apic_mode();
kaf24@1452 193 }
kaf24@1452 194
kaf24@8847 195 void disconnect_bsp_APIC(int virt_wire_setup)
kaf24@1452 196 {
kaf24@1452 197 if (pic_mode) {
kaf24@1452 198 /*
kaf24@1452 199 * Put the board back into PIC mode (has an effect
kaf24@1452 200 * only on certain older boards). Note that APIC
kaf24@1452 201 * interrupts, including IPIs, won't work beyond
kaf24@1452 202 * this point! The only exception are INIT IPIs.
kaf24@1452 203 */
kaf24@4888 204 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
kaf24@4888 205 "entering PIC mode.\n");
kaf24@1452 206 outb(0x70, 0x22);
kaf24@1452 207 outb(0x00, 0x23);
kaf24@1452 208 }
kaf24@8847 209 else {
kaf24@8847 210 /* Go back to Virtual Wire compatibility mode */
kaf24@8847 211 unsigned long value;
kaf24@8847 212
kaf24@8847 213 /* For the spurious interrupt use vector F, and enable it */
kaf24@8847 214 value = apic_read(APIC_SPIV);
kaf24@8847 215 value &= ~APIC_VECTOR_MASK;
kaf24@8847 216 value |= APIC_SPIV_APIC_ENABLED;
kaf24@8847 217 value |= 0xf;
kaf24@8847 218 apic_write_around(APIC_SPIV, value);
kaf24@8847 219
kaf24@8847 220 if (!virt_wire_setup) {
kaf24@8847 221 /* For LVT0 make it edge triggered, active high, external and enabled */
kaf24@8847 222 value = apic_read(APIC_LVT0);
kaf24@8847 223 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 224 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 225 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
kaf24@8847 226 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 227 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
kaf24@8847 228 apic_write_around(APIC_LVT0, value);
kaf24@8847 229 }
kaf24@8847 230 else {
kaf24@8847 231 /* Disable LVT0 */
kaf24@8847 232 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
kaf24@8847 233 }
kaf24@8847 234
kaf24@8847 235 /* For LVT1 make it edge triggered, active high, nmi and enabled */
kaf24@8847 236 value = apic_read(APIC_LVT1);
kaf24@8847 237 value &= ~(
kaf24@8847 238 APIC_MODE_MASK | APIC_SEND_PENDING |
kaf24@8847 239 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
kaf24@8847 240 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
kaf24@8847 241 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
kaf24@8847 242 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
kaf24@8847 243 apic_write_around(APIC_LVT1, value);
kaf24@8847 244 }
kaf24@1452 245 }
kaf24@1452 246
kaf24@1452 247 void disable_local_APIC(void)
kaf24@1452 248 {
kaf24@1452 249 unsigned long value;
kaf24@1452 250
kaf24@1452 251 clear_local_APIC();
kaf24@1452 252
kaf24@1452 253 /*
kaf24@1452 254 * Disable APIC (implies clearing of registers
kaf24@1452 255 * for 82489DX!).
kaf24@1452 256 */
kaf24@1452 257 value = apic_read(APIC_SPIV);
kaf24@1452 258 value &= ~APIC_SPIV_APIC_ENABLED;
kaf24@1452 259 apic_write_around(APIC_SPIV, value);
kaf24@1452 260
kaf24@1452 261 if (enabled_via_apicbase) {
kaf24@1452 262 unsigned int l, h;
kaf24@1452 263 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 264 l &= ~MSR_IA32_APICBASE_ENABLE;
kaf24@1452 265 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 266 }
kaf24@1452 267 }
kaf24@1452 268
kaf24@1452 269 /*
kaf24@1452 270 * This is to verify that we're looking at a real local APIC.
kaf24@1452 271 * Check these against your board if the CPUs aren't getting
kaf24@1452 272 * started for no apparent reason.
kaf24@1452 273 */
kaf24@1452 274 int __init verify_local_APIC(void)
kaf24@1452 275 {
kaf24@1452 276 unsigned int reg0, reg1;
kaf24@1452 277
kaf24@1452 278 /*
kaf24@1452 279 * The version register is read-only in a real APIC.
kaf24@1452 280 */
kaf24@1452 281 reg0 = apic_read(APIC_LVR);
kaf24@4888 282 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
kaf24@1452 283 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
kaf24@1452 284 reg1 = apic_read(APIC_LVR);
kaf24@4888 285 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
kaf24@1452 286
kaf24@1452 287 /*
kaf24@1452 288 * The two version reads above should print the same
kaf24@1452 289 * numbers. If the second one is different, then we
kaf24@1452 290 * poke at a non-APIC.
kaf24@1452 291 */
kaf24@1452 292 if (reg1 != reg0)
kaf24@1452 293 return 0;
kaf24@1452 294
kaf24@1452 295 /*
kaf24@1452 296 * Check if the version looks reasonably.
kaf24@1452 297 */
kaf24@1452 298 reg1 = GET_APIC_VERSION(reg0);
kaf24@1452 299 if (reg1 == 0x00 || reg1 == 0xff)
kaf24@1452 300 return 0;
kaf24@1452 301 reg1 = get_maxlvt();
kaf24@1452 302 if (reg1 < 0x02 || reg1 == 0xff)
kaf24@1452 303 return 0;
kaf24@1452 304
kaf24@1452 305 /*
kaf24@1452 306 * The ID register is read/write in a real APIC.
kaf24@1452 307 */
kaf24@1452 308 reg0 = apic_read(APIC_ID);
kaf24@4888 309 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
kaf24@1452 310
kaf24@1452 311 /*
kaf24@1452 312 * The next two are just to see if we have sane values.
kaf24@1452 313 * They're only really relevant if we're in Virtual Wire
kaf24@1452 314 * compatibility mode, but most boxes are anymore.
kaf24@1452 315 */
kaf24@1452 316 reg0 = apic_read(APIC_LVT0);
kaf24@4888 317 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
kaf24@1452 318 reg1 = apic_read(APIC_LVT1);
kaf24@4888 319 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
kaf24@1452 320
kaf24@1452 321 return 1;
kaf24@1452 322 }
kaf24@1452 323
kaf24@1452 324 void __init sync_Arb_IDs(void)
kaf24@1452 325 {
iap10@4548 326 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
iap10@4548 327 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
iap10@4548 328 if (ver >= 0x14) /* P4 or higher */
iap10@4548 329 return;
kaf24@1452 330 /*
kaf24@1452 331 * Wait for idle.
kaf24@1452 332 */
kaf24@1452 333 apic_wait_icr_idle();
kaf24@1452 334
kaf24@4888 335 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
kaf24@1452 336 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
kaf24@1452 337 | APIC_DM_INIT);
kaf24@1452 338 }
kaf24@1452 339
kaf24@1452 340 extern void __error_in_apic_c (void);
kaf24@1452 341
kaf24@4888 342 /*
kaf24@4888 343 * An initial setup of the virtual wire mode.
kaf24@4888 344 */
kaf24@1452 345 void __init init_bsp_APIC(void)
kaf24@1452 346 {
kaf24@4620 347 unsigned long value, ver;
kaf24@4620 348
kaf24@4620 349 /*
kaf24@4888 350 * Don't do the setup now if we have a SMP BIOS as the
kaf24@4888 351 * through-I/O-APIC virtual wire mode might be active.
kaf24@4620 352 */
kaf24@4620 353 if (smp_found_config || !cpu_has_apic)
kaf24@4620 354 return;
kaf24@4620 355
kaf24@4620 356 value = apic_read(APIC_LVR);
kaf24@4620 357 ver = GET_APIC_VERSION(value);
kaf24@4620 358
kaf24@4620 359 /*
kaf24@4620 360 * Do not trust the local APIC being empty at bootup.
kaf24@4620 361 */
kaf24@4620 362 clear_local_APIC();
kaf24@4620 363
kaf24@4620 364 /*
kaf24@4620 365 * Enable APIC.
kaf24@4620 366 */
kaf24@4620 367 value = apic_read(APIC_SPIV);
kaf24@4620 368 value &= ~APIC_VECTOR_MASK;
kaf24@4620 369 value |= APIC_SPIV_APIC_ENABLED;
kaf24@4620 370
kaf24@4620 371 /* This bit is reserved on P4/Xeon and should be cleared */
kaf24@4620 372 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
kaf24@4620 373 value &= ~APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 374 else
kaf24@4620 375 value |= APIC_SPIV_FOCUS_DISABLED;
kaf24@4620 376 value |= SPURIOUS_APIC_VECTOR;
kaf24@4620 377 apic_write_around(APIC_SPIV, value);
kaf24@4620 378
kaf24@4620 379 /*
kaf24@4620 380 * Set up the virtual wire mode.
kaf24@4620 381 */
kaf24@4620 382 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
kaf24@4620 383 value = APIC_DM_NMI;
kaf24@4620 384 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@4620 385 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@4620 386 apic_write_around(APIC_LVT1, value);
kaf24@1452 387 }
kaf24@1452 388
kaf24@8847 389 void __devinit setup_local_APIC(void)
kaf24@1452 390 {
iap10@4548 391 unsigned long oldvalue, value, ver, maxlvt;
iap10@4548 392
iap10@4548 393 /* Pound the ESR really hard over the head with a big hammer - mbligh */
iap10@4548 394 if (esr_disable) {
iap10@4548 395 apic_write(APIC_ESR, 0);
iap10@4548 396 apic_write(APIC_ESR, 0);
iap10@4548 397 apic_write(APIC_ESR, 0);
iap10@4548 398 apic_write(APIC_ESR, 0);
iap10@4548 399 }
kaf24@1452 400
kaf24@1452 401 value = apic_read(APIC_LVR);
kaf24@1452 402 ver = GET_APIC_VERSION(value);
kaf24@1452 403
kaf24@1452 404 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
kaf24@1452 405 __error_in_apic_c();
kaf24@1452 406
iap10@4548 407 /*
iap10@4548 408 * Double-check whether this APIC is really registered.
iap10@4548 409 */
iap10@4548 410 if (!apic_id_registered())
kaf24@1452 411 BUG();
kaf24@1452 412
kaf24@1452 413 /*
kaf24@1452 414 * Intel recommends to set DFR, LDR and TPR before enabling
kaf24@1452 415 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
kaf24@1452 416 * document number 292116). So here it goes...
kaf24@1452 417 */
iap10@4548 418 init_apic_ldr();
kaf24@1452 419
kaf24@1452 420 /*
kaf24@1452 421 * Set Task Priority to 'accept all'. We never change this
kaf24@1452 422 * later on.
kaf24@1452 423 */
kaf24@1452 424 value = apic_read(APIC_TASKPRI);
kaf24@1452 425 value &= ~APIC_TPRI_MASK;
kaf24@1452 426 apic_write_around(APIC_TASKPRI, value);
kaf24@1452 427
kaf24@1452 428 /*
kaf24@1452 429 * Now that we are all set up, enable the APIC
kaf24@1452 430 */
kaf24@1452 431 value = apic_read(APIC_SPIV);
kaf24@1452 432 value &= ~APIC_VECTOR_MASK;
kaf24@1452 433 /*
kaf24@1452 434 * Enable APIC
kaf24@1452 435 */
kaf24@1452 436 value |= APIC_SPIV_APIC_ENABLED;
kaf24@1452 437
iap10@4548 438 /*
iap10@4548 439 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
iap10@4548 440 * certain networking cards. If high frequency interrupts are
iap10@4548 441 * happening on a particular IOAPIC pin, plus the IOAPIC routing
iap10@4548 442 * entry is masked/unmasked at a high rate as well then sooner or
iap10@4548 443 * later IOAPIC line gets 'stuck', no more interrupts are received
iap10@4548 444 * from the device. If focus CPU is disabled then the hang goes
iap10@4548 445 * away, oh well :-(
iap10@4548 446 *
iap10@4548 447 * [ This bug can be reproduced easily with a level-triggered
iap10@4548 448 * PCI Ne2000 networking cards and PII/PIII processors, dual
iap10@4548 449 * BX chipset. ]
iap10@4548 450 */
iap10@4548 451 /*
iap10@4548 452 * Actually disabling the focus CPU check just makes the hang less
iap10@4548 453 * frequent as it makes the interrupt distributon model be more
iap10@4548 454 * like LRU than MRU (the short-term load is more even across CPUs).
iap10@4548 455 * See also the comment in end_level_ioapic_irq(). --macro
iap10@4548 456 */
iap10@4548 457 #if 1
kaf24@1452 458 /* Enable focus processor (bit==0) */
kaf24@1452 459 value &= ~APIC_SPIV_FOCUS_DISABLED;
iap10@4548 460 #else
iap10@4548 461 /* Disable focus processor (bit==1) */
iap10@4548 462 value |= APIC_SPIV_FOCUS_DISABLED;
iap10@4548 463 #endif
iap10@4548 464 /*
iap10@4548 465 * Set spurious IRQ vector
iap10@4548 466 */
kaf24@1452 467 value |= SPURIOUS_APIC_VECTOR;
kaf24@1452 468 apic_write_around(APIC_SPIV, value);
kaf24@1452 469
kaf24@1452 470 /*
kaf24@1452 471 * Set up LVT0, LVT1:
kaf24@1452 472 *
kaf24@1452 473 * set up through-local-APIC on the BP's LINT0. This is not
kaf24@1452 474 * strictly necessery in pure symmetric-IO mode, but sometimes
kaf24@1452 475 * we delegate interrupts to the 8259A.
kaf24@1452 476 */
kaf24@1452 477 /*
kaf24@1452 478 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
kaf24@1452 479 */
kaf24@1452 480 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
iap10@4548 481 if (!smp_processor_id() && (pic_mode || !value)) {
kaf24@1452 482 value = APIC_DM_EXTINT;
kaf24@4888 483 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
kaf24@4888 484 smp_processor_id());
kaf24@1452 485 } else {
kaf24@1452 486 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
kaf24@4888 487 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
kaf24@4888 488 smp_processor_id());
kaf24@1452 489 }
kaf24@1452 490 apic_write_around(APIC_LVT0, value);
kaf24@1452 491
kaf24@1452 492 /*
kaf24@1452 493 * only the BP should see the LINT1 NMI signal, obviously.
kaf24@1452 494 */
kaf24@1452 495 if (!smp_processor_id())
kaf24@1452 496 value = APIC_DM_NMI;
kaf24@1452 497 else
kaf24@1452 498 value = APIC_DM_NMI | APIC_LVT_MASKED;
kaf24@1452 499 if (!APIC_INTEGRATED(ver)) /* 82489DX */
kaf24@1452 500 value |= APIC_LVT_LEVEL_TRIGGER;
kaf24@1452 501 apic_write_around(APIC_LVT1, value);
kaf24@1452 502
iap10@4548 503 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
kaf24@1452 504 maxlvt = get_maxlvt();
kaf24@1452 505 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
kaf24@1452 506 apic_write(APIC_ESR, 0);
iap10@4548 507 oldvalue = apic_read(APIC_ESR);
kaf24@1452 508
iap10@4548 509 value = ERROR_APIC_VECTOR; // enables sending errors
kaf24@1452 510 apic_write_around(APIC_LVTERR, value);
iap10@4548 511 /*
iap10@4548 512 * spec says clear errors after enabling vector.
iap10@4548 513 */
kaf24@1452 514 if (maxlvt > 3)
kaf24@1452 515 apic_write(APIC_ESR, 0);
kaf24@1452 516 value = apic_read(APIC_ESR);
iap10@4548 517 if (value != oldvalue)
kaf24@4888 518 apic_printk(APIC_VERBOSE, "ESR value before enabling "
kaf24@4888 519 "vector: 0x%08lx after: 0x%08lx\n",
kaf24@4888 520 oldvalue, value);
kaf24@1452 521 } else {
iap10@4548 522 if (esr_disable)
iap10@4548 523 /*
iap10@4548 524 * Something untraceble is creating bad interrupts on
iap10@4548 525 * secondary quads ... for the moment, just leave the
iap10@4548 526 * ESR disabled - we can't do anything useful with the
iap10@4548 527 * errors anyway - mbligh
iap10@4548 528 */
iap10@4548 529 printk("Leaving ESR disabled.\n");
kaf24@4888 530 else
kaf24@4888 531 printk("No ESR for 82489DX.\n");
kaf24@1452 532 }
kaf24@1452 533
kaf24@8594 534 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@8594 535 setup_apic_nmi_watchdog();
kaf24@8847 536 apic_pm_activate();
kaf24@1452 537 }
kaf24@1452 538
kaf24@8847 539 static void apic_pm_activate(void) { }
kaf24@8847 540
kaf24@1452 541 /*
kaf24@1452 542 * Detect and enable local APICs on non-SMP boards.
kaf24@1452 543 * Original code written by Keir Fraser.
kaf24@1452 544 */
kaf24@1452 545
kaf24@5211 546 static void __init lapic_disable(char *str)
kaf24@5211 547 {
kaf24@5211 548 enable_local_apic = -1;
kaf24@5211 549 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 550 }
kaf24@5211 551 custom_param("nolapic", lapic_disable);
kaf24@5211 552
kaf24@5211 553 static void __init lapic_enable(char *str)
kaf24@5211 554 {
kaf24@5211 555 enable_local_apic = 1;
kaf24@5211 556 }
kaf24@5211 557 custom_param("lapic", lapic_enable);
kaf24@5211 558
kaf24@4888 559 static void __init apic_set_verbosity(char *str)
kaf24@4888 560 {
kaf24@4888 561 if (strcmp("debug", str) == 0)
kaf24@4888 562 apic_verbosity = APIC_DEBUG;
kaf24@4888 563 else if (strcmp("verbose", str) == 0)
kaf24@4888 564 apic_verbosity = APIC_VERBOSE;
kaf24@5211 565 else
kaf24@5211 566 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
kaf24@5211 567 " use apic_verbosity=verbose or apic_verbosity=debug", str);
kaf24@4888 568 }
kaf24@5211 569 custom_param("apic_verbosity", apic_set_verbosity);
kaf24@4888 570
kaf24@1452 571 static int __init detect_init_APIC (void)
kaf24@1452 572 {
kaf24@1452 573 u32 h, l, features;
kaf24@1452 574
kaf24@5211 575 /* Disabled by kernel option? */
kaf24@5211 576 if (enable_local_apic < 0)
kaf24@5211 577 return -1;
kaf24@5211 578
kaf24@1452 579 switch (boot_cpu_data.x86_vendor) {
kaf24@1452 580 case X86_VENDOR_AMD:
iap10@4548 581 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
iap10@4548 582 (boot_cpu_data.x86 == 15))
kaf24@1452 583 break;
kaf24@1452 584 goto no_apic;
kaf24@1452 585 case X86_VENDOR_INTEL:
iap10@4548 586 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
kaf24@1452 587 (boot_cpu_data.x86 == 5 && cpu_has_apic))
kaf24@1452 588 break;
kaf24@1452 589 goto no_apic;
kaf24@1452 590 default:
kaf24@1452 591 goto no_apic;
kaf24@1452 592 }
kaf24@1452 593
kaf24@1452 594 if (!cpu_has_apic) {
kaf24@1452 595 /*
kaf24@5211 596 * Over-ride BIOS and try to enable the local
kaf24@5211 597 * APIC only if "lapic" specified.
kaf24@5211 598 */
kaf24@5211 599 if (enable_local_apic <= 0) {
kaf24@5211 600 printk("Local APIC disabled by BIOS -- "
kaf24@5211 601 "you can enable it with \"lapic\"\n");
kaf24@5211 602 return -1;
kaf24@5211 603 }
kaf24@5211 604 /*
kaf24@1452 605 * Some BIOSes disable the local APIC in the
kaf24@1452 606 * APIC_BASE MSR. This can only be done in
iap10@4548 607 * software for Intel P6 or later and AMD K7
iap10@4548 608 * (Model > 1) or later.
kaf24@1452 609 */
kaf24@1452 610 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 611 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
kaf24@1452 612 printk("Local APIC disabled by BIOS -- reenabling.\n");
kaf24@1452 613 l &= ~MSR_IA32_APICBASE_BASE;
kaf24@1452 614 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
kaf24@1452 615 wrmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 616 enabled_via_apicbase = 1;
kaf24@1452 617 }
kaf24@1452 618 }
kaf24@4888 619 /*
kaf24@4888 620 * The APIC feature bit should now be enabled
kaf24@4888 621 * in `cpuid'
kaf24@4888 622 */
kaf24@1452 623 features = cpuid_edx(1);
kaf24@1452 624 if (!(features & (1 << X86_FEATURE_APIC))) {
kaf24@1452 625 printk("Could not enable APIC!\n");
kaf24@1452 626 return -1;
kaf24@1452 627 }
kaf24@4619 628
iap10@4548 629 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@1452 630 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
kaf24@1452 631
kaf24@1452 632 /* The BIOS may have set up the APIC at some other address */
kaf24@1452 633 rdmsr(MSR_IA32_APICBASE, l, h);
kaf24@1452 634 if (l & MSR_IA32_APICBASE_ENABLE)
kaf24@1452 635 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
kaf24@1452 636
kaf24@4619 637 if (nmi_watchdog != NMI_NONE)
kaf24@4619 638 nmi_watchdog = NMI_LOCAL_APIC;
kaf24@1452 639
kaf24@1452 640 printk("Found and enabled local APIC!\n");
iap10@4548 641
kaf24@8847 642 apic_pm_activate();
kaf24@8847 643
kaf24@1452 644 return 0;
kaf24@1452 645
iap10@4548 646 no_apic:
kaf24@1452 647 printk("No local APIC present or hardware disabled\n");
kaf24@1452 648 return -1;
kaf24@1452 649 }
kaf24@1452 650
kaf24@1452 651 void __init init_apic_mappings(void)
kaf24@1452 652 {
iap10@4548 653 unsigned long apic_phys;
kaf24@1452 654
kaf24@1452 655 /*
iap10@4548 656 * If no local APIC can be found then set up a fake all
iap10@4548 657 * zeroes page to simulate the local APIC and another
iap10@4548 658 * one for the IO-APIC.
kaf24@1452 659 */
kaf24@5398 660 if (!smp_found_config && detect_init_APIC())
kaf24@5398 661 apic_phys = __pa(alloc_xenheap_page());
kaf24@5398 662 else
kaf24@1452 663 apic_phys = mp_lapic_addr;
kaf24@1452 664
kaf24@1452 665 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
kaf24@4888 666 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
kaf24@4888 667 apic_phys);
kaf24@1452 668
kaf24@1452 669 /*
kaf24@1452 670 * Fetch the APIC ID of the BSP in case we have a
kaf24@1452 671 * default configuration (or the MP table is broken).
kaf24@1452 672 */
kaf24@1452 673 if (boot_cpu_physical_apicid == -1U)
kaf24@1452 674 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
kaf24@1452 675
kaf24@1452 676 #ifdef CONFIG_X86_IO_APIC
kaf24@1452 677 {
iap10@4548 678 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
kaf24@1452 679 int i;
kaf24@1452 680
kaf24@1452 681 for (i = 0; i < nr_ioapics; i++) {
iap10@4548 682 if (smp_found_config) {
kaf24@1452 683 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
iap10@4548 684 if (!ioapic_phys) {
iap10@4548 685 printk(KERN_ERR
iap10@4548 686 "WARNING: bogus zero IO-APIC "
iap10@4548 687 "address found in MPTABLE, "
iap10@4548 688 "disabling IO/APIC support!\n");
iap10@4548 689 smp_found_config = 0;
iap10@4548 690 skip_ioapic_setup = 1;
iap10@4548 691 goto fake_ioapic_page;
iap10@4548 692 }
iap10@4548 693 } else {
iap10@4548 694 fake_ioapic_page:
kaf24@5398 695 ioapic_phys = __pa(alloc_xenheap_page());
iap10@4548 696 }
kaf24@1452 697 set_fixmap_nocache(idx, ioapic_phys);
kaf24@4888 698 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
kaf24@4888 699 __fix_to_virt(idx), ioapic_phys);
kaf24@1452 700 idx++;
kaf24@1452 701 }
kaf24@1452 702 }
kaf24@1452 703 #endif
kaf24@1452 704 }
kaf24@1452 705
kaf24@1452 706 /*****************************************************************************
kaf24@1452 707 * APIC calibration
kaf24@1452 708 *
kaf24@1452 709 * The APIC is programmed in bus cycles.
kaf24@1452 710 * Timeout values should specified in real time units.
kaf24@1452 711 * The "cheapest" time source is the cyclecounter.
kaf24@1452 712 *
kaf24@1452 713 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
kaf24@1452 714 *
kaf24@1452 715 * The calibration is currently a bit shoddy since it requires the external
kaf24@1452 716 * timer chip to generate periodic timer interupts.
kaf24@1452 717 *****************************************************************************/
kaf24@1452 718
kaf24@1452 719 /* used for system time scaling */
kaf24@1672 720 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
kaf24@1672 721 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
kaf24@1672 722 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
kaf24@1452 723
kaf24@1452 724 /*
kaf24@1452 725 * The timer chip is already set up at HZ interrupts per second here,
kaf24@1452 726 * but we do not accept timer interrupts yet. We only allow the BP
kaf24@1452 727 * to calibrate.
kaf24@1452 728 */
kaf24@1452 729 static unsigned int __init get_8254_timer_count(void)
kaf24@1452 730 {
kaf24@1452 731 /*extern spinlock_t i8253_lock;*/
kaf24@1452 732 /*unsigned long flags;*/
iap10@4548 733
kaf24@1452 734 unsigned int count;
iap10@4548 735
kaf24@1452 736 /*spin_lock_irqsave(&i8253_lock, flags);*/
iap10@4548 737
iap10@4548 738 outb_p(0x00, PIT_MODE);
iap10@4548 739 count = inb_p(PIT_CH0);
iap10@4548 740 count |= inb_p(PIT_CH0) << 8;
iap10@4548 741
kaf24@1452 742 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
iap10@4548 743
kaf24@1452 744 return count;
kaf24@1452 745 }
kaf24@1452 746
iap10@4548 747 /* next tick in 8254 can be caught by catching timer wraparound */
iap10@4548 748 static void __init wait_8254_wraparound(void)
kaf24@1452 749 {
kaf24@4888 750 unsigned int curr_count, prev_count;
kaf24@4888 751
kaf24@1452 752 curr_count = get_8254_timer_count();
kaf24@1452 753 do {
kaf24@1452 754 prev_count = curr_count;
kaf24@1452 755 curr_count = get_8254_timer_count();
iap10@4548 756
kaf24@4888 757 /* workaround for broken Mercury/Neptune */
kaf24@4888 758 if (prev_count >= curr_count + 0x100)
kaf24@4888 759 curr_count = get_8254_timer_count();
kaf24@4888 760
kaf24@4888 761 } while (prev_count >= curr_count);
kaf24@1452 762 }
kaf24@1452 763
kaf24@1452 764 /*
iap10@4548 765 * Default initialization for 8254 timers. If we use other timers like HPET,
iap10@4548 766 * we override this later
iap10@4548 767 */
kaf24@4888 768 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
iap10@4548 769
iap10@4548 770 /*
kaf24@1452 771 * This function sets up the local APIC timer, with a timeout of
kaf24@1452 772 * 'clocks' APIC bus clock. During calibration we actually call
kaf24@4888 773 * this function twice on the boot CPU, once with a bogus timeout
kaf24@4888 774 * value, second time for real. The other (noncalibrating) CPUs
kaf24@4888 775 * call this function only once, with the real, calibrated value.
kaf24@1452 776 *
kaf24@1452 777 * We do reads before writes even if unnecessary, to get around the
kaf24@1452 778 * P5 APIC double write bug.
kaf24@1452 779 */
iap10@4548 780
kaf24@1452 781 #define APIC_DIVISOR 1
iap10@4548 782
kaf24@5146 783 void __setup_APIC_LVTT(unsigned int clocks)
kaf24@1452 784 {
iap10@4548 785 unsigned int lvtt_value, tmp_value, ver;
iap10@4548 786
iap10@4548 787 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
kaf24@4619 788 /* NB. Xen uses local APIC timer in one-shot mode. */
kaf24@4619 789 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
iap10@4548 790 if (!APIC_INTEGRATED(ver))
iap10@4548 791 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
iap10@4548 792 apic_write_around(APIC_LVTT, lvtt_value);
iap10@4548 793
kaf24@1452 794 tmp_value = apic_read(APIC_TDCR);
kaf24@1452 795 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
iap10@4548 796
kaf24@1452 797 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
kaf24@1452 798 }
kaf24@1452 799
kaf24@5146 800 static void __init setup_APIC_timer(unsigned int clocks)
kaf24@1452 801 {
kaf24@1452 802 unsigned long flags;
kaf24@5146 803 local_irq_save(flags);
kaf24@5146 804 __setup_APIC_LVTT(clocks);
kaf24@5146 805 local_irq_restore(flags);
kaf24@1452 806 }
kaf24@1452 807
kaf24@1452 808 /*
kaf24@5146 809 * In this function we calibrate APIC bus clocks to the external
kaf24@5146 810 * timer. Unfortunately we cannot use jiffies and the timer irq
kaf24@5146 811 * to calibrate, since some later bootup code depends on getting
kaf24@5146 812 * the first irq? Ugh.
kaf24@1452 813 *
kaf24@5146 814 * We want to do the calibration only once since we
kaf24@5146 815 * want to have local timer irqs syncron. CPUs connected
kaf24@5146 816 * by the same APIC bus have the very same bus frequency.
kaf24@5146 817 * And we want to have irqs off anyways, no accidental
kaf24@5146 818 * APIC irq that way.
kaf24@1452 819 */
kaf24@1452 820
kaf24@1452 821 int __init calibrate_APIC_clock(void)
kaf24@1452 822 {
kaf24@1452 823 unsigned long long t1 = 0, t2 = 0;
kaf24@1452 824 long tt1, tt2;
kaf24@1452 825 long result;
kaf24@1452 826 int i;
kaf24@1452 827 const int LOOPS = HZ/10;
kaf24@1452 828
kaf24@4888 829 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
kaf24@1452 830
iap10@4548 831 /*
iap10@4548 832 * Put whatever arbitrary (but long enough) timeout
kaf24@1452 833 * value into the APIC clock, we just want to get the
iap10@4548 834 * counter running for calibration.
iap10@4548 835 */
kaf24@1452 836 __setup_APIC_LVTT(1000000000);
kaf24@1452 837
iap10@4548 838 /*
iap10@4548 839 * The timer chip counts down to zero. Let's wait
kaf24@1452 840 * for a wraparound to start exact measurement:
iap10@4548 841 * (the current tick might have been already half done)
iap10@4548 842 */
iap10@4548 843 wait_timer_tick();
iap10@4548 844
iap10@4548 845 /*
iap10@4548 846 * We wrapped around just now. Let's start:
iap10@4548 847 */
iap10@4548 848 if (cpu_has_tsc)
kaf24@4619 849 rdtscll(t1);
kaf24@1452 850 tt1 = apic_read(APIC_TMCCT);
kaf24@1452 851
iap10@4548 852 /*
iap10@4548 853 * Let's wait LOOPS wraprounds:
iap10@4548 854 */
kaf24@1452 855 for (i = 0; i < LOOPS; i++)
iap10@4548 856 wait_timer_tick();
kaf24@1452 857
kaf24@1452 858 tt2 = apic_read(APIC_TMCCT);
iap10@4548 859 if (cpu_has_tsc)
kaf24@4619 860 rdtscll(t2);
kaf24@1452 861
iap10@4548 862 /*
iap10@4548 863 * The APIC bus clock counter is 32 bits only, it
kaf24@1452 864 * might have overflown, but note that we use signed
kaf24@1452 865 * longs, thus no extra care needed.
kaf24@4888 866 *
kaf24@4888 867 * underflown to be exact, as the timer counts down ;)
iap10@4548 868 */
iap10@4548 869
kaf24@1452 870 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
kaf24@1452 871
iap10@4548 872 if (cpu_has_tsc)
kaf24@4888 873 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
kaf24@4888 874 "%ld.%04ld MHz.\n",
kaf24@4888 875 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
kaf24@4888 876 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
kaf24@1452 877
kaf24@4888 878 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
kaf24@4888 879 "%ld.%04ld MHz.\n",
kaf24@4888 880 result/(1000000/HZ),
kaf24@4888 881 result%(1000000/HZ));
kaf24@1452 882
kaf24@1452 883 /* set up multipliers for accurate timer code */
kaf24@1452 884 bus_freq = result*HZ;
kaf24@1452 885 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
kaf24@1452 886 bus_scale = (1000*262144)/bus_cycle;
kaf24@1452 887
kaf24@4888 888 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
kaf24@1452 889 /* reset APIC to zero timeout value */
kaf24@1452 890 __setup_APIC_LVTT(0);
iap10@4548 891
kaf24@1452 892 return result;
kaf24@1452 893 }
kaf24@1452 894
kaf24@7546 895 unsigned int get_apic_bus_scale(void)
kaf24@7546 896 {
kaf24@7546 897 return bus_scale;
kaf24@7546 898 }
kaf24@5146 899
kaf24@5146 900 static unsigned int calibration_result;
kaf24@5146 901
kaf24@5146 902 void __init setup_boot_APIC_clock(void)
kaf24@1452 903 {
kaf24@8847 904 unsigned long flags;
kaf24@5146 905 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
kaf24@1452 906 using_apic_timer = 1;
kaf24@5146 907
kaf24@8847 908 local_irq_save(flags);
kaf24@8847 909
kaf24@5146 910 calibration_result = calibrate_APIC_clock();
kaf24@5146 911 /*
kaf24@5146 912 * Now set up the timer for real.
kaf24@5146 913 */
kaf24@5146 914 setup_APIC_timer(calibration_result);
kaf24@5146 915
kaf24@8847 916 local_irq_restore(flags);
kaf24@5146 917 }
kaf24@5146 918
kaf24@8847 919 void __devinit setup_secondary_APIC_clock(void)
kaf24@5146 920 {
kaf24@5146 921 setup_APIC_timer(calibration_result);
kaf24@5146 922 }
kaf24@5146 923
kaf24@8847 924 void disable_APIC_timer(void)
kaf24@5146 925 {
kaf24@5146 926 if (using_apic_timer) {
kaf24@5146 927 unsigned long v;
kaf24@5146 928
kaf24@5146 929 v = apic_read(APIC_LVTT);
kaf24@5146 930 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
kaf24@5146 931 }
kaf24@5146 932 }
kaf24@5146 933
kaf24@5146 934 void enable_APIC_timer(void)
kaf24@5146 935 {
kaf24@5146 936 if (using_apic_timer) {
kaf24@5146 937 unsigned long v;
kaf24@5146 938
kaf24@5146 939 v = apic_read(APIC_LVTT);
kaf24@5146 940 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
kaf24@5146 941 }
kaf24@1452 942 }
kaf24@1452 943
kaf24@1452 944 #undef APIC_DIVISOR
kaf24@1452 945
kaf24@1452 946 /*
kaf24@1452 947 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
kaf24@1452 948 * returns 1 on success
kaf24@1452 949 * returns 0 if the timeout value is too small or in the past.
kaf24@1452 950 */
kaf24@8586 951 int reprogram_timer(s_time_t timeout)
kaf24@1452 952 {
kaf24@1452 953 s_time_t now;
kaf24@1452 954 s_time_t expire;
kaf24@1452 955 u64 apic_tmict;
kaf24@1452 956
kaf24@1452 957 /*
kaf24@1452 958 * We use this value because we don't trust zero (we think it may just
kaf24@1452 959 * cause an immediate interrupt). At least this is guaranteed to hold it
kaf24@1452 960 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
kaf24@1452 961 */
kaf24@1452 962 if ( timeout == 0 )
kaf24@1452 963 {
kaf24@1452 964 apic_tmict = 0xffffffff;
kaf24@1452 965 goto reprogram;
kaf24@1452 966 }
kaf24@1452 967
kaf24@1452 968 now = NOW();
kaf24@1452 969 expire = timeout - now; /* value from now */
kaf24@1452 970
kaf24@1452 971 if ( expire <= 0 )
kaf24@1452 972 {
kaf24@1452 973 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
kaf24@1452 974 smp_processor_id(), (u32)(now>>32),
kaf24@1452 975 (u32)now, (u32)(timeout>>32),(u32)timeout);
kaf24@1452 976 return 0;
kaf24@1452 977 }
kaf24@1452 978
kaf24@1452 979 /*
kaf24@1452 980 * If we don't have local APIC then we just poll the timer list off the
kaf24@1452 981 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
kaf24@1452 982 */
kaf24@1452 983 if ( !cpu_has_apic )
kaf24@1452 984 return 1;
kaf24@1452 985
kaf24@1452 986 /* conversion to bus units */
kaf24@1452 987 apic_tmict = (((u64)bus_scale) * expire)>>18;
kaf24@1452 988
kaf24@1452 989 if ( apic_tmict >= 0xffffffff )
kaf24@1452 990 {
kaf24@1452 991 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
kaf24@1452 992 apic_tmict = 0xffffffff;
kaf24@1452 993 }
kaf24@1452 994
kaf24@1452 995 if ( apic_tmict == 0 )
kaf24@1452 996 {
kaf24@1452 997 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
kaf24@1452 998 return 0;
kaf24@1452 999 }
kaf24@1452 1000
kaf24@1452 1001 reprogram:
kaf24@1452 1002 /* Program the timer. */
kaf24@1452 1003 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
kaf24@1452 1004
kaf24@1452 1005 return 1;
kaf24@1452 1006 }
kaf24@1452 1007
kaf24@8846 1008 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
kaf24@1452 1009 {
kaf24@1452 1010 ack_APIC_irq();
kaf24@1452 1011 perfc_incrc(apic_timer);
kaf24@8586 1012 raise_softirq(TIMER_SOFTIRQ);
kaf24@1452 1013 }
kaf24@1452 1014
kaf24@1452 1015 /*
kaf24@1452 1016 * This interrupt should _never_ happen with our APIC/SMP architecture
kaf24@1452 1017 */
kaf24@8846 1018 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1019 {
kaf24@1452 1020 unsigned long v;
kaf24@1452 1021
kaf24@8847 1022 irq_enter();
kaf24@1452 1023 /*
kaf24@1452 1024 * Check if this really is a spurious interrupt and ACK it
kaf24@1452 1025 * if it is a vectored one. Just in case...
kaf24@1452 1026 * Spurious interrupts should not be ACKed.
kaf24@1452 1027 */
kaf24@1452 1028 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
kaf24@1452 1029 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
kaf24@1452 1030 ack_APIC_irq();
kaf24@1452 1031
kaf24@1452 1032 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
kaf24@5146 1033 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
kaf24@1452 1034 smp_processor_id());
kaf24@8847 1035 irq_exit();
kaf24@1452 1036 }
kaf24@1452 1037
kaf24@1452 1038 /*
kaf24@1452 1039 * This interrupt should never happen with our APIC/SMP architecture
kaf24@1452 1040 */
kaf24@1452 1041
kaf24@8846 1042 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
kaf24@1452 1043 {
kaf24@1452 1044 unsigned long v, v1;
kaf24@1452 1045
kaf24@8847 1046 irq_enter();
kaf24@1452 1047 /* First tickle the hardware, only then report what went on. -- REW */
kaf24@1452 1048 v = apic_read(APIC_ESR);
kaf24@1452 1049 apic_write(APIC_ESR, 0);
kaf24@1452 1050 v1 = apic_read(APIC_ESR);
kaf24@1452 1051 ack_APIC_irq();
kaf24@1452 1052 atomic_inc(&irq_err_count);
kaf24@1452 1053
kaf24@1452 1054 /* Here is what the APIC error bits mean:
kaf24@1452 1055 0: Send CS error
kaf24@1452 1056 1: Receive CS error
kaf24@1452 1057 2: Send accept error
kaf24@1452 1058 3: Receive accept error
kaf24@1452 1059 4: Reserved
kaf24@1452 1060 5: Send illegal vector
kaf24@1452 1061 6: Received illegal vector
kaf24@1452 1062 7: Illegal register address
kaf24@1452 1063 */
kaf24@5146 1064 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
kaf24@5146 1065 smp_processor_id(), v , v1);
kaf24@8847 1066 irq_exit();
kaf24@1452 1067 }
kaf24@1452 1068
kaf24@1452 1069 /*
kaf24@1452 1070 * This initializes the IO-APIC and APIC hardware if this is
kaf24@1452 1071 * a UP kernel.
kaf24@1452 1072 */
kaf24@1452 1073 int __init APIC_init_uniprocessor (void)
kaf24@1452 1074 {
kaf24@5211 1075 if (enable_local_apic < 0)
kaf24@5211 1076 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
kaf24@5211 1077
kaf24@1452 1078 if (!smp_found_config && !cpu_has_apic)
kaf24@1452 1079 return -1;
kaf24@1452 1080
kaf24@1452 1081 /*
kaf24@1452 1082 * Complain if the BIOS pretends there is one.
kaf24@1452 1083 */
iap10@4548 1084 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
kaf24@4888 1085 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
kaf24@1452 1086 boot_cpu_physical_apicid);
kaf24@1452 1087 return -1;
kaf24@1452 1088 }
kaf24@1452 1089
kaf24@1452 1090 verify_local_APIC();
kaf24@1452 1091
kaf24@1452 1092 connect_bsp_APIC();
kaf24@1452 1093
kaf24@4804 1094 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
kaf24@1452 1095
kaf24@1452 1096 setup_local_APIC();
kaf24@1452 1097
kaf24@5146 1098 if (nmi_watchdog == NMI_LOCAL_APIC)
kaf24@5146 1099 check_nmi_watchdog();
kaf24@1452 1100 #ifdef CONFIG_X86_IO_APIC
iap10@4548 1101 if (smp_found_config)
iap10@4548 1102 if (!skip_ioapic_setup && nr_ioapics)
kaf24@4619 1103 setup_IO_APIC();
iap10@4548 1104 #endif
kaf24@5146 1105 setup_boot_APIC_clock();
kaf24@1452 1106
kaf24@1452 1107 return 0;
kaf24@1452 1108 }