ia64/xen-unstable

annotate xen/include/asm-ia64/xenprocessor.h @ 5046:0554a6615257

bitkeeper revision 1.1389.23.4 (428e13b9Hne7WMFOPqv3id1PNB6EYg)

- CONFIG_VTI=n by default.
- Reorganize code such that the changes to cp_patch files are minimized

Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author adsharma@linux-t08.sc.intel.com
date Fri May 20 16:43:37 2005 +0000 (2005-05-20)
parents
children 541012edd6e5
rev   line source
adsharma@5046 1 #ifndef _ASM_IA64_XENPROCESSOR_H
adsharma@5046 2 #define _ASM_IA64_XENPROCESSOR_H
adsharma@5046 3 /*
adsharma@5046 4 * xen specific processor definition
adsharma@5046 5 *
adsharma@5046 6 * Copyright (C) 2005 Hewlett-Packard Co.
adsharma@5046 7 * Dan Magenheimer (dan.magenheimer@hp.com)
adsharma@5046 8 *
adsharma@5046 9 * Copyright (C) 2005 Intel Co.
adsharma@5046 10 * Kun Tian (Kevin Tian) <kevin.tian@intel.com>
adsharma@5046 11 *
adsharma@5046 12 */
adsharma@5046 13
adsharma@5046 14
adsharma@5046 15 #define ia64_is_local_fpu_owner(t) 0
adsharma@5046 16
adsharma@5046 17 /* like above but expressed as bitfields for more efficient access: */
adsharma@5046 18 struct ia64_psr {
adsharma@5046 19 __u64 reserved0 : 1;
adsharma@5046 20 __u64 be : 1;
adsharma@5046 21 __u64 up : 1;
adsharma@5046 22 __u64 ac : 1;
adsharma@5046 23 __u64 mfl : 1;
adsharma@5046 24 __u64 mfh : 1;
adsharma@5046 25 __u64 reserved1 : 7;
adsharma@5046 26 __u64 ic : 1;
adsharma@5046 27 __u64 i : 1;
adsharma@5046 28 __u64 pk : 1;
adsharma@5046 29 __u64 reserved2 : 1;
adsharma@5046 30 __u64 dt : 1;
adsharma@5046 31 __u64 dfl : 1;
adsharma@5046 32 __u64 dfh : 1;
adsharma@5046 33 __u64 sp : 1;
adsharma@5046 34 __u64 pp : 1;
adsharma@5046 35 __u64 di : 1;
adsharma@5046 36 __u64 si : 1;
adsharma@5046 37 __u64 db : 1;
adsharma@5046 38 __u64 lp : 1;
adsharma@5046 39 __u64 tb : 1;
adsharma@5046 40 __u64 rt : 1;
adsharma@5046 41 __u64 reserved3 : 4;
adsharma@5046 42 __u64 cpl : 2;
adsharma@5046 43 __u64 is : 1;
adsharma@5046 44 __u64 mc : 1;
adsharma@5046 45 __u64 it : 1;
adsharma@5046 46 __u64 id : 1;
adsharma@5046 47 __u64 da : 1;
adsharma@5046 48 __u64 dd : 1;
adsharma@5046 49 __u64 ss : 1;
adsharma@5046 50 __u64 ri : 2;
adsharma@5046 51 __u64 ed : 1;
adsharma@5046 52 __u64 bn : 1;
adsharma@5046 53 #ifdef CONFIG_VTI
adsharma@5046 54 __u64 ia : 1;
adsharma@5046 55 __u64 vm : 1;
adsharma@5046 56 __u64 reserved5 : 17;
adsharma@5046 57 #else // CONFIG_VTI
adsharma@5046 58 __u64 reserved4 : 19;
adsharma@5046 59 #endif // CONFIG_VTI
adsharma@5046 60 };
adsharma@5046 61
adsharma@5046 62 #ifdef CONFIG_VTI
adsharma@5046 63 /* vmx like above but expressed as bitfields for more efficient access: */
adsharma@5046 64 typedef union{
adsharma@5046 65 __u64 val;
adsharma@5046 66 struct{
adsharma@5046 67 __u64 reserved0 : 1;
adsharma@5046 68 __u64 be : 1;
adsharma@5046 69 __u64 up : 1;
adsharma@5046 70 __u64 ac : 1;
adsharma@5046 71 __u64 mfl : 1;
adsharma@5046 72 __u64 mfh : 1;
adsharma@5046 73 __u64 reserved1 : 7;
adsharma@5046 74 __u64 ic : 1;
adsharma@5046 75 __u64 i : 1;
adsharma@5046 76 __u64 pk : 1;
adsharma@5046 77 __u64 reserved2 : 1;
adsharma@5046 78 __u64 dt : 1;
adsharma@5046 79 __u64 dfl : 1;
adsharma@5046 80 __u64 dfh : 1;
adsharma@5046 81 __u64 sp : 1;
adsharma@5046 82 __u64 pp : 1;
adsharma@5046 83 __u64 di : 1;
adsharma@5046 84 __u64 si : 1;
adsharma@5046 85 __u64 db : 1;
adsharma@5046 86 __u64 lp : 1;
adsharma@5046 87 __u64 tb : 1;
adsharma@5046 88 __u64 rt : 1;
adsharma@5046 89 __u64 reserved3 : 4;
adsharma@5046 90 __u64 cpl : 2;
adsharma@5046 91 __u64 is : 1;
adsharma@5046 92 __u64 mc : 1;
adsharma@5046 93 __u64 it : 1;
adsharma@5046 94 __u64 id : 1;
adsharma@5046 95 __u64 da : 1;
adsharma@5046 96 __u64 dd : 1;
adsharma@5046 97 __u64 ss : 1;
adsharma@5046 98 __u64 ri : 2;
adsharma@5046 99 __u64 ed : 1;
adsharma@5046 100 __u64 bn : 1;
adsharma@5046 101 __u64 reserved4 : 19;
adsharma@5046 102 };
adsharma@5046 103 } IA64_PSR;
adsharma@5046 104
adsharma@5046 105 typedef union {
adsharma@5046 106 __u64 val;
adsharma@5046 107 struct {
adsharma@5046 108 __u64 code : 16;
adsharma@5046 109 __u64 vector : 8;
adsharma@5046 110 __u64 reserved1 : 8;
adsharma@5046 111 __u64 x : 1;
adsharma@5046 112 __u64 w : 1;
adsharma@5046 113 __u64 r : 1;
adsharma@5046 114 __u64 na : 1;
adsharma@5046 115 __u64 sp : 1;
adsharma@5046 116 __u64 rs : 1;
adsharma@5046 117 __u64 ir : 1;
adsharma@5046 118 __u64 ni : 1;
adsharma@5046 119 __u64 so : 1;
adsharma@5046 120 __u64 ei : 2;
adsharma@5046 121 __u64 ed : 1;
adsharma@5046 122 __u64 reserved2 : 20;
adsharma@5046 123 };
adsharma@5046 124 } ISR;
adsharma@5046 125
adsharma@5046 126
adsharma@5046 127 typedef union {
adsharma@5046 128 __u64 val;
adsharma@5046 129 struct {
adsharma@5046 130 __u64 ve : 1;
adsharma@5046 131 __u64 reserved0 : 1;
adsharma@5046 132 __u64 size : 6;
adsharma@5046 133 __u64 vf : 1;
adsharma@5046 134 __u64 reserved1 : 6;
adsharma@5046 135 __u64 base : 49;
adsharma@5046 136 };
adsharma@5046 137 } PTA;
adsharma@5046 138
adsharma@5046 139 typedef union {
adsharma@5046 140 __u64 val;
adsharma@5046 141 struct {
adsharma@5046 142 __u64 rv : 16;
adsharma@5046 143 __u64 eid : 8;
adsharma@5046 144 __u64 id : 8;
adsharma@5046 145 __u64 ig : 32;
adsharma@5046 146 };
adsharma@5046 147 } LID;
adsharma@5046 148
adsharma@5046 149 typedef union{
adsharma@5046 150 __u64 val;
adsharma@5046 151 struct {
adsharma@5046 152 __u64 rv : 3;
adsharma@5046 153 __u64 ir : 1;
adsharma@5046 154 __u64 eid : 8;
adsharma@5046 155 __u64 id : 8;
adsharma@5046 156 __u64 ib_base : 44;
adsharma@5046 157 };
adsharma@5046 158 } ipi_a_t;
adsharma@5046 159
adsharma@5046 160 typedef union{
adsharma@5046 161 __u64 val;
adsharma@5046 162 struct {
adsharma@5046 163 __u64 vector : 8;
adsharma@5046 164 __u64 dm : 3;
adsharma@5046 165 __u64 ig : 53;
adsharma@5046 166 };
adsharma@5046 167 } ipi_d_t;
adsharma@5046 168
adsharma@5046 169
adsharma@5046 170 #define IA64_ISR_CODE_MASK0 0xf
adsharma@5046 171 #define IA64_UNIMPL_DADDR_FAULT 0x30
adsharma@5046 172 #define IA64_UNIMPL_IADDR_TRAP 0x10
adsharma@5046 173 #define IA64_RESERVED_REG_FAULT 0x30
adsharma@5046 174 #define IA64_REG_NAT_CONSUMPTION_FAULT 0x10
adsharma@5046 175 #define IA64_NAT_CONSUMPTION_FAULT 0x20
adsharma@5046 176 #define IA64_PRIV_OP_FAULT 0x10
adsharma@5046 177
adsharma@5046 178 /* indirect register type */
adsharma@5046 179 enum {
adsharma@5046 180 IA64_CPUID, /* cpuid */
adsharma@5046 181 IA64_DBR, /* dbr */
adsharma@5046 182 IA64_IBR, /* ibr */
adsharma@5046 183 IA64_PKR, /* pkr */
adsharma@5046 184 IA64_PMC, /* pmc */
adsharma@5046 185 IA64_PMD, /* pmd */
adsharma@5046 186 IA64_RR /* rr */
adsharma@5046 187 };
adsharma@5046 188
adsharma@5046 189 /* instruction type */
adsharma@5046 190 enum {
adsharma@5046 191 IA64_INST_TPA=1,
adsharma@5046 192 IA64_INST_TAK
adsharma@5046 193 };
adsharma@5046 194
adsharma@5046 195 /* Generate Mask
adsharma@5046 196 * Parameter:
adsharma@5046 197 * bit -- starting bit
adsharma@5046 198 * len -- how many bits
adsharma@5046 199 */
adsharma@5046 200 #define MASK(bit,len) \
adsharma@5046 201 ({ \
adsharma@5046 202 __u64 ret; \
adsharma@5046 203 \
adsharma@5046 204 __asm __volatile("dep %0=-1, r0, %1, %2" \
adsharma@5046 205 : "=r" (ret): \
adsharma@5046 206 "M" (bit), \
adsharma@5046 207 "M" (len) ); \
adsharma@5046 208 ret; \
adsharma@5046 209 })
adsharma@5046 210
adsharma@5046 211 #endif // CONFIG_VTI
adsharma@5046 212
adsharma@5046 213 #endif // _ASM_IA64_XENPROCESSOR_H