ia64/linux-2.6.18-xen.hg

changeset 693:fe3cd38ff06a

Import upstream git commit b4af3f7cf11e6b5904af08a652d4a2429af17c74

[PATCH] i386: mark cpu init functions as __cpuinit, data as
__cpuinitdata

Mark i386-specific cpu init functions as __cpuinit. They are all
only called from arch/i386/common.c:identify_cpu() that already is
marked as __cpuinit. This patch also removes the empty function
init_umc().

Signed-off-by: Magnus Damm <magnus@valinux.co.jp>
Signed-off-by: Andi Kleen <ak@suse.de>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Oct 08 14:13:28 2008 +0100 (2008-10-08)
parents 18f976ebc870
children 92094d768241
files arch/i386/kernel/cpu/amd.c arch/i386/kernel/cpu/centaur.c arch/i386/kernel/cpu/common.c arch/i386/kernel/cpu/cyrix.c arch/i386/kernel/cpu/nexgen.c arch/i386/kernel/cpu/rise.c arch/i386/kernel/cpu/transmeta.c arch/i386/kernel/cpu/umc.c
line diff
     1.1 --- a/arch/i386/kernel/cpu/amd.c	Wed Oct 08 14:12:45 2008 +0100
     1.2 +++ b/arch/i386/kernel/cpu/amd.c	Wed Oct 08 14:13:28 2008 +0100
     1.3 @@ -22,7 +22,7 @@
     1.4  extern void vide(void);
     1.5  __asm__(".align 4\nvide: ret");
     1.6  
     1.7 -static void __init init_amd(struct cpuinfo_x86 *c)
     1.8 +static void __cpuinit init_amd(struct cpuinfo_x86 *c)
     1.9  {
    1.10  	u32 l, h;
    1.11  	int mbytes = num_physpages >> (20-PAGE_SHIFT);
     2.1 --- a/arch/i386/kernel/cpu/centaur.c	Wed Oct 08 14:12:45 2008 +0100
     2.2 +++ b/arch/i386/kernel/cpu/centaur.c	Wed Oct 08 14:13:28 2008 +0100
     2.3 @@ -9,7 +9,7 @@
     2.4  
     2.5  #ifdef CONFIG_X86_OOSTORE
     2.6  
     2.7 -static u32 __init power2(u32 x)
     2.8 +static u32 __cpuinit power2(u32 x)
     2.9  {
    2.10  	u32 s=1;
    2.11  	while(s<=x)
    2.12 @@ -22,7 +22,7 @@ static u32 __init power2(u32 x)
    2.13   *	Set up an actual MCR
    2.14   */
    2.15   
    2.16 -static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key)
    2.17 +static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
    2.18  {
    2.19  	u32 lo, hi;
    2.20  	
    2.21 @@ -40,7 +40,7 @@ static void __init centaur_mcr_insert(in
    2.22   *	Shortcut: We know you can't put 4Gig of RAM on a winchip
    2.23   */
    2.24  
    2.25 -static u32 __init ramtop(void)		/* 16388 */
    2.26 +static u32 __cpuinit ramtop(void)		/* 16388 */
    2.27  {
    2.28  	int i;
    2.29  	u32 top = 0;
    2.30 @@ -91,7 +91,7 @@ static u32 __init ramtop(void)		/* 16388
    2.31   *	Compute a set of MCR's to give maximum coverage
    2.32   */
    2.33  
    2.34 -static int __init centaur_mcr_compute(int nr, int key)
    2.35 +static int __cpuinit centaur_mcr_compute(int nr, int key)
    2.36  {
    2.37  	u32 mem = ramtop();
    2.38  	u32 root = power2(mem);
    2.39 @@ -166,7 +166,7 @@ static int __init centaur_mcr_compute(in
    2.40  	return ct;
    2.41  }
    2.42  
    2.43 -static void __init centaur_create_optimal_mcr(void)
    2.44 +static void __cpuinit centaur_create_optimal_mcr(void)
    2.45  {
    2.46  	int i;
    2.47  	/*
    2.48 @@ -189,7 +189,7 @@ static void __init centaur_create_optima
    2.49  		wrmsr(MSR_IDT_MCR0+i, 0, 0);
    2.50  }
    2.51  
    2.52 -static void __init winchip2_create_optimal_mcr(void)
    2.53 +static void __cpuinit winchip2_create_optimal_mcr(void)
    2.54  {
    2.55  	u32 lo, hi;
    2.56  	int i;
    2.57 @@ -227,7 +227,7 @@ static void __init winchip2_create_optim
    2.58   *	Handle the MCR key on the Winchip 2.
    2.59   */
    2.60  
    2.61 -static void __init winchip2_unprotect_mcr(void)
    2.62 +static void __cpuinit winchip2_unprotect_mcr(void)
    2.63  {
    2.64  	u32 lo, hi;
    2.65  	u32 key;
    2.66 @@ -239,7 +239,7 @@ static void __init winchip2_unprotect_mc
    2.67  	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
    2.68  }
    2.69  
    2.70 -static void __init winchip2_protect_mcr(void)
    2.71 +static void __cpuinit winchip2_protect_mcr(void)
    2.72  {
    2.73  	u32 lo, hi;
    2.74  	
    2.75 @@ -257,7 +257,7 @@ static void __init winchip2_protect_mcr(
    2.76  #define RNG_ENABLED	(1 << 3)
    2.77  #define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */
    2.78  
    2.79 -static void __init init_c3(struct cpuinfo_x86 *c)
    2.80 +static void __cpuinit init_c3(struct cpuinfo_x86 *c)
    2.81  {
    2.82  	u32  lo, hi;
    2.83  
    2.84 @@ -303,7 +303,7 @@ static void __init init_c3(struct cpuinf
    2.85  	display_cacheinfo(c);
    2.86  }
    2.87  
    2.88 -static void __init init_centaur(struct cpuinfo_x86 *c)
    2.89 +static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
    2.90  {
    2.91  	enum {
    2.92  		ECX8=1<<1,
     3.1 --- a/arch/i386/kernel/cpu/common.c	Wed Oct 08 14:12:45 2008 +0100
     3.2 +++ b/arch/i386/kernel/cpu/common.c	Wed Oct 08 14:13:28 2008 +0100
     3.3 @@ -36,7 +36,7 @@ struct cpu_dev * cpu_devs[X86_VENDOR_NUM
     3.4  
     3.5  extern int disable_pse;
     3.6  
     3.7 -static void default_init(struct cpuinfo_x86 * c)
     3.8 +static void __cpuinit default_init(struct cpuinfo_x86 * c)
     3.9  {
    3.10  	/* Not much we can do here... */
    3.11  	/* Check if at least it has cpuid */
     4.1 --- a/arch/i386/kernel/cpu/cyrix.c	Wed Oct 08 14:12:45 2008 +0100
     4.2 +++ b/arch/i386/kernel/cpu/cyrix.c	Wed Oct 08 14:13:28 2008 +0100
     4.3 @@ -52,25 +52,25 @@ static void __init do_cyrix_devid(unsign
     4.4   * Actually since bugs.h doesn't even reference this perhaps someone should
     4.5   * fix the documentation ???
     4.6   */
     4.7 -static unsigned char Cx86_dir0_msb __initdata = 0;
     4.8 +static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
     4.9  
    4.10 -static char Cx86_model[][9] __initdata = {
    4.11 +static char Cx86_model[][9] __cpuinitdata = {
    4.12  	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
    4.13  	"M II ", "Unknown"
    4.14  };
    4.15 -static char Cx486_name[][5] __initdata = {
    4.16 +static char Cx486_name[][5] __cpuinitdata = {
    4.17  	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
    4.18  	"SRx2", "DRx2"
    4.19  };
    4.20 -static char Cx486S_name[][4] __initdata = {
    4.21 +static char Cx486S_name[][4] __cpuinitdata = {
    4.22  	"S", "S2", "Se", "S2e"
    4.23  };
    4.24 -static char Cx486D_name[][4] __initdata = {
    4.25 +static char Cx486D_name[][4] __cpuinitdata = {
    4.26  	"DX", "DX2", "?", "?", "?", "DX4"
    4.27  };
    4.28 -static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";
    4.29 -static char cyrix_model_mult1[] __initdata = "12??43";
    4.30 -static char cyrix_model_mult2[] __initdata = "12233445";
    4.31 +static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
    4.32 +static char cyrix_model_mult1[] __cpuinitdata = "12??43";
    4.33 +static char cyrix_model_mult2[] __cpuinitdata = "12233445";
    4.34  
    4.35  /*
    4.36   * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
    4.37 @@ -82,7 +82,7 @@ static char cyrix_model_mult2[] __initda
    4.38  
    4.39  extern void calibrate_delay(void) __init;
    4.40  
    4.41 -static void __init check_cx686_slop(struct cpuinfo_x86 *c)
    4.42 +static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
    4.43  {
    4.44  	unsigned long flags;
    4.45  	
    4.46 @@ -107,7 +107,7 @@ static void __init check_cx686_slop(stru
    4.47  }
    4.48  
    4.49  
    4.50 -static void __init set_cx86_reorder(void)
    4.51 +static void __cpuinit set_cx86_reorder(void)
    4.52  {
    4.53  	u8 ccr3;
    4.54  
    4.55 @@ -122,7 +122,7 @@ static void __init set_cx86_reorder(void
    4.56  	setCx86(CX86_CCR3, ccr3);
    4.57  }
    4.58  
    4.59 -static void __init set_cx86_memwb(void)
    4.60 +static void __cpuinit set_cx86_memwb(void)
    4.61  {
    4.62  	u32 cr0;
    4.63  
    4.64 @@ -137,7 +137,7 @@ static void __init set_cx86_memwb(void)
    4.65  	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
    4.66  }
    4.67  
    4.68 -static void __init set_cx86_inc(void)
    4.69 +static void __cpuinit set_cx86_inc(void)
    4.70  {
    4.71  	unsigned char ccr3;
    4.72  
    4.73 @@ -158,7 +158,7 @@ static void __init set_cx86_inc(void)
    4.74   *	Configure later MediaGX and/or Geode processor.
    4.75   */
    4.76  
    4.77 -static void __init geode_configure(void)
    4.78 +static void __cpuinit geode_configure(void)
    4.79  {
    4.80  	unsigned long flags;
    4.81  	u8 ccr3, ccr4;
    4.82 @@ -184,14 +184,14 @@ static void __init geode_configure(void)
    4.83  
    4.84  
    4.85  #ifdef CONFIG_PCI
    4.86 -static struct pci_device_id __initdata cyrix_55x0[] = {
    4.87 +static struct pci_device_id __cpuinitdata cyrix_55x0[] = {
    4.88  	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },
    4.89  	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },
    4.90  	{ },
    4.91  };
    4.92  #endif
    4.93  
    4.94 -static void __init init_cyrix(struct cpuinfo_x86 *c)
    4.95 +static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
    4.96  {
    4.97  	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
    4.98  	char *buf = c->x86_model_id;
    4.99 @@ -346,7 +346,7 @@ static void __init init_cyrix(struct cpu
   4.100  /*
   4.101   * Handle National Semiconductor branded processors
   4.102   */
   4.103 -static void __init init_nsc(struct cpuinfo_x86 *c)
   4.104 +static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
   4.105  {
   4.106  	/* There may be GX1 processors in the wild that are branded
   4.107  	 * NSC and not Cyrix.
     5.1 --- a/arch/i386/kernel/cpu/nexgen.c	Wed Oct 08 14:12:45 2008 +0100
     5.2 +++ b/arch/i386/kernel/cpu/nexgen.c	Wed Oct 08 14:13:28 2008 +0100
     5.3 @@ -27,7 +27,7 @@ static int __init deep_magic_nexgen_prob
     5.4  	return  ret;
     5.5  }
     5.6  
     5.7 -static void __init init_nexgen(struct cpuinfo_x86 * c)
     5.8 +static void __cpuinit init_nexgen(struct cpuinfo_x86 * c)
     5.9  {
    5.10  	c->x86_cache_size = 256; /* A few had 1 MB... */
    5.11  }
     6.1 --- a/arch/i386/kernel/cpu/rise.c	Wed Oct 08 14:12:45 2008 +0100
     6.2 +++ b/arch/i386/kernel/cpu/rise.c	Wed Oct 08 14:13:28 2008 +0100
     6.3 @@ -5,7 +5,7 @@
     6.4  
     6.5  #include "cpu.h"
     6.6  
     6.7 -static void __init init_rise(struct cpuinfo_x86 *c)
     6.8 +static void __cpuinit init_rise(struct cpuinfo_x86 *c)
     6.9  {
    6.10  	printk("CPU: Rise iDragon");
    6.11  	if (c->x86_model > 2)
     7.1 --- a/arch/i386/kernel/cpu/transmeta.c	Wed Oct 08 14:12:45 2008 +0100
     7.2 +++ b/arch/i386/kernel/cpu/transmeta.c	Wed Oct 08 14:13:28 2008 +0100
     7.3 @@ -5,7 +5,7 @@
     7.4  #include <asm/msr.h>
     7.5  #include "cpu.h"
     7.6  
     7.7 -static void __init init_transmeta(struct cpuinfo_x86 *c)
     7.8 +static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
     7.9  {
    7.10  	unsigned int cap_mask, uk, max, dummy;
    7.11  	unsigned int cms_rev1, cms_rev2;
     8.1 --- a/arch/i386/kernel/cpu/umc.c	Wed Oct 08 14:12:45 2008 +0100
     8.2 +++ b/arch/i386/kernel/cpu/umc.c	Wed Oct 08 14:13:28 2008 +0100
     8.3 @@ -5,10 +5,6 @@
     8.4  
     8.5  /* UMC chips appear to be only either 386 or 486, so no special init takes place.
     8.6   */
     8.7 -static void __init init_umc(struct cpuinfo_x86 * c)
     8.8 -{
     8.9 -
    8.10 -}
    8.11  
    8.12  static struct cpu_dev umc_cpu_dev __cpuinitdata = {
    8.13  	.c_vendor	= "UMC",
    8.14 @@ -21,7 +17,6 @@ static struct cpu_dev umc_cpu_dev __cpui
    8.15  		  }
    8.16  		},
    8.17  	},
    8.18 -	.c_init		= init_umc,
    8.19  };
    8.20  
    8.21  int __init umc_init_cpu(void)