ia64/linux-2.6.18-xen.hg

changeset 796:f0db1ac7ca8d

Add the igb driver for dom0

backport the driver from RHEL5.3 and make it work.

signed-off-by: Zhang Yang <yang.zhang@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Feb 17 11:25:51 2009 +0000 (2009-02-17)
parents 2ee6febdd4f9
children 2f1b770d84e5
files arch/i386/defconfig arch/ia64/defconfig arch/x86_64/defconfig drivers/net/Kconfig drivers/net/Makefile drivers/net/igb/Makefile drivers/net/igb/e1000_82575.c drivers/net/igb/e1000_82575.h drivers/net/igb/e1000_defines.h drivers/net/igb/e1000_hw.h drivers/net/igb/e1000_mac.c drivers/net/igb/e1000_mac.h drivers/net/igb/e1000_nvm.c drivers/net/igb/e1000_nvm.h drivers/net/igb/e1000_phy.c drivers/net/igb/e1000_phy.h drivers/net/igb/e1000_regs.h drivers/net/igb/igb.h drivers/net/igb/igb_compat.h drivers/net/igb/igb_ethtool.c drivers/net/igb/igb_main.c
line diff
     1.1 --- a/arch/i386/defconfig	Tue Feb 17 11:25:22 2009 +0000
     1.2 +++ b/arch/i386/defconfig	Tue Feb 17 11:25:51 2009 +0000
     1.3 @@ -693,6 +693,7 @@ CONFIG_E100=y
     1.4  # CONFIG_VIA_VELOCITY is not set
     1.5  # CONFIG_TIGON3 is not set
     1.6  # CONFIG_BNX2 is not set
     1.7 +# CONFIG_IGB is not set
     1.8  
     1.9  #
    1.10  # Ethernet (10000 Mbit)
     2.1 --- a/arch/ia64/defconfig	Tue Feb 17 11:25:22 2009 +0000
     2.2 +++ b/arch/ia64/defconfig	Tue Feb 17 11:25:51 2009 +0000
     2.3 @@ -607,6 +607,7 @@ CONFIG_E1000E=y
     2.4  # CONFIG_SK98LIN is not set
     2.5  # CONFIG_VIA_VELOCITY is not set
     2.6  CONFIG_TIGON3=y
     2.7 +CONFIG_IGB=y
     2.8  # CONFIG_BNX2 is not set
     2.9  
    2.10  #
     3.1 --- a/arch/x86_64/defconfig	Tue Feb 17 11:25:22 2009 +0000
     3.2 +++ b/arch/x86_64/defconfig	Tue Feb 17 11:25:51 2009 +0000
     3.3 @@ -715,6 +715,7 @@ CONFIG_E1000E=y
     3.4  # CONFIG_VIA_VELOCITY is not set
     3.5  CONFIG_TIGON3=y
     3.6  CONFIG_BNX2=y
     3.7 +CONFIG_IGB=y
     3.8  
     3.9  #
    3.10  # Ethernet (10000 Mbit)
     4.1 --- a/drivers/net/Kconfig	Tue Feb 17 11:25:22 2009 +0000
     4.2 +++ b/drivers/net/Kconfig	Tue Feb 17 11:25:51 2009 +0000
     4.3 @@ -1960,6 +1960,28 @@ config E1000_DISABLE_PACKET_SPLIT
     4.4  
     4.5  	  If in doubt, say N.
     4.6  
     4.7 +config IGB
     4.8 +	tristate "Intel(R) 82575 Gigabit Ethernet support"
     4.9 +	depends on PCI
    4.10 +	---help---
    4.11 +	  This driver supports Intel(R) 82575 gigabit ethernet adapters.
    4.12 +	  For more information on how to identify your adapter, go to the
    4.13 +	  Adapter & Driver ID Guide at:
    4.14 +
    4.15 +	  <http://support.intel.com/support/network/adapter/pro100/21397.htm>
    4.16 +
    4.17 +	  For general information and support, go to the Intel support
    4.18 +	  website at:
    4.19 +
    4.20 +	  <http://support.intel.com>
    4.21 +
    4.22 +	  More specific information on configuring the driver is in
    4.23 +	  <file:Documentation/networking/igb.txt>.
    4.24 +
    4.25 +	  To compile this driver as a module, choose M here and read
    4.26 +	  <file:Documentation/networking/net-modules.txt>.  The module
    4.27 +	  will be called igb.
    4.28 +
    4.29  config E1000E
    4.30  	tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
    4.31  	depends on PCI
     5.1 --- a/drivers/net/Makefile	Tue Feb 17 11:25:22 2009 +0000
     5.2 +++ b/drivers/net/Makefile	Tue Feb 17 11:25:51 2009 +0000
     5.3 @@ -10,6 +10,7 @@ obj-$(CONFIG_E1000) += e1000/
     5.4  obj-$(CONFIG_E1000E) += e1000e/
     5.5  obj-$(CONFIG_IBM_EMAC) += ibm_emac/
     5.6  obj-$(CONFIG_IXGB) += ixgb/
     5.7 +obj-$(CONFIG_IGB) += igb/
     5.8  obj-$(CONFIG_IXGBE) += ixgbe/
     5.9  obj-$(CONFIG_CHELSIO_T1) += chelsio/
    5.10  obj-$(CONFIG_BONDING) += bonding/
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/drivers/net/igb/Makefile	Tue Feb 17 11:25:51 2009 +0000
     6.3 @@ -0,0 +1,37 @@
     6.4 +################################################################################
     6.5 +#
     6.6 +# Intel 82575 PCI-Express Ethernet Linux driver
     6.7 +# Copyright(c) 1999 - 2007 Intel Corporation.
     6.8 +#
     6.9 +# This program is free software; you can redistribute it and/or modify it
    6.10 +# under the terms and conditions of the GNU General Public License,
    6.11 +# version 2, as published by the Free Software Foundation.
    6.12 +#
    6.13 +# This program is distributed in the hope it will be useful, but WITHOUT
    6.14 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    6.15 +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    6.16 +# more details.
    6.17 +#
    6.18 +# You should have received a copy of the GNU General Public License along with
    6.19 +# this program; if not, write to the Free Software Foundation, Inc.,
    6.20 +# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    6.21 +#
    6.22 +# The full GNU General Public License is included in this distribution in
    6.23 +# the file called "COPYING".
    6.24 +#
    6.25 +# Contact Information:
    6.26 +# Linux NICS <linux.nics@intel.com>
    6.27 +# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    6.28 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    6.29 +#
    6.30 +################################################################################
    6.31 +
    6.32 +#
    6.33 +# Makefile for the Intel(R) 82575 PCI-Express ethernet driver
    6.34 +#
    6.35 +
    6.36 +obj-$(CONFIG_IGB) += igb.o
    6.37 +
    6.38 +igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \
    6.39 +	    e1000_mac.o e1000_nvm.o e1000_phy.o
    6.40 +
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/drivers/net/igb/e1000_82575.c	Tue Feb 17 11:25:51 2009 +0000
     7.3 @@ -0,0 +1,1455 @@
     7.4 +/*******************************************************************************
     7.5 +
     7.6 +  Intel(R) Gigabit Ethernet Linux driver
     7.7 +  Copyright(c) 2007 - 2008 Intel Corporation.
     7.8 +
     7.9 +  This program is free software; you can redistribute it and/or modify it
    7.10 +  under the terms and conditions of the GNU General Public License,
    7.11 +  version 2, as published by the Free Software Foundation.
    7.12 +
    7.13 +  This program is distributed in the hope it will be useful, but WITHOUT
    7.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    7.16 +  more details.
    7.17 +
    7.18 +  You should have received a copy of the GNU General Public License along with
    7.19 +  this program; if not, write to the Free Software Foundation, Inc.,
    7.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    7.21 +
    7.22 +  The full GNU General Public License is included in this distribution in
    7.23 +  the file called "COPYING".
    7.24 +
    7.25 +  Contact Information:
    7.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    7.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    7.28 +
    7.29 +*******************************************************************************/
    7.30 +
    7.31 +/* e1000_82575
    7.32 + * e1000_82576
    7.33 + */
    7.34 +
    7.35 +#include <linux/types.h>
    7.36 +#include <linux/slab.h>
    7.37 +#include <linux/if_ether.h>
    7.38 +
    7.39 +#include "e1000_mac.h"
    7.40 +#include "e1000_82575.h"
    7.41 +
    7.42 +static s32  igb_get_invariants_82575(struct e1000_hw *);
    7.43 +static s32  igb_acquire_phy_82575(struct e1000_hw *);
    7.44 +static void igb_release_phy_82575(struct e1000_hw *);
    7.45 +static s32  igb_acquire_nvm_82575(struct e1000_hw *);
    7.46 +static void igb_release_nvm_82575(struct e1000_hw *);
    7.47 +static s32  igb_check_for_link_82575(struct e1000_hw *);
    7.48 +static s32  igb_get_cfg_done_82575(struct e1000_hw *);
    7.49 +static s32  igb_init_hw_82575(struct e1000_hw *);
    7.50 +static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
    7.51 +static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
    7.52 +static s32  igb_reset_hw_82575(struct e1000_hw *);
    7.53 +static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
    7.54 +static s32  igb_setup_copper_link_82575(struct e1000_hw *);
    7.55 +static s32  igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
    7.56 +static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
    7.57 +static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
    7.58 +static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
    7.59 +static s32  igb_configure_pcs_link_82575(struct e1000_hw *);
    7.60 +static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
    7.61 +						 u16 *);
    7.62 +static s32  igb_get_phy_id_82575(struct e1000_hw *);
    7.63 +static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
    7.64 +static bool igb_sgmii_active_82575(struct e1000_hw *);
    7.65 +static s32  igb_reset_init_script_82575(struct e1000_hw *);
    7.66 +static s32  igb_read_mac_addr_82575(struct e1000_hw *);
    7.67 +
    7.68 +
    7.69 +struct e1000_dev_spec_82575 {
    7.70 +	bool sgmii_active;
    7.71 +};
    7.72 +
    7.73 +static s32 igb_get_invariants_82575(struct e1000_hw *hw)
    7.74 +{
    7.75 +	struct e1000_phy_info *phy = &hw->phy;
    7.76 +	struct e1000_nvm_info *nvm = &hw->nvm;
    7.77 +	struct e1000_mac_info *mac = &hw->mac;
    7.78 +	struct e1000_dev_spec_82575 *dev_spec;
    7.79 +	u32 eecd;
    7.80 +	s32 ret_val;
    7.81 +	u16 size;
    7.82 +	u32 ctrl_ext = 0;
    7.83 +
    7.84 +	switch (hw->device_id) {
    7.85 +	case E1000_DEV_ID_82575EB_COPPER:
    7.86 +	case E1000_DEV_ID_82575EB_FIBER_SERDES:
    7.87 +	case E1000_DEV_ID_82575GB_QUAD_COPPER:
    7.88 +		mac->type = e1000_82575;
    7.89 +		break;
    7.90 +	case E1000_DEV_ID_82576:
    7.91 +	case E1000_DEV_ID_82576_FIBER:
    7.92 +	case E1000_DEV_ID_82576_SERDES:
    7.93 +	case E1000_DEV_ID_82576_QUAD_COPPER:
    7.94 +		mac->type = e1000_82576;
    7.95 +		break;
    7.96 +	default:
    7.97 +		return -E1000_ERR_MAC_INIT;
    7.98 +		break;
    7.99 +	}
   7.100 +
   7.101 +	/* MAC initialization */
   7.102 +	hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575);
   7.103 +
   7.104 +	/* Device-specific structure allocation */
   7.105 +	hw->dev_spec = kzalloc(hw->dev_spec_size, GFP_KERNEL);
   7.106 +
   7.107 +	if (!hw->dev_spec)
   7.108 +		return -ENOMEM;
   7.109 +
   7.110 +	dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
   7.111 +
   7.112 +	/* Set media type */
   7.113 +	/*
   7.114 +	 * The 82575 uses bits 22:23 for link mode. The mode can be changed
   7.115 +	 * based on the EEPROM. We cannot rely upon device ID. There
   7.116 +	 * is no distinguishable difference between fiber and internal
   7.117 +	 * SerDes mode on the 82575. There can be an external PHY attached
   7.118 +	 * on the SGMII interface. For this, we'll set sgmii_active to true.
   7.119 +	 */
   7.120 +	phy->media_type = e1000_media_type_copper;
   7.121 +	dev_spec->sgmii_active = false;
   7.122 +
   7.123 +	ctrl_ext = rd32(E1000_CTRL_EXT);
   7.124 +	if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
   7.125 +	    E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
   7.126 +		hw->phy.media_type = e1000_media_type_internal_serdes;
   7.127 +		ctrl_ext |= E1000_CTRL_I2C_ENA;
   7.128 +	} else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
   7.129 +		dev_spec->sgmii_active = true;
   7.130 +		ctrl_ext |= E1000_CTRL_I2C_ENA;
   7.131 +	} else {
   7.132 +		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
   7.133 +	}
   7.134 +	wr32(E1000_CTRL_EXT, ctrl_ext);
   7.135 +
   7.136 +	/* Set mta register count */
   7.137 +	mac->mta_reg_count = 128;
   7.138 +	/* Set rar entry count */
   7.139 +	mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
   7.140 +	if (mac->type == e1000_82576)
   7.141 +		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
   7.142 +	/* Set if part includes ASF firmware */
   7.143 +	mac->asf_firmware_present = true;
   7.144 +	/* Set if manageability features are enabled. */
   7.145 +	mac->arc_subsystem_valid =
   7.146 +		(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
   7.147 +			? true : false;
   7.148 +
   7.149 +	/* physical interface link setup */
   7.150 +	mac->ops.setup_physical_interface =
   7.151 +		(hw->phy.media_type == e1000_media_type_copper)
   7.152 +			? igb_setup_copper_link_82575
   7.153 +			: igb_setup_fiber_serdes_link_82575;
   7.154 +
   7.155 +	/* NVM initialization */
   7.156 +	eecd = rd32(E1000_EECD);
   7.157 +
   7.158 +	nvm->opcode_bits        = 8;
   7.159 +	nvm->delay_usec         = 1;
   7.160 +	switch (nvm->override) {
   7.161 +	case e1000_nvm_override_spi_large:
   7.162 +		nvm->page_size    = 32;
   7.163 +		nvm->address_bits = 16;
   7.164 +		break;
   7.165 +	case e1000_nvm_override_spi_small:
   7.166 +		nvm->page_size    = 8;
   7.167 +		nvm->address_bits = 8;
   7.168 +		break;
   7.169 +	default:
   7.170 +		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
   7.171 +		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
   7.172 +		break;
   7.173 +	}
   7.174 +
   7.175 +	nvm->type = e1000_nvm_eeprom_spi;
   7.176 +
   7.177 +	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
   7.178 +		     E1000_EECD_SIZE_EX_SHIFT);
   7.179 +
   7.180 +	/*
   7.181 +	 * Added to a constant, "size" becomes the left-shift value
   7.182 +	 * for setting word_size.
   7.183 +	 */
   7.184 +	size += NVM_WORD_SIZE_BASE_SHIFT;
   7.185 +
   7.186 +	/* EEPROM access above 16k is unsupported */
   7.187 +	if (size > 14)
   7.188 +		size = 14;
   7.189 +	nvm->word_size = 1 << size;
   7.190 +
   7.191 +	/* setup PHY parameters */
   7.192 +	if (phy->media_type != e1000_media_type_copper) {
   7.193 +		phy->type = e1000_phy_none;
   7.194 +		return 0;
   7.195 +	}
   7.196 +
   7.197 +	phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
   7.198 +	phy->reset_delay_us      = 100;
   7.199 +
   7.200 +	/* PHY function pointers */
   7.201 +	if (igb_sgmii_active_82575(hw)) {
   7.202 +		phy->ops.reset_phy          = igb_phy_hw_reset_sgmii_82575;
   7.203 +		phy->ops.read_phy_reg       = igb_read_phy_reg_sgmii_82575;
   7.204 +		phy->ops.write_phy_reg      = igb_write_phy_reg_sgmii_82575;
   7.205 +	} else {
   7.206 +		phy->ops.reset_phy          = igb_phy_hw_reset;
   7.207 +		phy->ops.read_phy_reg       = igb_read_phy_reg_igp;
   7.208 +		phy->ops.write_phy_reg      = igb_write_phy_reg_igp;
   7.209 +	}
   7.210 +
   7.211 +	/* Set phy->phy_addr and phy->id. */
   7.212 +	ret_val = igb_get_phy_id_82575(hw);
   7.213 +	if (ret_val)
   7.214 +		return ret_val;
   7.215 +
   7.216 +	/* Verify phy id and set remaining function pointers */
   7.217 +	switch (phy->id) {
   7.218 +	case M88E1111_I_PHY_ID:
   7.219 +		phy->type                   = e1000_phy_m88;
   7.220 +		phy->ops.get_phy_info       = igb_get_phy_info_m88;
   7.221 +		phy->ops.get_cable_length   = igb_get_cable_length_m88;
   7.222 +		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
   7.223 +		break;
   7.224 +	case IGP03E1000_E_PHY_ID:
   7.225 +		phy->type                   = e1000_phy_igp_3;
   7.226 +		phy->ops.get_phy_info       = igb_get_phy_info_igp;
   7.227 +		phy->ops.get_cable_length   = igb_get_cable_length_igp_2;
   7.228 +		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
   7.229 +		phy->ops.set_d0_lplu_state  = igb_set_d0_lplu_state_82575;
   7.230 +		phy->ops.set_d3_lplu_state  = igb_set_d3_lplu_state;
   7.231 +		break;
   7.232 +	default:
   7.233 +		return -E1000_ERR_PHY;
   7.234 +	}
   7.235 +
   7.236 +	return 0;
   7.237 +}
   7.238 +
   7.239 +/**
   7.240 + *  igb_acquire_phy_82575 - Acquire rights to access PHY
   7.241 + *  @hw: pointer to the HW structure
   7.242 + *
   7.243 + *  Acquire access rights to the correct PHY.  This is a
   7.244 + *  function pointer entry point called by the api module.
   7.245 + **/
   7.246 +static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
   7.247 +{
   7.248 +	u16 mask;
   7.249 +
   7.250 +	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
   7.251 +
   7.252 +	return igb_acquire_swfw_sync_82575(hw, mask);
   7.253 +}
   7.254 +
   7.255 +/**
   7.256 + *  igb_release_phy_82575 - Release rights to access PHY
   7.257 + *  @hw: pointer to the HW structure
   7.258 + *
   7.259 + *  A wrapper to release access rights to the correct PHY.  This is a
   7.260 + *  function pointer entry point called by the api module.
   7.261 + **/
   7.262 +static void igb_release_phy_82575(struct e1000_hw *hw)
   7.263 +{
   7.264 +	u16 mask;
   7.265 +
   7.266 +	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
   7.267 +	igb_release_swfw_sync_82575(hw, mask);
   7.268 +}
   7.269 +
   7.270 +/**
   7.271 + *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
   7.272 + *  @hw: pointer to the HW structure
   7.273 + *  @offset: register offset to be read
   7.274 + *  @data: pointer to the read data
   7.275 + *
   7.276 + *  Reads the PHY register at offset using the serial gigabit media independent
   7.277 + *  interface and stores the retrieved information in data.
   7.278 + **/
   7.279 +static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
   7.280 +					  u16 *data)
   7.281 +{
   7.282 +	struct e1000_phy_info *phy = &hw->phy;
   7.283 +	u32 i, i2ccmd = 0;
   7.284 +
   7.285 +	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
   7.286 +		hw_dbg("PHY Address %u is out of range\n", offset);
   7.287 +		return -E1000_ERR_PARAM;
   7.288 +	}
   7.289 +
   7.290 +	/*
   7.291 +	 * Set up Op-code, Phy Address, and register address in the I2CCMD
   7.292 +	 * register.  The MAC will take care of interfacing with the
   7.293 +	 * PHY to retrieve the desired data.
   7.294 +	 */
   7.295 +	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
   7.296 +		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
   7.297 +		  (E1000_I2CCMD_OPCODE_READ));
   7.298 +
   7.299 +	wr32(E1000_I2CCMD, i2ccmd);
   7.300 +
   7.301 +	/* Poll the ready bit to see if the I2C read completed */
   7.302 +	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
   7.303 +		udelay(50);
   7.304 +		i2ccmd = rd32(E1000_I2CCMD);
   7.305 +		if (i2ccmd & E1000_I2CCMD_READY)
   7.306 +			break;
   7.307 +	}
   7.308 +	if (!(i2ccmd & E1000_I2CCMD_READY)) {
   7.309 +		hw_dbg("I2CCMD Read did not complete\n");
   7.310 +		return -E1000_ERR_PHY;
   7.311 +	}
   7.312 +	if (i2ccmd & E1000_I2CCMD_ERROR) {
   7.313 +		hw_dbg("I2CCMD Error bit set\n");
   7.314 +		return -E1000_ERR_PHY;
   7.315 +	}
   7.316 +
   7.317 +	/* Need to byte-swap the 16-bit value. */
   7.318 +	*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
   7.319 +
   7.320 +	return 0;
   7.321 +}
   7.322 +
   7.323 +/**
   7.324 + *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
   7.325 + *  @hw: pointer to the HW structure
   7.326 + *  @offset: register offset to write to
   7.327 + *  @data: data to write at register offset
   7.328 + *
   7.329 + *  Writes the data to PHY register at the offset using the serial gigabit
   7.330 + *  media independent interface.
   7.331 + **/
   7.332 +static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
   7.333 +					   u16 data)
   7.334 +{
   7.335 +	struct e1000_phy_info *phy = &hw->phy;
   7.336 +	u32 i, i2ccmd = 0;
   7.337 +	u16 phy_data_swapped;
   7.338 +
   7.339 +	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
   7.340 +		hw_dbg("PHY Address %d is out of range\n", offset);
   7.341 +		return -E1000_ERR_PARAM;
   7.342 +	}
   7.343 +
   7.344 +	/* Swap the data bytes for the I2C interface */
   7.345 +	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
   7.346 +
   7.347 +	/*
   7.348 +	 * Set up Op-code, Phy Address, and register address in the I2CCMD
   7.349 +	 * register.  The MAC will take care of interfacing with the
   7.350 +	 * PHY to retrieve the desired data.
   7.351 +	 */
   7.352 +	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
   7.353 +		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
   7.354 +		  E1000_I2CCMD_OPCODE_WRITE |
   7.355 +		  phy_data_swapped);
   7.356 +
   7.357 +	wr32(E1000_I2CCMD, i2ccmd);
   7.358 +
   7.359 +	/* Poll the ready bit to see if the I2C read completed */
   7.360 +	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
   7.361 +		udelay(50);
   7.362 +		i2ccmd = rd32(E1000_I2CCMD);
   7.363 +		if (i2ccmd & E1000_I2CCMD_READY)
   7.364 +			break;
   7.365 +	}
   7.366 +	if (!(i2ccmd & E1000_I2CCMD_READY)) {
   7.367 +		hw_dbg("I2CCMD Write did not complete\n");
   7.368 +		return -E1000_ERR_PHY;
   7.369 +	}
   7.370 +	if (i2ccmd & E1000_I2CCMD_ERROR) {
   7.371 +		hw_dbg("I2CCMD Error bit set\n");
   7.372 +		return -E1000_ERR_PHY;
   7.373 +	}
   7.374 +
   7.375 +	return 0;
   7.376 +}
   7.377 +
   7.378 +/**
   7.379 + *  igb_get_phy_id_82575 - Retrieve PHY addr and id
   7.380 + *  @hw: pointer to the HW structure
   7.381 + *
   7.382 + *  Retrieves the PHY address and ID for both PHY's which do and do not use
   7.383 + *  sgmi interface.
   7.384 + **/
   7.385 +static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
   7.386 +{
   7.387 +	struct e1000_phy_info *phy = &hw->phy;
   7.388 +	s32  ret_val = 0;
   7.389 +	u16 phy_id;
   7.390 +
   7.391 +	/*
   7.392 +	 * For SGMII PHYs, we try the list of possible addresses until
   7.393 +	 * we find one that works.  For non-SGMII PHYs
   7.394 +	 * (e.g. integrated copper PHYs), an address of 1 should
   7.395 +	 * work.  The result of this function should mean phy->phy_addr
   7.396 +	 * and phy->id are set correctly.
   7.397 +	 */
   7.398 +	if (!(igb_sgmii_active_82575(hw))) {
   7.399 +		phy->addr = 1;
   7.400 +		ret_val = igb_get_phy_id(hw);
   7.401 +		goto out;
   7.402 +	}
   7.403 +
   7.404 +	/*
   7.405 +	 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
   7.406 +	 * Therefore, we need to test 1-7
   7.407 +	 */
   7.408 +	for (phy->addr = 1; phy->addr < 8; phy->addr++) {
   7.409 +		ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
   7.410 +		if (ret_val == 0) {
   7.411 +			hw_dbg("Vendor ID 0x%08X read at address %u\n",
   7.412 +			       phy_id, phy->addr);
   7.413 +			/*
   7.414 +			 * At the time of this writing, The M88 part is
   7.415 +			 * the only supported SGMII PHY product.
   7.416 +			 */
   7.417 +			if (phy_id == M88_VENDOR)
   7.418 +				break;
   7.419 +		} else {
   7.420 +			hw_dbg("PHY address %u was unreadable\n", phy->addr);
   7.421 +		}
   7.422 +	}
   7.423 +
   7.424 +	/* A valid PHY type couldn't be found. */
   7.425 +	if (phy->addr == 8) {
   7.426 +		phy->addr = 0;
   7.427 +		ret_val = -E1000_ERR_PHY;
   7.428 +		goto out;
   7.429 +	}
   7.430 +
   7.431 +	ret_val = igb_get_phy_id(hw);
   7.432 +
   7.433 +out:
   7.434 +	return ret_val;
   7.435 +}
   7.436 +
   7.437 +/**
   7.438 + *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
   7.439 + *  @hw: pointer to the HW structure
   7.440 + *
   7.441 + *  Resets the PHY using the serial gigabit media independent interface.
   7.442 + **/
   7.443 +static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
   7.444 +{
   7.445 +	s32 ret_val;
   7.446 +
   7.447 +	/*
   7.448 +	 * This isn't a true "hard" reset, but is the only reset
   7.449 +	 * available to us at this time.
   7.450 +	*/
   7.451 +
   7.452 +	hw_dbg("Soft resetting SGMII attached PHY...\n");
   7.453 +
   7.454 +	/*
   7.455 +	 * SFP documentation requires the following to configure the SPF module
   7.456 +	 * to work on SGMII.  No further documentation is given.
   7.457 +	 */
   7.458 +	ret_val = hw->phy.ops.write_phy_reg(hw, 0x1B, 0x8084);
   7.459 +	if (ret_val)
   7.460 +		goto out;
   7.461 +
   7.462 +	ret_val = igb_phy_sw_reset(hw);
   7.463 +
   7.464 +out:
   7.465 +	return ret_val;
   7.466 +}
   7.467 +
   7.468 +/**
   7.469 + *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
   7.470 + *  @hw: pointer to the HW structure
   7.471 + *  @active: true to enable LPLU, false to disable
   7.472 + *
   7.473 + *  Sets the LPLU D0 state according to the active flag.  When
   7.474 + *  activating LPLU this function also disables smart speed
   7.475 + *  and vice versa.  LPLU will not be activated unless the
   7.476 + *  device autonegotiation advertisement meets standards of
   7.477 + *  either 10 or 10/100 or 10/100/1000 at all duplexes.
   7.478 + *  This is a function pointer entry point only called by
   7.479 + *  PHY setup routines.
   7.480 + **/
   7.481 +static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
   7.482 +{
   7.483 +	struct e1000_phy_info *phy = &hw->phy;
   7.484 +	s32 ret_val;
   7.485 +	u16 data;
   7.486 +
   7.487 +	ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
   7.488 +	if (ret_val)
   7.489 +		goto out;
   7.490 +
   7.491 +	if (active) {
   7.492 +		data |= IGP02E1000_PM_D0_LPLU;
   7.493 +		ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
   7.494 +						 data);
   7.495 +		if (ret_val)
   7.496 +			goto out;
   7.497 +
   7.498 +		/* When LPLU is enabled, we should disable SmartSpeed */
   7.499 +		ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
   7.500 +						&data);
   7.501 +		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
   7.502 +		ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
   7.503 +						 data);
   7.504 +		if (ret_val)
   7.505 +			goto out;
   7.506 +	} else {
   7.507 +		data &= ~IGP02E1000_PM_D0_LPLU;
   7.508 +		ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
   7.509 +						 data);
   7.510 +		/*
   7.511 +		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
   7.512 +		 * during Dx states where the power conservation is most
   7.513 +		 * important.  During driver activity we should enable
   7.514 +		 * SmartSpeed, so performance is maintained.
   7.515 +		 */
   7.516 +		if (phy->smart_speed == e1000_smart_speed_on) {
   7.517 +			ret_val = phy->ops.read_phy_reg(hw,
   7.518 +					IGP01E1000_PHY_PORT_CONFIG, &data);
   7.519 +			if (ret_val)
   7.520 +				goto out;
   7.521 +
   7.522 +			data |= IGP01E1000_PSCFR_SMART_SPEED;
   7.523 +			ret_val = phy->ops.write_phy_reg(hw,
   7.524 +					IGP01E1000_PHY_PORT_CONFIG, data);
   7.525 +			if (ret_val)
   7.526 +				goto out;
   7.527 +		} else if (phy->smart_speed == e1000_smart_speed_off) {
   7.528 +			ret_val = phy->ops.read_phy_reg(hw,
   7.529 +					IGP01E1000_PHY_PORT_CONFIG, &data);
   7.530 +			if (ret_val)
   7.531 +				goto out;
   7.532 +
   7.533 +			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
   7.534 +			ret_val = phy->ops.write_phy_reg(hw,
   7.535 +					IGP01E1000_PHY_PORT_CONFIG, data);
   7.536 +			if (ret_val)
   7.537 +				goto out;
   7.538 +		}
   7.539 +	}
   7.540 +
   7.541 +out:
   7.542 +	return ret_val;
   7.543 +}
   7.544 +
   7.545 +/**
   7.546 + *  igb_acquire_nvm_82575 - Request for access to EEPROM
   7.547 + *  @hw: pointer to the HW structure
   7.548 + *
   7.549 + *  Acquire the necessary semaphores for exclusive access to the EEPROM.
   7.550 + *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
   7.551 + *  Return successful if access grant bit set, else clear the request for
   7.552 + *  EEPROM access and return -E1000_ERR_NVM (-1).
   7.553 + **/
   7.554 +static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
   7.555 +{
   7.556 +	s32 ret_val;
   7.557 +
   7.558 +	ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
   7.559 +	if (ret_val)
   7.560 +		goto out;
   7.561 +
   7.562 +	ret_val = igb_acquire_nvm(hw);
   7.563 +
   7.564 +	if (ret_val)
   7.565 +		igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
   7.566 +
   7.567 +out:
   7.568 +	return ret_val;
   7.569 +}
   7.570 +
   7.571 +/**
   7.572 + *  igb_release_nvm_82575 - Release exclusive access to EEPROM
   7.573 + *  @hw: pointer to the HW structure
   7.574 + *
   7.575 + *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
   7.576 + *  then release the semaphores acquired.
   7.577 + **/
   7.578 +static void igb_release_nvm_82575(struct e1000_hw *hw)
   7.579 +{
   7.580 +	igb_release_nvm(hw);
   7.581 +	igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
   7.582 +}
   7.583 +
   7.584 +/**
   7.585 + *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
   7.586 + *  @hw: pointer to the HW structure
   7.587 + *  @mask: specifies which semaphore to acquire
   7.588 + *
   7.589 + *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
   7.590 + *  will also specify which port we're acquiring the lock for.
   7.591 + **/
   7.592 +static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
   7.593 +{
   7.594 +	u32 swfw_sync;
   7.595 +	u32 swmask = mask;
   7.596 +	u32 fwmask = mask << 16;
   7.597 +	s32 ret_val = 0;
   7.598 +	s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
   7.599 +
   7.600 +	while (i < timeout) {
   7.601 +		if (igb_get_hw_semaphore(hw)) {
   7.602 +			ret_val = -E1000_ERR_SWFW_SYNC;
   7.603 +			goto out;
   7.604 +		}
   7.605 +
   7.606 +		swfw_sync = rd32(E1000_SW_FW_SYNC);
   7.607 +		if (!(swfw_sync & (fwmask | swmask)))
   7.608 +			break;
   7.609 +
   7.610 +		/*
   7.611 +		 * Firmware currently using resource (fwmask)
   7.612 +		 * or other software thread using resource (swmask)
   7.613 +		 */
   7.614 +		igb_put_hw_semaphore(hw);
   7.615 +		mdelay(5);
   7.616 +		i++;
   7.617 +	}
   7.618 +
   7.619 +	if (i == timeout) {
   7.620 +		hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
   7.621 +		ret_val = -E1000_ERR_SWFW_SYNC;
   7.622 +		goto out;
   7.623 +	}
   7.624 +
   7.625 +	swfw_sync |= swmask;
   7.626 +	wr32(E1000_SW_FW_SYNC, swfw_sync);
   7.627 +
   7.628 +	igb_put_hw_semaphore(hw);
   7.629 +
   7.630 +out:
   7.631 +	return ret_val;
   7.632 +}
   7.633 +
   7.634 +/**
   7.635 + *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
   7.636 + *  @hw: pointer to the HW structure
   7.637 + *  @mask: specifies which semaphore to acquire
   7.638 + *
   7.639 + *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
   7.640 + *  will also specify which port we're releasing the lock for.
   7.641 + **/
   7.642 +static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
   7.643 +{
   7.644 +	u32 swfw_sync;
   7.645 +
   7.646 +	while (igb_get_hw_semaphore(hw) != 0);
   7.647 +	/* Empty */
   7.648 +
   7.649 +	swfw_sync = rd32(E1000_SW_FW_SYNC);
   7.650 +	swfw_sync &= ~mask;
   7.651 +	wr32(E1000_SW_FW_SYNC, swfw_sync);
   7.652 +
   7.653 +	igb_put_hw_semaphore(hw);
   7.654 +}
   7.655 +
   7.656 +/**
   7.657 + *  igb_get_cfg_done_82575 - Read config done bit
   7.658 + *  @hw: pointer to the HW structure
   7.659 + *
   7.660 + *  Read the management control register for the config done bit for
   7.661 + *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
   7.662 + *  to read the config done bit, so an error is *ONLY* logged and returns
   7.663 + *  0.  If we were to return with error, EEPROM-less silicon
   7.664 + *  would not be able to be reset or change link.
   7.665 + **/
   7.666 +static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
   7.667 +{
   7.668 +	s32 timeout = PHY_CFG_TIMEOUT;
   7.669 +	s32 ret_val = 0;
   7.670 +	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
   7.671 +
   7.672 +	if (hw->bus.func == 1)
   7.673 +		mask = E1000_NVM_CFG_DONE_PORT_1;
   7.674 +
   7.675 +	while (timeout) {
   7.676 +		if (rd32(E1000_EEMNGCTL) & mask)
   7.677 +			break;
   7.678 +		msleep(1);
   7.679 +		timeout--;
   7.680 +	}
   7.681 +	if (!timeout)
   7.682 +		hw_dbg("MNG configuration cycle has not completed.\n");
   7.683 +
   7.684 +	/* If EEPROM is not marked present, init the PHY manually */
   7.685 +	if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
   7.686 +	    (hw->phy.type == e1000_phy_igp_3))
   7.687 +		igb_phy_init_script_igp3(hw);
   7.688 +
   7.689 +	return ret_val;
   7.690 +}
   7.691 +
   7.692 +/**
   7.693 + *  igb_check_for_link_82575 - Check for link
   7.694 + *  @hw: pointer to the HW structure
   7.695 + *
   7.696 + *  If sgmii is enabled, then use the pcs register to determine link, otherwise
   7.697 + *  use the generic interface for determining link.
   7.698 + **/
   7.699 +static s32 igb_check_for_link_82575(struct e1000_hw *hw)
   7.700 +{
   7.701 +	s32 ret_val;
   7.702 +	u16 speed, duplex;
   7.703 +
   7.704 +	/* SGMII link check is done through the PCS register. */
   7.705 +	if ((hw->phy.media_type != e1000_media_type_copper) ||
   7.706 +	    (igb_sgmii_active_82575(hw)))
   7.707 +		ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
   7.708 +		                                             &duplex);
   7.709 +	else
   7.710 +		ret_val = igb_check_for_copper_link(hw);
   7.711 +
   7.712 +	return ret_val;
   7.713 +}
   7.714 +/**
   7.715 + *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
   7.716 + *  @hw: pointer to the HW structure
   7.717 + *  @speed: stores the current speed
   7.718 + *  @duplex: stores the current duplex
   7.719 + *
   7.720 + *  Using the physical coding sub-layer (PCS), retrieve the current speed and
   7.721 + *  duplex, then store the values in the pointers provided.
   7.722 + **/
   7.723 +static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
   7.724 +						u16 *duplex)
   7.725 +{
   7.726 +	struct e1000_mac_info *mac = &hw->mac;
   7.727 +	u32 pcs;
   7.728 +
   7.729 +	/* Set up defaults for the return values of this function */
   7.730 +	mac->serdes_has_link = false;
   7.731 +	*speed = 0;
   7.732 +	*duplex = 0;
   7.733 +
   7.734 +	/*
   7.735 +	 * Read the PCS Status register for link state. For non-copper mode,
   7.736 +	 * the status register is not accurate. The PCS status register is
   7.737 +	 * used instead.
   7.738 +	 */
   7.739 +	pcs = rd32(E1000_PCS_LSTAT);
   7.740 +
   7.741 +	/*
   7.742 +	 * The link up bit determines when link is up on autoneg. The sync ok
   7.743 +	 * gets set once both sides sync up and agree upon link. Stable link
   7.744 +	 * can be determined by checking for both link up and link sync ok
   7.745 +	 */
   7.746 +	if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
   7.747 +		mac->serdes_has_link = true;
   7.748 +
   7.749 +		/* Detect and store PCS speed */
   7.750 +		if (pcs & E1000_PCS_LSTS_SPEED_1000) {
   7.751 +			*speed = SPEED_1000;
   7.752 +		} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
   7.753 +			*speed = SPEED_100;
   7.754 +		} else {
   7.755 +			*speed = SPEED_10;
   7.756 +		}
   7.757 +
   7.758 +		/* Detect and store PCS duplex */
   7.759 +		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
   7.760 +			*duplex = FULL_DUPLEX;
   7.761 +		} else {
   7.762 +			*duplex = HALF_DUPLEX;
   7.763 +		}
   7.764 +	}
   7.765 +
   7.766 +	return 0;
   7.767 +}
   7.768 +
   7.769 +/**
   7.770 + *  igb_init_rx_addrs_82575 - Initialize receive address's
   7.771 + *  @hw: pointer to the HW structure
   7.772 + *  @rar_count: receive address registers
   7.773 + *
   7.774 + *  Setups the receive address registers by setting the base receive address
   7.775 + *  register to the devices MAC address and clearing all the other receive
   7.776 + *  address registers to 0.
   7.777 + **/
   7.778 +static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
   7.779 +{
   7.780 +	u32 i;
   7.781 +	u8 addr[6] = {0,0,0,0,0,0};
   7.782 +	/*
   7.783 +	 * This function is essentially the same as that of
   7.784 +	 * e1000_init_rx_addrs_generic. However it also takes care
   7.785 +	 * of the special case where the register offset of the
   7.786 +	 * second set of RARs begins elsewhere. This is implicitly taken care by
   7.787 +	 * function e1000_rar_set_generic.
   7.788 +	 */
   7.789 +
   7.790 +	hw_dbg("e1000_init_rx_addrs_82575");
   7.791 +
   7.792 +	/* Setup the receive address */
   7.793 +	hw_dbg("Programming MAC Address into RAR[0]\n");
   7.794 +	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
   7.795 +
   7.796 +	/* Zero out the other (rar_entry_count - 1) receive addresses */
   7.797 +	hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
   7.798 +	for (i = 1; i < rar_count; i++)
   7.799 +	    hw->mac.ops.rar_set(hw, addr, i);
   7.800 +}
   7.801 +
   7.802 +/**
   7.803 + *  igb_update_mc_addr_list_82575 - Update Multicast addresses
   7.804 + *  @hw: pointer to the HW structure
   7.805 + *  @mc_addr_list: array of multicast addresses to program
   7.806 + *  @mc_addr_count: number of multicast addresses to program
   7.807 + *  @rar_used_count: the first RAR register free to program
   7.808 + *  @rar_count: total number of supported Receive Address Registers
   7.809 + *
   7.810 + *  Updates the Receive Address Registers and Multicast Table Array.
   7.811 + *  The caller must have a packed mc_addr_list of multicast addresses.
   7.812 + *  The parameter rar_count will usually be hw->mac.rar_entry_count
   7.813 + *  unless there are workarounds that change this.
   7.814 + **/
   7.815 +void igb_update_mc_addr_list_82575(struct e1000_hw *hw,
   7.816 +                                   u8 *mc_addr_list, u32 mc_addr_count,
   7.817 +                                   u32 rar_used_count, u32 rar_count)
   7.818 +{
   7.819 +	u32 hash_value;
   7.820 +	u32 i;
   7.821 +	u8 addr[6] = {0,0,0,0,0,0};
   7.822 +	/*
   7.823 +	 * This function is essentially the same as that of 
   7.824 +	 * igb_update_mc_addr_list_generic. However it also takes care 
   7.825 +	 * of the special case where the register offset of the 
   7.826 +	 * second set of RARs begins elsewhere. This is implicitly taken care by 
   7.827 +	 * function e1000_rar_set_generic.
   7.828 +	 */
   7.829 +
   7.830 +	/*
   7.831 +	 * Load the first set of multicast addresses into the exact
   7.832 +	 * filters (RAR).  If there are not enough to fill the RAR
   7.833 +	 * array, clear the filters.
   7.834 +	 */
   7.835 +	for (i = rar_used_count; i < rar_count; i++) {
   7.836 +		if (mc_addr_count) {
   7.837 +			igb_rar_set(hw, mc_addr_list, i);
   7.838 +			mc_addr_count--;
   7.839 +			mc_addr_list += ETH_ALEN;
   7.840 +		} else {
   7.841 +			igb_rar_set(hw, addr, i);
   7.842 +		}
   7.843 +	}
   7.844 +
   7.845 +	/* Clear the old settings from the MTA */
   7.846 +	hw_dbg("Clearing MTA\n");
   7.847 +	for (i = 0; i < hw->mac.mta_reg_count; i++) {
   7.848 +		array_wr32(E1000_MTA, i, 0);
   7.849 +		wrfl();
   7.850 +	}
   7.851 +
   7.852 +	/* Load any remaining multicast addresses into the hash table. */
   7.853 +	for (; mc_addr_count > 0; mc_addr_count--) {
   7.854 +		hash_value = igb_hash_mc_addr(hw, mc_addr_list);
   7.855 +		hw_dbg("Hash value = 0x%03X\n", hash_value);
   7.856 +		igb_mta_set(hw, hash_value);
   7.857 +		mc_addr_list += ETH_ALEN;
   7.858 +	}
   7.859 +}
   7.860 +
   7.861 +/**
   7.862 + *  igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
   7.863 + *  @hw: pointer to the HW structure
   7.864 + *
   7.865 + *  In the case of fiber serdes, shut down optics and PCS on driver unload
   7.866 + *  when management pass thru is not enabled.
   7.867 + **/
   7.868 +void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
   7.869 +{
   7.870 +	u32 reg;
   7.871 +
   7.872 +	if (hw->mac.type != e1000_82576 ||
   7.873 +	    (hw->phy.media_type != e1000_media_type_fiber &&
   7.874 +	     hw->phy.media_type != e1000_media_type_internal_serdes))
   7.875 +		return;
   7.876 +
   7.877 +	/* if the management interface is not enabled, then power down */
   7.878 +	if (!igb_enable_mng_pass_thru(hw)) {
   7.879 +		/* Disable PCS to turn off link */
   7.880 +		reg = rd32(E1000_PCS_CFG0);
   7.881 +		reg &= ~E1000_PCS_CFG_PCS_EN;
   7.882 +		wr32(E1000_PCS_CFG0, reg);
   7.883 +
   7.884 +		/* shutdown the laser */
   7.885 +		reg = rd32(E1000_CTRL_EXT);
   7.886 +		reg |= E1000_CTRL_EXT_SDP7_DATA;
   7.887 +		wr32(E1000_CTRL_EXT, reg);
   7.888 +
   7.889 +		/* flush the write to verify completion */
   7.890 +		wrfl();
   7.891 +		msleep(1);
   7.892 +	}
   7.893 +
   7.894 +	return;
   7.895 +}
   7.896 +
   7.897 +/**
   7.898 + *  igb_reset_hw_82575 - Reset hardware
   7.899 + *  @hw: pointer to the HW structure
   7.900 + *
   7.901 + *  This resets the hardware into a known state.  This is a
   7.902 + *  function pointer entry point called by the api module.
   7.903 + **/
   7.904 +static s32 igb_reset_hw_82575(struct e1000_hw *hw)
   7.905 +{
   7.906 +	u32 ctrl, icr;
   7.907 +	s32 ret_val;
   7.908 +
   7.909 +	/*
   7.910 +	 * Prevent the PCI-E bus from sticking if there is no TLP connection
   7.911 +	 * on the last TLP read/write transaction when MAC is reset.
   7.912 +	 */
   7.913 +	ret_val = igb_disable_pcie_master(hw);
   7.914 +	if (ret_val)
   7.915 +		hw_dbg("PCI-E Master disable polling has failed.\n");
   7.916 +
   7.917 +	hw_dbg("Masking off all interrupts\n");
   7.918 +	wr32(E1000_IMC, 0xffffffff);
   7.919 +
   7.920 +	wr32(E1000_RCTL, 0);
   7.921 +	wr32(E1000_TCTL, E1000_TCTL_PSP);
   7.922 +	wrfl();
   7.923 +
   7.924 +	msleep(10);
   7.925 +
   7.926 +	ctrl = rd32(E1000_CTRL);
   7.927 +
   7.928 +	hw_dbg("Issuing a global reset to MAC\n");
   7.929 +	wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
   7.930 +
   7.931 +	ret_val = igb_get_auto_rd_done(hw);
   7.932 +	if (ret_val) {
   7.933 +		/*
   7.934 +		 * When auto config read does not complete, do not
   7.935 +		 * return with an error. This can happen in situations
   7.936 +		 * where there is no eeprom and prevents getting link.
   7.937 +		 */
   7.938 +		hw_dbg("Auto Read Done did not complete\n");
   7.939 +	}
   7.940 +
   7.941 +	/* If EEPROM is not present, run manual init scripts */
   7.942 +	if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
   7.943 +		igb_reset_init_script_82575(hw);
   7.944 +
   7.945 +	/* Clear any pending interrupt events. */
   7.946 +	wr32(E1000_IMC, 0xffffffff);
   7.947 +	icr = rd32(E1000_ICR);
   7.948 +
   7.949 +	igb_check_alt_mac_addr(hw);
   7.950 +
   7.951 +	return ret_val;
   7.952 +}
   7.953 +
   7.954 +/**
   7.955 + *  igb_init_hw_82575 - Initialize hardware
   7.956 + *  @hw: pointer to the HW structure
   7.957 + *
   7.958 + *  This inits the hardware readying it for operation.
   7.959 + **/
   7.960 +static s32 igb_init_hw_82575(struct e1000_hw *hw)
   7.961 +{
   7.962 +	struct e1000_mac_info *mac = &hw->mac;
   7.963 +	s32 ret_val;
   7.964 +	u16 i, rar_count = mac->rar_entry_count;
   7.965 +
   7.966 +	/* Initialize identification LED */
   7.967 +	ret_val = igb_id_led_init(hw);
   7.968 +	if (ret_val) {
   7.969 +		hw_dbg("Error initializing identification LED\n");
   7.970 +		/* This is not fatal and we should not stop init due to this */
   7.971 +	}
   7.972 +
   7.973 +	/* Disabling VLAN filtering */
   7.974 +	hw_dbg("Initializing the IEEE VLAN\n");
   7.975 +	igb_clear_vfta(hw);
   7.976 +
   7.977 +	/* Setup the receive address */
   7.978 +	igb_init_rx_addrs_82575(hw, rar_count);
   7.979 +	/* Zero out the Multicast HASH table */
   7.980 +	hw_dbg("Zeroing the MTA\n");
   7.981 +	for (i = 0; i < mac->mta_reg_count; i++)
   7.982 +		array_wr32(E1000_MTA, i, 0);
   7.983 +
   7.984 +	/* Setup link and flow control */
   7.985 +	ret_val = igb_setup_link(hw);
   7.986 +
   7.987 +	/*
   7.988 +	 * Clear all of the statistics registers (clear on read).  It is
   7.989 +	 * important that we do this after we have tried to establish link
   7.990 +	 * because the symbol error count will increment wildly if there
   7.991 +	 * is no link.
   7.992 +	 */
   7.993 +	igb_clear_hw_cntrs_82575(hw);
   7.994 +
   7.995 +	return ret_val;
   7.996 +}
   7.997 +
   7.998 +/**
   7.999 + *  igb_setup_copper_link_82575 - Configure copper link settings
  7.1000 + *  @hw: pointer to the HW structure
  7.1001 + *
  7.1002 + *  Configures the link for auto-neg or forced speed and duplex.  Then we check
  7.1003 + *  for link, once link is established calls to configure collision distance
  7.1004 + *  and flow control are called.
  7.1005 + **/
  7.1006 +static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
  7.1007 +{
  7.1008 +	u32 ctrl, led_ctrl;
  7.1009 +	s32  ret_val;
  7.1010 +	bool link;
  7.1011 +
  7.1012 +	ctrl = rd32(E1000_CTRL);
  7.1013 +	ctrl |= E1000_CTRL_SLU;
  7.1014 +	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  7.1015 +	wr32(E1000_CTRL, ctrl);
  7.1016 +
  7.1017 +	switch (hw->phy.type) {
  7.1018 +	case e1000_phy_m88:
  7.1019 +		ret_val = igb_copper_link_setup_m88(hw);
  7.1020 +		break;
  7.1021 +	case e1000_phy_igp_3:
  7.1022 +		ret_val = igb_copper_link_setup_igp(hw);
  7.1023 +		/* Setup activity LED */
  7.1024 +		led_ctrl = rd32(E1000_LEDCTL);
  7.1025 +		led_ctrl &= IGP_ACTIVITY_LED_MASK;
  7.1026 +		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  7.1027 +		wr32(E1000_LEDCTL, led_ctrl);
  7.1028 +		break;
  7.1029 +	default:
  7.1030 +		ret_val = -E1000_ERR_PHY;
  7.1031 +		break;
  7.1032 +	}
  7.1033 +
  7.1034 +	if (ret_val)
  7.1035 +		goto out;
  7.1036 +
  7.1037 +	if (hw->mac.autoneg) {
  7.1038 +		/*
  7.1039 +		 * Setup autoneg and flow control advertisement
  7.1040 +		 * and perform autonegotiation.
  7.1041 +		 */
  7.1042 +		ret_val = igb_copper_link_autoneg(hw);
  7.1043 +		if (ret_val)
  7.1044 +			goto out;
  7.1045 +	} else {
  7.1046 +		/*
  7.1047 +		 * PHY will be set to 10H, 10F, 100H or 100F
  7.1048 +		 * depending on user settings.
  7.1049 +		 */
  7.1050 +		hw_dbg("Forcing Speed and Duplex\n");
  7.1051 +		ret_val = igb_phy_force_speed_duplex(hw);
  7.1052 +		if (ret_val) {
  7.1053 +			hw_dbg("Error Forcing Speed and Duplex\n");
  7.1054 +			goto out;
  7.1055 +		}
  7.1056 +	}
  7.1057 +
  7.1058 +	ret_val = igb_configure_pcs_link_82575(hw);
  7.1059 +	if (ret_val)
  7.1060 +		goto out;
  7.1061 +
  7.1062 +	/*
  7.1063 +	 * Check link status. Wait up to 100 microseconds for link to become
  7.1064 +	 * valid.
  7.1065 +	 */
  7.1066 +	ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
  7.1067 +	if (ret_val)
  7.1068 +		goto out;
  7.1069 +
  7.1070 +	if (link) {
  7.1071 +		hw_dbg("Valid link established!!!\n");
  7.1072 +		/* Config the MAC and PHY after link is up */
  7.1073 +		igb_config_collision_dist(hw);
  7.1074 +		ret_val = igb_config_fc_after_link_up(hw);
  7.1075 +	} else {
  7.1076 +		hw_dbg("Unable to establish link!!!\n");
  7.1077 +	}
  7.1078 +
  7.1079 +out:
  7.1080 +	return ret_val;
  7.1081 +}
  7.1082 +
  7.1083 +/**
  7.1084 + *  igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
  7.1085 + *  @hw: pointer to the HW structure
  7.1086 + *
  7.1087 + *  Configures speed and duplex for fiber and serdes links.
  7.1088 + **/
  7.1089 +static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
  7.1090 +{
  7.1091 +	u32 reg;
  7.1092 +
  7.1093 +	/*
  7.1094 +	 * On the 82575, SerDes loopback mode persists until it is
  7.1095 +	 * explicitly turned off or a power cycle is performed.  A read to
  7.1096 +	 * the register does not indicate its status.  Therefore, we ensure
  7.1097 +	 * loopback mode is disabled during initialization.
  7.1098 +	 */
  7.1099 +	wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
  7.1100 +
  7.1101 +	/* Force link up, set 1gb, set both sw defined pins */
  7.1102 +	reg = rd32(E1000_CTRL);
  7.1103 +	reg |= E1000_CTRL_SLU |
  7.1104 +	       E1000_CTRL_SPD_1000 |
  7.1105 +	       E1000_CTRL_FRCSPD |
  7.1106 +	       E1000_CTRL_SWDPIN0 |
  7.1107 +	       E1000_CTRL_SWDPIN1;
  7.1108 +	wr32(E1000_CTRL, reg);
  7.1109 +
  7.1110 +	/* Set switch control to serdes energy detect */
  7.1111 +	reg = rd32(E1000_CONNSW);
  7.1112 +	reg |= E1000_CONNSW_ENRGSRC;
  7.1113 +	wr32(E1000_CONNSW, reg);
  7.1114 +
  7.1115 +	/*
  7.1116 +	 * New SerDes mode allows for forcing speed or autonegotiating speed
  7.1117 +	 * at 1gb. Autoneg should be default set by most drivers. This is the
  7.1118 +	 * mode that will be compatible with older link partners and switches.
  7.1119 +	 * However, both are supported by the hardware and some drivers/tools.
  7.1120 +	 */
  7.1121 +	reg = rd32(E1000_PCS_LCTL);
  7.1122 +
  7.1123 +	reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
  7.1124 +		E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
  7.1125 +
  7.1126 +	if (hw->mac.autoneg) {
  7.1127 +		/* Set PCS register for autoneg */
  7.1128 +		reg |= E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
  7.1129 +		       E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
  7.1130 +		       E1000_PCS_LCTL_AN_ENABLE |     /* Enable Autoneg */
  7.1131 +		       E1000_PCS_LCTL_AN_RESTART;     /* Restart autoneg */
  7.1132 +		hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
  7.1133 +	} else {
  7.1134 +		/* Set PCS register for forced speed */
  7.1135 +		reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
  7.1136 +		       E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
  7.1137 +		       E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
  7.1138 +		       E1000_PCS_LCTL_FSD |           /* Force Speed */
  7.1139 +		       E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
  7.1140 +		hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
  7.1141 +	}
  7.1142 +
  7.1143 +	if (hw->mac.type == e1000_82576) {
  7.1144 +		reg |= E1000_PCS_LCTL_FORCE_FCTRL;
  7.1145 +		igb_force_mac_fc(hw);
  7.1146 +	}
  7.1147 +
  7.1148 +	wr32(E1000_PCS_LCTL, reg);
  7.1149 +
  7.1150 +	return 0;
  7.1151 +}
  7.1152 +
  7.1153 +/**
  7.1154 + *  igb_configure_pcs_link_82575 - Configure PCS link
  7.1155 + *  @hw: pointer to the HW structure
  7.1156 + *
  7.1157 + *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
  7.1158 + *  only used on copper connections where the serialized gigabit media
  7.1159 + *  independent interface (sgmii) is being used.  Configures the link
  7.1160 + *  for auto-negotiation or forces speed/duplex.
  7.1161 + **/
  7.1162 +static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
  7.1163 +{
  7.1164 +	struct e1000_mac_info *mac = &hw->mac;
  7.1165 +	u32 reg = 0;
  7.1166 +
  7.1167 +	if (hw->phy.media_type != e1000_media_type_copper ||
  7.1168 +	    !(igb_sgmii_active_82575(hw)))
  7.1169 +		goto out;
  7.1170 +
  7.1171 +	/* For SGMII, we need to issue a PCS autoneg restart */
  7.1172 +	reg = rd32(E1000_PCS_LCTL);
  7.1173 +
  7.1174 +	/* AN time out should be disabled for SGMII mode */
  7.1175 +	reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
  7.1176 +
  7.1177 +	if (mac->autoneg) {
  7.1178 +		/* Make sure forced speed and force link are not set */
  7.1179 +		reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
  7.1180 +
  7.1181 +		/*
  7.1182 +		 * The PHY should be setup prior to calling this function.
  7.1183 +		 * All we need to do is restart autoneg and enable autoneg.
  7.1184 +		 */
  7.1185 +		reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
  7.1186 +	} else {
  7.1187 +		/* Set PCS register for forced speed */
  7.1188 +
  7.1189 +		/* Turn off bits for full duplex, speed, and autoneg */
  7.1190 +		reg &= ~(E1000_PCS_LCTL_FSV_1000 |
  7.1191 +			 E1000_PCS_LCTL_FSV_100 |
  7.1192 +			 E1000_PCS_LCTL_FDV_FULL |
  7.1193 +			 E1000_PCS_LCTL_AN_ENABLE);
  7.1194 +
  7.1195 +		/* Check for duplex first */
  7.1196 +		if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
  7.1197 +			reg |= E1000_PCS_LCTL_FDV_FULL;
  7.1198 +
  7.1199 +		/* Now set speed */
  7.1200 +		if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
  7.1201 +			reg |= E1000_PCS_LCTL_FSV_100;
  7.1202 +
  7.1203 +		/* Force speed and force link */
  7.1204 +		reg |= E1000_PCS_LCTL_FSD |
  7.1205 +		       E1000_PCS_LCTL_FORCE_LINK |
  7.1206 +		       E1000_PCS_LCTL_FLV_LINK_UP;
  7.1207 +
  7.1208 +		hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
  7.1209 +		       reg);
  7.1210 +	}
  7.1211 +	wr32(E1000_PCS_LCTL, reg);
  7.1212 +
  7.1213 +out:
  7.1214 +	return 0;
  7.1215 +}
  7.1216 +
  7.1217 +/**
  7.1218 + *  igb_sgmii_active_82575 - Return sgmii state
  7.1219 + *  @hw: pointer to the HW structure
  7.1220 + *
  7.1221 + *  82575 silicon has a serialized gigabit media independent interface (sgmii)
  7.1222 + *  which can be enabled for use in the embedded applications.  Simply
  7.1223 + *  return the current state of the sgmii interface.
  7.1224 + **/
  7.1225 +static bool igb_sgmii_active_82575(struct e1000_hw *hw)
  7.1226 +{
  7.1227 +	struct e1000_dev_spec_82575 *dev_spec;
  7.1228 +	bool ret_val;
  7.1229 +
  7.1230 +	if (hw->mac.type != e1000_82575) {
  7.1231 +		ret_val = false;
  7.1232 +		goto out;
  7.1233 +	}
  7.1234 +
  7.1235 +	dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
  7.1236 +
  7.1237 +	ret_val = dev_spec->sgmii_active;
  7.1238 +
  7.1239 +out:
  7.1240 +	return ret_val;
  7.1241 +}
  7.1242 +
  7.1243 +/**
  7.1244 + *  igb_reset_init_script_82575 - Inits HW defaults after reset
  7.1245 + *  @hw: pointer to the HW structure
  7.1246 + *
  7.1247 + *  Inits recommended HW defaults after a reset when there is no EEPROM
  7.1248 + *  detected. This is only for the 82575.
  7.1249 + **/
  7.1250 +static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
  7.1251 +{
  7.1252 +	if (hw->mac.type == e1000_82575) {
  7.1253 +		hw_dbg("Running reset init script for 82575\n");
  7.1254 +		/* SerDes configuration via SERDESCTRL */
  7.1255 +		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
  7.1256 +		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
  7.1257 +		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
  7.1258 +		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
  7.1259 +
  7.1260 +		/* CCM configuration via CCMCTL register */
  7.1261 +		igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
  7.1262 +		igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
  7.1263 +
  7.1264 +		/* PCIe lanes configuration */
  7.1265 +		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
  7.1266 +		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
  7.1267 +		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
  7.1268 +		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
  7.1269 +
  7.1270 +		/* PCIe PLL Configuration */
  7.1271 +		igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
  7.1272 +		igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
  7.1273 +		igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
  7.1274 +	}
  7.1275 +
  7.1276 +	return 0;
  7.1277 +}
  7.1278 +
  7.1279 +/**
  7.1280 + *  igb_read_mac_addr_82575 - Read device MAC address
  7.1281 + *  @hw: pointer to the HW structure
  7.1282 + **/
  7.1283 +static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
  7.1284 +{
  7.1285 +	s32 ret_val = 0;
  7.1286 +
  7.1287 +	if (igb_check_alt_mac_addr(hw))
  7.1288 +		ret_val = igb_read_mac_addr(hw);
  7.1289 +
  7.1290 +	return ret_val;
  7.1291 +}
  7.1292 +
  7.1293 +/**
  7.1294 + *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
  7.1295 + *  @hw: pointer to the HW structure
  7.1296 + *
  7.1297 + *  Clears the hardware counters by reading the counter registers.
  7.1298 + **/
  7.1299 +static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
  7.1300 +{
  7.1301 +	u32 temp;
  7.1302 +
  7.1303 +	igb_clear_hw_cntrs_base(hw);
  7.1304 +
  7.1305 +	temp = rd32(E1000_PRC64);
  7.1306 +	temp = rd32(E1000_PRC127);
  7.1307 +	temp = rd32(E1000_PRC255);
  7.1308 +	temp = rd32(E1000_PRC511);
  7.1309 +	temp = rd32(E1000_PRC1023);
  7.1310 +	temp = rd32(E1000_PRC1522);
  7.1311 +	temp = rd32(E1000_PTC64);
  7.1312 +	temp = rd32(E1000_PTC127);
  7.1313 +	temp = rd32(E1000_PTC255);
  7.1314 +	temp = rd32(E1000_PTC511);
  7.1315 +	temp = rd32(E1000_PTC1023);
  7.1316 +	temp = rd32(E1000_PTC1522);
  7.1317 +
  7.1318 +	temp = rd32(E1000_ALGNERRC);
  7.1319 +	temp = rd32(E1000_RXERRC);
  7.1320 +	temp = rd32(E1000_TNCRS);
  7.1321 +	temp = rd32(E1000_CEXTERR);
  7.1322 +	temp = rd32(E1000_TSCTC);
  7.1323 +	temp = rd32(E1000_TSCTFC);
  7.1324 +
  7.1325 +	temp = rd32(E1000_MGTPRC);
  7.1326 +	temp = rd32(E1000_MGTPDC);
  7.1327 +	temp = rd32(E1000_MGTPTC);
  7.1328 +
  7.1329 +	temp = rd32(E1000_IAC);
  7.1330 +	temp = rd32(E1000_ICRXOC);
  7.1331 +
  7.1332 +	temp = rd32(E1000_ICRXPTC);
  7.1333 +	temp = rd32(E1000_ICRXATC);
  7.1334 +	temp = rd32(E1000_ICTXPTC);
  7.1335 +	temp = rd32(E1000_ICTXATC);
  7.1336 +	temp = rd32(E1000_ICTXQEC);
  7.1337 +	temp = rd32(E1000_ICTXQMTC);
  7.1338 +	temp = rd32(E1000_ICRXDMTC);
  7.1339 +
  7.1340 +	temp = rd32(E1000_CBTMPC);
  7.1341 +	temp = rd32(E1000_HTDPMC);
  7.1342 +	temp = rd32(E1000_CBRMPC);
  7.1343 +	temp = rd32(E1000_RPTHC);
  7.1344 +	temp = rd32(E1000_HGPTC);
  7.1345 +	temp = rd32(E1000_HTCBDPC);
  7.1346 +	temp = rd32(E1000_HGORCL);
  7.1347 +	temp = rd32(E1000_HGORCH);
  7.1348 +	temp = rd32(E1000_HGOTCL);
  7.1349 +	temp = rd32(E1000_HGOTCH);
  7.1350 +	temp = rd32(E1000_LENERRS);
  7.1351 +
  7.1352 +	/* This register should not be read in copper configurations */
  7.1353 +	if (hw->phy.media_type == e1000_media_type_internal_serdes)
  7.1354 +		temp = rd32(E1000_SCVPC);
  7.1355 +}
  7.1356 +
  7.1357 +/**
  7.1358 + *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
  7.1359 + *  @hw: pointer to the HW structure
  7.1360 + *
  7.1361 + *  After rx enable if managability is enabled then there is likely some
  7.1362 + *  bad data at the start of the fifo and possibly in the DMA fifo.  This
  7.1363 + *  function clears the fifos and flushes any packets that came in as rx was
  7.1364 + *  being enabled.
  7.1365 + **/
  7.1366 +void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
  7.1367 +{
  7.1368 +	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
  7.1369 +	int i, ms_wait;
  7.1370 +
  7.1371 +	if (hw->mac.type != e1000_82575 ||
  7.1372 +	    !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
  7.1373 +		return;
  7.1374 +
  7.1375 +	/* Disable all RX queues */
  7.1376 +	for (i = 0; i < 4; i++) {
  7.1377 +		rxdctl[i] = rd32(E1000_RXDCTL(i));
  7.1378 +		wr32(E1000_RXDCTL(i),
  7.1379 +		     rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
  7.1380 +	}
  7.1381 +	/* Poll all queues to verify they have shut down */
  7.1382 +	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
  7.1383 +		msleep(1);
  7.1384 +		rx_enabled = 0;
  7.1385 +		for (i = 0; i < 4; i++)
  7.1386 +			rx_enabled |= rd32(E1000_RXDCTL(i));
  7.1387 +		if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
  7.1388 +			break;
  7.1389 +	}
  7.1390 +
  7.1391 +	if (ms_wait == 10)
  7.1392 +		hw_dbg("Queue disable timed out after 10ms\n");
  7.1393 +
  7.1394 +	/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
  7.1395 +	 * incoming packets are rejected.  Set enable and wait 2ms so that
  7.1396 +	 * any packet that was coming in as RCTL.EN was set is flushed
  7.1397 +	 */
  7.1398 +	rfctl = rd32(E1000_RFCTL);
  7.1399 +	wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
  7.1400 +
  7.1401 +	rlpml = rd32(E1000_RLPML);
  7.1402 +	wr32(E1000_RLPML, 0);
  7.1403 +
  7.1404 +	rctl = rd32(E1000_RCTL);
  7.1405 +	temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
  7.1406 +	temp_rctl |= E1000_RCTL_LPE;
  7.1407 +
  7.1408 +	wr32(E1000_RCTL, temp_rctl);
  7.1409 +	wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
  7.1410 +	wrfl();
  7.1411 +	msleep(2);
  7.1412 +
  7.1413 +	/* Enable RX queues that were previously enabled and restore our
  7.1414 +	 * previous state
  7.1415 +	 */
  7.1416 +	for (i = 0; i < 4; i++)
  7.1417 +		wr32(E1000_RXDCTL(i), rxdctl[i]);
  7.1418 +	wr32(E1000_RCTL, rctl);
  7.1419 +	wrfl();
  7.1420 +
  7.1421 +	wr32(E1000_RLPML, rlpml);
  7.1422 +	wr32(E1000_RFCTL, rfctl);
  7.1423 +
  7.1424 +	/* Flush receive errors generated by workaround */
  7.1425 +	rd32(E1000_ROC);
  7.1426 +	rd32(E1000_RNBC);
  7.1427 +	rd32(E1000_MPC);
  7.1428 +}
  7.1429 +
  7.1430 +static struct e1000_mac_operations e1000_mac_ops_82575 = {
  7.1431 +	.reset_hw             = igb_reset_hw_82575,
  7.1432 +	.init_hw              = igb_init_hw_82575,
  7.1433 +	.check_for_link       = igb_check_for_link_82575,
  7.1434 +	.rar_set              = igb_rar_set,
  7.1435 +	.read_mac_addr        = igb_read_mac_addr_82575,
  7.1436 +	.get_speed_and_duplex = igb_get_speed_and_duplex_copper,
  7.1437 +};
  7.1438 +
  7.1439 +static struct e1000_phy_operations e1000_phy_ops_82575 = {
  7.1440 +	.acquire_phy          = igb_acquire_phy_82575,
  7.1441 +	.get_cfg_done         = igb_get_cfg_done_82575,
  7.1442 +	.release_phy          = igb_release_phy_82575,
  7.1443 +};
  7.1444 +
  7.1445 +static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
  7.1446 +	.acquire_nvm          = igb_acquire_nvm_82575,
  7.1447 +	.read_nvm             = igb_read_nvm_eerd,
  7.1448 +	.release_nvm          = igb_release_nvm_82575,
  7.1449 +	.write_nvm            = igb_write_nvm_spi,
  7.1450 +};
  7.1451 +
  7.1452 +const struct e1000_info e1000_82575_info = {
  7.1453 +	.get_invariants = igb_get_invariants_82575,
  7.1454 +	.mac_ops = &e1000_mac_ops_82575,
  7.1455 +	.phy_ops = &e1000_phy_ops_82575,
  7.1456 +	.nvm_ops = &e1000_nvm_ops_82575,
  7.1457 +};
  7.1458 +
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/drivers/net/igb/e1000_82575.h	Tue Feb 17 11:25:51 2009 +0000
     8.3 @@ -0,0 +1,157 @@
     8.4 +/*******************************************************************************
     8.5 +
     8.6 +  Intel(R) Gigabit Ethernet Linux driver
     8.7 +  Copyright(c) 2007 - 2008 Intel Corporation.
     8.8 +
     8.9 +  This program is free software; you can redistribute it and/or modify it
    8.10 +  under the terms and conditions of the GNU General Public License,
    8.11 +  version 2, as published by the Free Software Foundation.
    8.12 +
    8.13 +  This program is distributed in the hope it will be useful, but WITHOUT
    8.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    8.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    8.16 +  more details.
    8.17 +
    8.18 +  You should have received a copy of the GNU General Public License along with
    8.19 +  this program; if not, write to the Free Software Foundation, Inc.,
    8.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    8.21 +
    8.22 +  The full GNU General Public License is included in this distribution in
    8.23 +  the file called "COPYING".
    8.24 +
    8.25 +  Contact Information:
    8.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    8.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    8.28 +
    8.29 +*******************************************************************************/
    8.30 +
    8.31 +#ifndef _E1000_82575_H_
    8.32 +#define _E1000_82575_H_
    8.33 +
    8.34 +void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32);
    8.35 +extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
    8.36 +extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
    8.37 +
    8.38 +#define E1000_RAR_ENTRIES_82575   16
    8.39 +#define E1000_RAR_ENTRIES_82576   24
    8.40 +
    8.41 +/* SRRCTL bit definitions */
    8.42 +#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
    8.43 +#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
    8.44 +#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
    8.45 +#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
    8.46 +
    8.47 +#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
    8.48 +#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
    8.49 +#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
    8.50 +#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
    8.51 +
    8.52 +#define E1000_EICR_TX_QUEUE ( \
    8.53 +    E1000_EICR_TX_QUEUE0 |    \
    8.54 +    E1000_EICR_TX_QUEUE1 |    \
    8.55 +    E1000_EICR_TX_QUEUE2 |    \
    8.56 +    E1000_EICR_TX_QUEUE3)
    8.57 +
    8.58 +#define E1000_EICR_RX_QUEUE ( \
    8.59 +    E1000_EICR_RX_QUEUE0 |    \
    8.60 +    E1000_EICR_RX_QUEUE1 |    \
    8.61 +    E1000_EICR_RX_QUEUE2 |    \
    8.62 +    E1000_EICR_RX_QUEUE3)
    8.63 +
    8.64 +#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
    8.65 +#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
    8.66 +
    8.67 +/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
    8.68 +
    8.69 +/* Receive Descriptor - Advanced */
    8.70 +union e1000_adv_rx_desc {
    8.71 +	struct {
    8.72 +		__le64 pkt_addr;             /* Packet buffer address */
    8.73 +		__le64 hdr_addr;             /* Header buffer address */
    8.74 +	} read;
    8.75 +	struct {
    8.76 +		struct {
    8.77 +			struct {
    8.78 +				__le16 pkt_info;   /* RSS type, Packet type */
    8.79 +				__le16 hdr_info;   /* Split Header,
    8.80 +						    * header buffer length */
    8.81 +			} lo_dword;
    8.82 +			union {
    8.83 +				__le32 rss;          /* RSS Hash */
    8.84 +				struct {
    8.85 +					__le16 ip_id;    /* IP id */
    8.86 +					__le16 csum;     /* Packet Checksum */
    8.87 +				} csum_ip;
    8.88 +			} hi_dword;
    8.89 +		} lower;
    8.90 +		struct {
    8.91 +			__le32 status_error;     /* ext status/error */
    8.92 +			__le16 length;           /* Packet length */
    8.93 +			__le16 vlan;             /* VLAN tag */
    8.94 +		} upper;
    8.95 +	} wb;  /* writeback */
    8.96 +};
    8.97 +
    8.98 +#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
    8.99 +#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
   8.100 +
   8.101 +/* RSS Hash results */
   8.102 +
   8.103 +/* RSS Packet Types as indicated in the receive descriptor */
   8.104 +#define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
   8.105 +#define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
   8.106 +
   8.107 +/* Transmit Descriptor - Advanced */
   8.108 +union e1000_adv_tx_desc {
   8.109 +	struct {
   8.110 +		__le64 buffer_addr;    /* Address of descriptor's data buf */
   8.111 +		__le32 cmd_type_len;
   8.112 +		__le32 olinfo_status;
   8.113 +	} read;
   8.114 +	struct {
   8.115 +		__le64 rsvd;       /* Reserved */
   8.116 +		__le32 nxtseq_seed;
   8.117 +		__le32 status;
   8.118 +	} wb;
   8.119 +};
   8.120 +
   8.121 +/* Adv Transmit Descriptor Config Masks */
   8.122 +#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
   8.123 +#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
   8.124 +#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
   8.125 +#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
   8.126 +#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
   8.127 +#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
   8.128 +#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
   8.129 +
   8.130 +/* Context descriptors */
   8.131 +struct e1000_adv_tx_context_desc {
   8.132 +	__le32 vlan_macip_lens;
   8.133 +	__le32 seqnum_seed;
   8.134 +	__le32 type_tucmd_mlhl;
   8.135 +	__le32 mss_l4len_idx;
   8.136 +};
   8.137 +
   8.138 +#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
   8.139 +#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
   8.140 +#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
   8.141 +/* IPSec Encrypt Enable for ESP */
   8.142 +#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
   8.143 +#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
   8.144 +/* Adv ctxt IPSec SA IDX mask */
   8.145 +/* Adv ctxt IPSec ESP len mask */
   8.146 +
   8.147 +/* Additional Transmit Descriptor Control definitions */
   8.148 +#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
   8.149 +/* Tx Queue Arbitration Priority 0=low, 1=high */
   8.150 +
   8.151 +/* Additional Receive Descriptor Control definitions */
   8.152 +#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
   8.153 +
   8.154 +/* Direct Cache Access (DCA) definitions */
   8.155 +
   8.156 +
   8.157 +
   8.158 +#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
   8.159 +
   8.160 +#endif
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/drivers/net/igb/e1000_defines.h	Tue Feb 17 11:25:51 2009 +0000
     9.3 @@ -0,0 +1,771 @@
     9.4 +/*******************************************************************************
     9.5 +
     9.6 +  Intel(R) Gigabit Ethernet Linux driver
     9.7 +  Copyright(c) 2007 - 2008 Intel Corporation.
     9.8 +
     9.9 +  This program is free software; you can redistribute it and/or modify it
    9.10 +  under the terms and conditions of the GNU General Public License,
    9.11 +  version 2, as published by the Free Software Foundation.
    9.12 +
    9.13 +  This program is distributed in the hope it will be useful, but WITHOUT
    9.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    9.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    9.16 +  more details.
    9.17 +
    9.18 +  You should have received a copy of the GNU General Public License along with
    9.19 +  this program; if not, write to the Free Software Foundation, Inc.,
    9.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    9.21 +
    9.22 +  The full GNU General Public License is included in this distribution in
    9.23 +  the file called "COPYING".
    9.24 +
    9.25 +  Contact Information:
    9.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    9.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    9.28 +
    9.29 +*******************************************************************************/
    9.30 +
    9.31 +#ifndef _E1000_DEFINES_H_
    9.32 +#define _E1000_DEFINES_H_
    9.33 +
    9.34 +/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
    9.35 +#define REQ_TX_DESCRIPTOR_MULTIPLE  8
    9.36 +#define REQ_RX_DESCRIPTOR_MULTIPLE  8
    9.37 +
    9.38 +/* Definitions for power management and wakeup registers */
    9.39 +/* Wake Up Control */
    9.40 +#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
    9.41 +
    9.42 +/* Wake Up Filter Control */
    9.43 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
    9.44 +#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
    9.45 +#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
    9.46 +#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
    9.47 +#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
    9.48 +#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
    9.49 +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
    9.50 +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
    9.51 +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
    9.52 +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
    9.53 +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
    9.54 +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
    9.55 +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
    9.56 +
    9.57 +/* Wake Up Status */
    9.58 +
    9.59 +/* Wake Up Packet Length */
    9.60 +
    9.61 +/* Four Flexible Filters are supported */
    9.62 +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
    9.63 +
    9.64 +/* Each Flexible Filter is at most 128 (0x80) bytes in length */
    9.65 +#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
    9.66 +
    9.67 +
    9.68 +/* Extended Device Control */
    9.69 +#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
    9.70 +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
    9.71 +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
    9.72 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
    9.73 +#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
    9.74 +#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
    9.75 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
    9.76 +#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
    9.77 +#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
    9.78 +#define E1000_CTRL_EXT_EIAME          0x01000000
    9.79 +#define E1000_CTRL_EXT_IRCA           0x00000001
    9.80 +/* Interrupt delay cancellation */
    9.81 +/* Driver loaded bit for FW */
    9.82 +#define E1000_CTRL_EXT_DRV_LOAD       0x10000000
    9.83 +/* Interrupt acknowledge Auto-mask */
    9.84 +/* Clear Interrupt timers after IMS clear */
    9.85 +/* packet buffer parity error detection enabled */
    9.86 +/* descriptor FIFO parity error detection enable */
    9.87 +#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
    9.88 +#define E1000_I2CCMD_REG_ADDR_SHIFT   16
    9.89 +#define E1000_I2CCMD_PHY_ADDR_SHIFT   24
    9.90 +#define E1000_I2CCMD_OPCODE_READ      0x08000000
    9.91 +#define E1000_I2CCMD_OPCODE_WRITE     0x00000000
    9.92 +#define E1000_I2CCMD_READY            0x20000000
    9.93 +#define E1000_I2CCMD_ERROR            0x80000000
    9.94 +#define E1000_MAX_SGMII_PHY_REG_ADDR  255
    9.95 +#define E1000_I2CCMD_PHY_TIMEOUT      200
    9.96 +#define E1000_IVAR_VALID              0x80
    9.97 +#define E1000_GPIE_NSICR              0x00000001
    9.98 +#define E1000_GPIE_MSIX_MODE          0x00000010
    9.99 +#define E1000_GPIE_EIAME              0x40000000
   9.100 +#define E1000_GPIE_PBA                0x80000000
   9.101 +
   9.102 +/* Receive Descriptor bit definitions */
   9.103 +#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
   9.104 +#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
   9.105 +#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
   9.106 +#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
   9.107 +#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
   9.108 +#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
   9.109 +#define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
   9.110 +#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
   9.111 +#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
   9.112 +#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
   9.113 +#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
   9.114 +#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
   9.115 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
   9.116 +
   9.117 +#define E1000_RXDEXT_STATERR_CE    0x01000000
   9.118 +#define E1000_RXDEXT_STATERR_SE    0x02000000
   9.119 +#define E1000_RXDEXT_STATERR_SEQ   0x04000000
   9.120 +#define E1000_RXDEXT_STATERR_CXE   0x10000000
   9.121 +#define E1000_RXDEXT_STATERR_TCPE  0x20000000
   9.122 +#define E1000_RXDEXT_STATERR_IPE   0x40000000
   9.123 +#define E1000_RXDEXT_STATERR_RXE   0x80000000
   9.124 +
   9.125 +/* mask to determine if packets should be dropped due to frame errors */
   9.126 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
   9.127 +    E1000_RXD_ERR_CE  |                \
   9.128 +    E1000_RXD_ERR_SE  |                \
   9.129 +    E1000_RXD_ERR_SEQ |                \
   9.130 +    E1000_RXD_ERR_CXE |                \
   9.131 +    E1000_RXD_ERR_RXE)
   9.132 +
   9.133 +/* Same mask, but for extended and packet split descriptors */
   9.134 +#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
   9.135 +    E1000_RXDEXT_STATERR_CE  |            \
   9.136 +    E1000_RXDEXT_STATERR_SE  |            \
   9.137 +    E1000_RXDEXT_STATERR_SEQ |            \
   9.138 +    E1000_RXDEXT_STATERR_CXE |            \
   9.139 +    E1000_RXDEXT_STATERR_RXE)
   9.140 +
   9.141 +#define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
   9.142 +#define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
   9.143 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
   9.144 +#define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
   9.145 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
   9.146 +
   9.147 +
   9.148 +/* Management Control */
   9.149 +#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
   9.150 +#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
   9.151 +#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
   9.152 +/* Enable Neighbor Discovery Filtering */
   9.153 +#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
   9.154 +#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
   9.155 +/* Enable MAC address filtering */
   9.156 +#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
   9.157 +/* Enable MNG packets to host memory */
   9.158 +#define E1000_MANC_EN_MNG2HOST   0x00200000
   9.159 +/* Enable IP address filtering */
   9.160 +
   9.161 +
   9.162 +/* Receive Control */
   9.163 +#define E1000_RCTL_EN             0x00000002    /* enable */
   9.164 +#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
   9.165 +#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
   9.166 +#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
   9.167 +#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
   9.168 +#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
   9.169 +#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
   9.170 +#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
   9.171 +#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
   9.172 +#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
   9.173 +#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
   9.174 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
   9.175 +#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
   9.176 +#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
   9.177 +#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
   9.178 +#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
   9.179 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
   9.180 +#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
   9.181 +#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
   9.182 +#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
   9.183 +#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
   9.184 +#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
   9.185 +#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
   9.186 +#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
   9.187 +
   9.188 +/*
   9.189 + * Use byte values for the following shift parameters
   9.190 + * Usage:
   9.191 + *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
   9.192 + *                  E1000_PSRCTL_BSIZE0_MASK) |
   9.193 + *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
   9.194 + *                  E1000_PSRCTL_BSIZE1_MASK) |
   9.195 + *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
   9.196 + *                  E1000_PSRCTL_BSIZE2_MASK) |
   9.197 + *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
   9.198 + *                  E1000_PSRCTL_BSIZE3_MASK))
   9.199 + * where value0 = [128..16256],  default=256
   9.200 + *       value1 = [1024..64512], default=4096
   9.201 + *       value2 = [0..64512],    default=4096
   9.202 + *       value3 = [0..64512],    default=0
   9.203 + */
   9.204 +
   9.205 +#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
   9.206 +#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
   9.207 +#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
   9.208 +#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
   9.209 +
   9.210 +#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
   9.211 +#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
   9.212 +#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
   9.213 +#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
   9.214 +
   9.215 +/* SWFW_SYNC Definitions */
   9.216 +#define E1000_SWFW_EEP_SM   0x1
   9.217 +#define E1000_SWFW_PHY0_SM  0x2
   9.218 +#define E1000_SWFW_PHY1_SM  0x4
   9.219 +
   9.220 +/* FACTPS Definitions */
   9.221 +/* Device Control */
   9.222 +#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
   9.223 +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
   9.224 +#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
   9.225 +#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
   9.226 +#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
   9.227 +#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
   9.228 +#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
   9.229 +#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
   9.230 +#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
   9.231 +#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
   9.232 +#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
   9.233 +/* Defined polarity of Dock/Undock indication in SDP[0] */
   9.234 +/* Reset both PHY ports, through PHYRST_N pin */
   9.235 +/* enable link status from external LINK_0 and LINK_1 pins */
   9.236 +#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
   9.237 +#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
   9.238 +#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
   9.239 +#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
   9.240 +#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
   9.241 +#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
   9.242 +#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
   9.243 +#define E1000_CTRL_RST      0x04000000  /* Global reset */
   9.244 +#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
   9.245 +#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
   9.246 +#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
   9.247 +#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
   9.248 +/* Initiate an interrupt to manageability engine */
   9.249 +#define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
   9.250 +
   9.251 +/* Bit definitions for the Management Data IO (MDIO) and Management Data
   9.252 + * Clock (MDC) pins in the Device Control Register.
   9.253 + */
   9.254 +
   9.255 +#define E1000_CONNSW_ENRGSRC             0x4
   9.256 +#define E1000_PCS_CFG_PCS_EN             8
   9.257 +#define E1000_PCS_LCTL_FLV_LINK_UP       1
   9.258 +#define E1000_PCS_LCTL_FSV_100           2
   9.259 +#define E1000_PCS_LCTL_FSV_1000          4
   9.260 +#define E1000_PCS_LCTL_FDV_FULL          8
   9.261 +#define E1000_PCS_LCTL_FSD               0x10
   9.262 +#define E1000_PCS_LCTL_FORCE_LINK        0x20
   9.263 +#define E1000_PCS_LCTL_FORCE_FCTRL       0x80
   9.264 +#define E1000_PCS_LCTL_AN_ENABLE         0x10000
   9.265 +#define E1000_PCS_LCTL_AN_RESTART        0x20000
   9.266 +#define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
   9.267 +#define E1000_ENABLE_SERDES_LOOPBACK     0x0410
   9.268 +
   9.269 +#define E1000_PCS_LSTS_LINK_OK           1
   9.270 +#define E1000_PCS_LSTS_SPEED_100         2
   9.271 +#define E1000_PCS_LSTS_SPEED_1000        4
   9.272 +#define E1000_PCS_LSTS_DUPLEX_FULL       8
   9.273 +#define E1000_PCS_LSTS_SYNK_OK           0x10
   9.274 +
   9.275 +/* Device Status */
   9.276 +#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
   9.277 +#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
   9.278 +#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
   9.279 +#define E1000_STATUS_FUNC_SHIFT 2
   9.280 +#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
   9.281 +#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
   9.282 +#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
   9.283 +#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
   9.284 +/* Change in Dock/Undock state. Clear on write '0'. */
   9.285 +/* Status of Master requests. */
   9.286 +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
   9.287 +/* BMC external code execution disabled */
   9.288 +
   9.289 +/* Constants used to intrepret the masked PCI-X bus speed. */
   9.290 +
   9.291 +#define SPEED_10    10
   9.292 +#define SPEED_100   100
   9.293 +#define SPEED_1000  1000
   9.294 +#define HALF_DUPLEX 1
   9.295 +#define FULL_DUPLEX 2
   9.296 +
   9.297 +
   9.298 +#define ADVERTISE_10_HALF                 0x0001
   9.299 +#define ADVERTISE_10_FULL                 0x0002
   9.300 +#define ADVERTISE_100_HALF                0x0004
   9.301 +#define ADVERTISE_100_FULL                0x0008
   9.302 +#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
   9.303 +#define ADVERTISE_1000_FULL               0x0020
   9.304 +
   9.305 +/* 1000/H is not supported, nor spec-compliant. */
   9.306 +#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
   9.307 +				ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
   9.308 +						      ADVERTISE_1000_FULL)
   9.309 +#define E1000_ALL_NOT_GIG      (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
   9.310 +				ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
   9.311 +#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
   9.312 +#define E1000_ALL_10_SPEED     (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL)
   9.313 +#define E1000_ALL_FULL_DUPLEX  (ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \
   9.314 +						      ADVERTISE_1000_FULL)
   9.315 +#define E1000_ALL_HALF_DUPLEX  (ADVERTISE_10_HALF  |  ADVERTISE_100_HALF)
   9.316 +
   9.317 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
   9.318 +
   9.319 +/* LED Control */
   9.320 +#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
   9.321 +#define E1000_LEDCTL_LED0_MODE_SHIFT      0
   9.322 +#define E1000_LEDCTL_LED0_IVRT            0x00000040
   9.323 +#define E1000_LEDCTL_LED0_BLINK           0x00000080
   9.324 +
   9.325 +#define E1000_LEDCTL_MODE_LED_ON        0xE
   9.326 +#define E1000_LEDCTL_MODE_LED_OFF       0xF
   9.327 +
   9.328 +/* Transmit Descriptor bit definitions */
   9.329 +#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
   9.330 +#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
   9.331 +#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
   9.332 +#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
   9.333 +#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
   9.334 +#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
   9.335 +/* Extended desc bits for Linksec and timesync */
   9.336 +
   9.337 +/* Transmit Control */
   9.338 +#define E1000_TCTL_EN     0x00000002    /* enable tx */
   9.339 +#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
   9.340 +#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
   9.341 +#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
   9.342 +#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
   9.343 +
   9.344 +/* Transmit Arbitration Count */
   9.345 +
   9.346 +/* SerDes Control */
   9.347 +#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
   9.348 +
   9.349 +/* Receive Checksum Control */
   9.350 +#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
   9.351 +#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
   9.352 +#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
   9.353 +
   9.354 +/* Header split receive */
   9.355 +#define E1000_RFCTL_LEF        0x00040000
   9.356 +
   9.357 +/* Collision related configuration parameters */
   9.358 +#define E1000_COLLISION_THRESHOLD       15
   9.359 +#define E1000_CT_SHIFT                  4
   9.360 +#define E1000_COLLISION_DISTANCE        63
   9.361 +#define E1000_COLD_SHIFT                12
   9.362 +
   9.363 +/* Ethertype field values */
   9.364 +#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
   9.365 +
   9.366 +#define MAX_JUMBO_FRAME_SIZE    0x3F00
   9.367 +
   9.368 +/* Extended Configuration Control and Size */
   9.369 +#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
   9.370 +
   9.371 +/* PBA constants */
   9.372 +#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
   9.373 +#define E1000_PBA_24K 0x0018
   9.374 +#define E1000_PBA_34K 0x0022
   9.375 +#define E1000_PBA_64K 0x0040    /* 64KB */
   9.376 +
   9.377 +#define IFS_MAX       80
   9.378 +#define IFS_MIN       40
   9.379 +#define IFS_RATIO     4
   9.380 +#define IFS_STEP      10
   9.381 +#define MIN_NUM_XMITS 1000
   9.382 +
   9.383 +/* SW Semaphore Register */
   9.384 +#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
   9.385 +#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
   9.386 +
   9.387 +/* Interrupt Cause Read */
   9.388 +#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
   9.389 +#define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
   9.390 +#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
   9.391 +#define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
   9.392 +#define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
   9.393 +#define E1000_ICR_RXO           0x00000040 /* rx overrun */
   9.394 +#define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
   9.395 +#define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
   9.396 +#define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
   9.397 +#define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
   9.398 +#define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
   9.399 +#define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
   9.400 +#define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
   9.401 +#define E1000_ICR_TXD_LOW       0x00008000
   9.402 +#define E1000_ICR_SRPD          0x00010000
   9.403 +#define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
   9.404 +#define E1000_ICR_MNG           0x00040000 /* Manageability event */
   9.405 +#define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
   9.406 +/* If this bit asserted, the driver should claim the interrupt */
   9.407 +#define E1000_ICR_INT_ASSERTED  0x80000000
   9.408 +/* queue 0 Rx descriptor FIFO parity error */
   9.409 +#define E1000_ICR_RXD_FIFO_PAR0 0x00100000
   9.410 +/* queue 0 Tx descriptor FIFO parity error */
   9.411 +#define E1000_ICR_TXD_FIFO_PAR0 0x00200000
   9.412 +/* host arb read buffer parity error */
   9.413 +#define E1000_ICR_HOST_ARB_PAR  0x00400000
   9.414 +#define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
   9.415 +/* queue 1 Rx descriptor FIFO parity error */
   9.416 +#define E1000_ICR_RXD_FIFO_PAR1 0x01000000
   9.417 +/* queue 1 Tx descriptor FIFO parity error */
   9.418 +#define E1000_ICR_TXD_FIFO_PAR1 0x02000000
   9.419 +/* FW changed the status of DISSW bit in the FWSM */
   9.420 +#define E1000_ICR_DSW           0x00000020
   9.421 +/* LAN connected device generates an interrupt */
   9.422 +#define E1000_ICR_PHYINT        0x00001000
   9.423 +#define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
   9.424 +
   9.425 +/* Extended Interrupt Cause Read */
   9.426 +#define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
   9.427 +#define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
   9.428 +#define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
   9.429 +#define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
   9.430 +#define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
   9.431 +#define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
   9.432 +#define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
   9.433 +#define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
   9.434 +#define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
   9.435 +#define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
   9.436 +/* TCP Timer */
   9.437 +
   9.438 +/*
   9.439 + * This defines the bits that are set in the Interrupt Mask
   9.440 + * Set/Read Register.  Each bit is documented below:
   9.441 + *   o RXT0   = Receiver Timer Interrupt (ring 0)
   9.442 + *   o TXDW   = Transmit Descriptor Written Back
   9.443 + *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
   9.444 + *   o RXSEQ  = Receive Sequence Error
   9.445 + *   o LSC    = Link Status Change
   9.446 + */
   9.447 +#define IMS_ENABLE_MASK ( \
   9.448 +    E1000_IMS_RXT0   |    \
   9.449 +    E1000_IMS_TXDW   |    \
   9.450 +    E1000_IMS_RXDMT0 |    \
   9.451 +    E1000_IMS_RXSEQ  |    \
   9.452 +    E1000_IMS_LSC)
   9.453 +
   9.454 +/* Interrupt Mask Set */
   9.455 +#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
   9.456 +#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
   9.457 +#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
   9.458 +#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
   9.459 +#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
   9.460 +
   9.461 +/* Extended Interrupt Mask Set */
   9.462 +#define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
   9.463 +#define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
   9.464 +
   9.465 +/* Interrupt Cause Set */
   9.466 +#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
   9.467 +#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
   9.468 +
   9.469 +/* Extended Interrupt Cause Set */
   9.470 +
   9.471 +/* Transmit Descriptor Control */
   9.472 +/* Enable the counting of descriptors still to be processed. */
   9.473 +
   9.474 +/* Flow Control Constants */
   9.475 +#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
   9.476 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
   9.477 +#define FLOW_CONTROL_TYPE         0x8808
   9.478 +
   9.479 +/* 802.1q VLAN Packet Size */
   9.480 +#define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
   9.481 +#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
   9.482 +
   9.483 +/* Receive Address */
   9.484 +/*
   9.485 + * Number of high/low register pairs in the RAR. The RAR (Receive Address
   9.486 + * Registers) holds the directed and multicast addresses that we monitor.
   9.487 + * Technically, we have 16 spots.  However, we reserve one of these spots
   9.488 + * (RAR[15]) for our directed address used by controllers with
   9.489 + * manageability enabled, allowing us room for 15 multicast addresses.
   9.490 + */
   9.491 +#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
   9.492 +
   9.493 +/* Error Codes */
   9.494 +#define E1000_ERR_NVM      1
   9.495 +#define E1000_ERR_PHY      2
   9.496 +#define E1000_ERR_CONFIG   3
   9.497 +#define E1000_ERR_PARAM    4
   9.498 +#define E1000_ERR_MAC_INIT 5
   9.499 +#define E1000_ERR_RESET   9
   9.500 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10
   9.501 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11
   9.502 +#define E1000_BLK_PHY_RESET   12
   9.503 +#define E1000_ERR_SWFW_SYNC 13
   9.504 +#define E1000_NOT_IMPLEMENTED 14
   9.505 +
   9.506 +/* Loop limit on how long we wait for auto-negotiation to complete */
   9.507 +#define COPPER_LINK_UP_LIMIT              10
   9.508 +#define PHY_AUTO_NEG_LIMIT                45
   9.509 +#define PHY_FORCE_LIMIT                   20
   9.510 +/* Number of 100 microseconds we wait for PCI Express master disable */
   9.511 +#define MASTER_DISABLE_TIMEOUT      800
   9.512 +/* Number of milliseconds we wait for PHY configuration done after MAC reset */
   9.513 +#define PHY_CFG_TIMEOUT             100
   9.514 +/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
   9.515 +/* Number of milliseconds for NVM auto read done after MAC reset. */
   9.516 +#define AUTO_READ_DONE_TIMEOUT      10
   9.517 +
   9.518 +/* Flow Control */
   9.519 +#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
   9.520 +
   9.521 +/* Transmit Configuration Word */
   9.522 +#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
   9.523 +
   9.524 +/* Receive Configuration Word */
   9.525 +
   9.526 +/* PCI Express Control */
   9.527 +#define E1000_GCR_RXD_NO_SNOOP          0x00000001
   9.528 +#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
   9.529 +#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
   9.530 +#define E1000_GCR_TXD_NO_SNOOP          0x00000008
   9.531 +#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
   9.532 +#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
   9.533 +
   9.534 +#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
   9.535 +			   E1000_GCR_RXDSCW_NO_SNOOP      | \
   9.536 +			   E1000_GCR_RXDSCR_NO_SNOOP      | \
   9.537 +			   E1000_GCR_TXD_NO_SNOOP         | \
   9.538 +			   E1000_GCR_TXDSCW_NO_SNOOP      | \
   9.539 +			   E1000_GCR_TXDSCR_NO_SNOOP)
   9.540 +
   9.541 +/* PHY Control Register */
   9.542 +#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
   9.543 +#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
   9.544 +#define MII_CR_POWER_DOWN       0x0800  /* Power down */
   9.545 +#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
   9.546 +#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
   9.547 +#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
   9.548 +#define MII_CR_SPEED_1000       0x0040
   9.549 +#define MII_CR_SPEED_100        0x2000
   9.550 +#define MII_CR_SPEED_10         0x0000
   9.551 +
   9.552 +/* PHY Status Register */
   9.553 +#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
   9.554 +#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
   9.555 +
   9.556 +/* Autoneg Advertisement Register */
   9.557 +#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
   9.558 +#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
   9.559 +#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
   9.560 +#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
   9.561 +#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
   9.562 +#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
   9.563 +
   9.564 +/* Link Partner Ability Register (Base Page) */
   9.565 +#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
   9.566 +#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
   9.567 +
   9.568 +/* Autoneg Expansion Register */
   9.569 +
   9.570 +/* 1000BASE-T Control Register */
   9.571 +#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
   9.572 +#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
   9.573 +#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
   9.574 +					/* 0=Configure PHY as Slave */
   9.575 +#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
   9.576 +					/* 0=Automatic Master/Slave config */
   9.577 +
   9.578 +/* 1000BASE-T Status Register */
   9.579 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
   9.580 +#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
   9.581 +
   9.582 +
   9.583 +/* PHY 1000 MII Register/Bit Definitions */
   9.584 +/* PHY Registers defined by IEEE */
   9.585 +#define PHY_CONTROL      0x00 /* Control Register */
   9.586 +#define PHY_STATUS       0x01 /* Status Register */
   9.587 +#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
   9.588 +#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
   9.589 +#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
   9.590 +#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
   9.591 +#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
   9.592 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
   9.593 +
   9.594 +/* NVM Control */
   9.595 +#define E1000_EECD_SK        0x00000001 /* NVM Clock */
   9.596 +#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
   9.597 +#define E1000_EECD_DI        0x00000004 /* NVM Data In */
   9.598 +#define E1000_EECD_DO        0x00000008 /* NVM Data Out */
   9.599 +#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
   9.600 +#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
   9.601 +#define E1000_EECD_PRES      0x00000100 /* NVM Present */
   9.602 +/* NVM Addressing bits based on type 0=small, 1=large */
   9.603 +#define E1000_EECD_ADDR_BITS 0x00000400
   9.604 +#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
   9.605 +#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
   9.606 +#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
   9.607 +#define E1000_EECD_SIZE_EX_SHIFT     11
   9.608 +
   9.609 +/* Offset to data in NVM read/write registers */
   9.610 +#define E1000_NVM_RW_REG_DATA   16
   9.611 +#define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
   9.612 +#define E1000_NVM_RW_REG_START  1    /* Start operation */
   9.613 +#define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
   9.614 +#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
   9.615 +
   9.616 +/* NVM Word Offsets */
   9.617 +#define NVM_ID_LED_SETTINGS        0x0004
   9.618 +/* For SERDES output amplitude adjustment. */
   9.619 +#define NVM_INIT_CONTROL2_REG      0x000F
   9.620 +#define NVM_INIT_CONTROL3_PORT_A   0x0024
   9.621 +#define NVM_ALT_MAC_ADDR_PTR       0x0037
   9.622 +#define NVM_CHECKSUM_REG           0x003F
   9.623 +
   9.624 +#define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
   9.625 +#define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
   9.626 +
   9.627 +/* Mask bits for fields in Word 0x0f of the NVM */
   9.628 +#define NVM_WORD0F_PAUSE_MASK       0x3000
   9.629 +#define NVM_WORD0F_ASM_DIR          0x2000
   9.630 +
   9.631 +/* Mask bits for fields in Word 0x1a of the NVM */
   9.632 +
   9.633 +/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
   9.634 +#define NVM_SUM                    0xBABA
   9.635 +
   9.636 +#define NVM_PBA_OFFSET_0           8
   9.637 +#define NVM_PBA_OFFSET_1           9
   9.638 +#define NVM_WORD_SIZE_BASE_SHIFT   6
   9.639 +
   9.640 +/* NVM Commands - Microwire */
   9.641 +
   9.642 +/* NVM Commands - SPI */
   9.643 +#define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
   9.644 +#define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
   9.645 +#define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
   9.646 +#define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
   9.647 +#define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
   9.648 +
   9.649 +/* SPI NVM Status Register */
   9.650 +#define NVM_STATUS_RDY_SPI         0x01
   9.651 +
   9.652 +/* Word definitions for ID LED Settings */
   9.653 +#define ID_LED_RESERVED_0000 0x0000
   9.654 +#define ID_LED_RESERVED_FFFF 0xFFFF
   9.655 +#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
   9.656 +			      (ID_LED_OFF1_OFF2 <<  8) | \
   9.657 +			      (ID_LED_DEF1_DEF2 <<  4) | \
   9.658 +			      (ID_LED_DEF1_DEF2))
   9.659 +#define ID_LED_DEF1_DEF2     0x1
   9.660 +#define ID_LED_DEF1_ON2      0x2
   9.661 +#define ID_LED_DEF1_OFF2     0x3
   9.662 +#define ID_LED_ON1_DEF2      0x4
   9.663 +#define ID_LED_ON1_ON2       0x5
   9.664 +#define ID_LED_ON1_OFF2      0x6
   9.665 +#define ID_LED_OFF1_DEF2     0x7
   9.666 +#define ID_LED_OFF1_ON2      0x8
   9.667 +#define ID_LED_OFF1_OFF2     0x9
   9.668 +
   9.669 +#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
   9.670 +#define IGP_ACTIVITY_LED_ENABLE 0x0300
   9.671 +#define IGP_LED3_MODE           0x07000000
   9.672 +
   9.673 +/* PCI/PCI-X/PCI-EX Config space */
   9.674 +#define PCI_HEADER_TYPE_REGISTER     0x0E
   9.675 +#define PCIE_LINK_STATUS             0x12
   9.676 +
   9.677 +#define PCI_HEADER_TYPE_MULTIFUNC    0x80
   9.678 +#define PCIE_LINK_WIDTH_MASK         0x3F0
   9.679 +#define PCIE_LINK_WIDTH_SHIFT        4
   9.680 +
   9.681 +#define PHY_REVISION_MASK      0xFFFFFFF0
   9.682 +#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
   9.683 +#define MAX_PHY_MULTI_PAGE_REG 0xF
   9.684 +
   9.685 +/* Bit definitions for valid PHY IDs. */
   9.686 +/*
   9.687 + * I = Integrated
   9.688 + * E = External
   9.689 + */
   9.690 +#define M88E1111_I_PHY_ID    0x01410CC0
   9.691 +#define IGP03E1000_E_PHY_ID  0x02A80390
   9.692 +#define M88_VENDOR           0x0141
   9.693 +
   9.694 +/* M88E1000 Specific Registers */
   9.695 +#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
   9.696 +#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
   9.697 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
   9.698 +
   9.699 +#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
   9.700 +#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
   9.701 +
   9.702 +/* M88E1000 PHY Specific Control Register */
   9.703 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
   9.704 +/* 1=CLK125 low, 0=CLK125 toggling */
   9.705 +#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
   9.706 +					       /* Manual MDI configuration */
   9.707 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
   9.708 +/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
   9.709 +#define M88E1000_PSCR_AUTO_X_1000T     0x0040
   9.710 +/* Auto crossover enabled all speeds */
   9.711 +#define M88E1000_PSCR_AUTO_X_MODE      0x0060
   9.712 +/*
   9.713 + * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
   9.714 + * 0=Normal 10BASE-T Rx Threshold
   9.715 + */
   9.716 +/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
   9.717 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
   9.718 +
   9.719 +/* M88E1000 PHY Specific Status Register */
   9.720 +#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
   9.721 +#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
   9.722 +#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
   9.723 +/*
   9.724 + * 0 = <50M
   9.725 + * 1 = 50-80M
   9.726 + * 2 = 80-110M
   9.727 + * 3 = 110-140M
   9.728 + * 4 = >140M
   9.729 + */
   9.730 +#define M88E1000_PSSR_CABLE_LENGTH       0x0380
   9.731 +#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
   9.732 +#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
   9.733 +
   9.734 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
   9.735 +
   9.736 +/* M88E1000 Extended PHY Specific Control Register */
   9.737 +/*
   9.738 + * 1 = Lost lock detect enabled.
   9.739 + * Will assert lost lock and bring
   9.740 + * link down if idle not seen
   9.741 + * within 1ms in 1000BASE-T
   9.742 + */
   9.743 +/*
   9.744 + * Number of times we will attempt to autonegotiate before downshifting if we
   9.745 + * are the master
   9.746 + */
   9.747 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
   9.748 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
   9.749 +/*
   9.750 + * Number of times we will attempt to autonegotiate before downshifting if we
   9.751 + * are the slave
   9.752 + */
   9.753 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
   9.754 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
   9.755 +#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
   9.756 +
   9.757 +/* M88EC018 Rev 2 specific DownShift settings */
   9.758 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
   9.759 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
   9.760 +
   9.761 +/* MDI Control */
   9.762 +#define E1000_MDIC_REG_SHIFT 16
   9.763 +#define E1000_MDIC_PHY_SHIFT 21
   9.764 +#define E1000_MDIC_OP_WRITE  0x04000000
   9.765 +#define E1000_MDIC_OP_READ   0x08000000
   9.766 +#define E1000_MDIC_READY     0x10000000
   9.767 +#define E1000_MDIC_ERROR     0x40000000
   9.768 +
   9.769 +/* SerDes Control */
   9.770 +#define E1000_GEN_CTL_READY             0x80000000
   9.771 +#define E1000_GEN_CTL_ADDRESS_SHIFT     8
   9.772 +#define E1000_GEN_POLL_TIMEOUT          640
   9.773 +
   9.774 +#endif
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/drivers/net/igb/e1000_hw.h	Tue Feb 17 11:25:51 2009 +0000
    10.3 @@ -0,0 +1,603 @@
    10.4 +/*******************************************************************************
    10.5 +
    10.6 +  Intel(R) Gigabit Ethernet Linux driver
    10.7 +  Copyright(c) 2007 Intel Corporation.
    10.8 +
    10.9 +  This program is free software; you can redistribute it and/or modify it
   10.10 +  under the terms and conditions of the GNU General Public License,
   10.11 +  version 2, as published by the Free Software Foundation.
   10.12 +
   10.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   10.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   10.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   10.16 +  more details.
   10.17 +
   10.18 +  You should have received a copy of the GNU General Public License along with
   10.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   10.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   10.21 +
   10.22 +  The full GNU General Public License is included in this distribution in
   10.23 +  the file called "COPYING".
   10.24 +
   10.25 +  Contact Information:
   10.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   10.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   10.28 +
   10.29 +*******************************************************************************/
   10.30 +
   10.31 +#ifndef _E1000_HW_H_
   10.32 +#define _E1000_HW_H_
   10.33 +
   10.34 +#include <linux/types.h>
   10.35 +#include <linux/delay.h>
   10.36 +#include <linux/io.h>
   10.37 +
   10.38 +#include "e1000_mac.h"
   10.39 +#include "e1000_regs.h"
   10.40 +#include "e1000_defines.h"
   10.41 +#include "igb_compat.h"
   10.42 +
   10.43 +struct e1000_hw;
   10.44 +
   10.45 +#define E1000_DEV_ID_82576                    0x10C9
   10.46 +#define E1000_DEV_ID_82576_FIBER              0x10E6
   10.47 +#define E1000_DEV_ID_82576_SERDES             0x10E7
   10.48 +#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
   10.49 +#define E1000_DEV_ID_82575EB_COPPER           0x10A7
   10.50 +#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
   10.51 +#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
   10.52 +
   10.53 +#define E1000_REVISION_2 2
   10.54 +#define E1000_REVISION_4 4
   10.55 +
   10.56 +#define E1000_FUNC_1     1
   10.57 +
   10.58 +enum e1000_mac_type {
   10.59 +	e1000_undefined = 0,
   10.60 +	e1000_82575,
   10.61 +	e1000_82576,
   10.62 +	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
   10.63 +};
   10.64 +
   10.65 +enum e1000_media_type {
   10.66 +	e1000_media_type_unknown = 0,
   10.67 +	e1000_media_type_copper = 1,
   10.68 +	e1000_media_type_fiber = 2,
   10.69 +	e1000_media_type_internal_serdes = 3,
   10.70 +	e1000_num_media_types
   10.71 +};
   10.72 +
   10.73 +enum e1000_nvm_type {
   10.74 +	e1000_nvm_unknown = 0,
   10.75 +	e1000_nvm_none,
   10.76 +	e1000_nvm_eeprom_spi,
   10.77 +	e1000_nvm_eeprom_microwire,
   10.78 +	e1000_nvm_flash_hw,
   10.79 +	e1000_nvm_flash_sw
   10.80 +};
   10.81 +
   10.82 +enum e1000_nvm_override {
   10.83 +	e1000_nvm_override_none = 0,
   10.84 +	e1000_nvm_override_spi_small,
   10.85 +	e1000_nvm_override_spi_large,
   10.86 +	e1000_nvm_override_microwire_small,
   10.87 +	e1000_nvm_override_microwire_large
   10.88 +};
   10.89 +
   10.90 +enum e1000_phy_type {
   10.91 +	e1000_phy_unknown = 0,
   10.92 +	e1000_phy_none,
   10.93 +	e1000_phy_m88,
   10.94 +	e1000_phy_igp,
   10.95 +	e1000_phy_igp_2,
   10.96 +	e1000_phy_gg82563,
   10.97 +	e1000_phy_igp_3,
   10.98 +	e1000_phy_ife,
   10.99 +};
  10.100 +
  10.101 +enum e1000_bus_type {
  10.102 +	e1000_bus_type_unknown = 0,
  10.103 +	e1000_bus_type_pci,
  10.104 +	e1000_bus_type_pcix,
  10.105 +	e1000_bus_type_pci_express,
  10.106 +	e1000_bus_type_reserved
  10.107 +};
  10.108 +
  10.109 +enum e1000_bus_speed {
  10.110 +	e1000_bus_speed_unknown = 0,
  10.111 +	e1000_bus_speed_33,
  10.112 +	e1000_bus_speed_66,
  10.113 +	e1000_bus_speed_100,
  10.114 +	e1000_bus_speed_120,
  10.115 +	e1000_bus_speed_133,
  10.116 +	e1000_bus_speed_2500,
  10.117 +	e1000_bus_speed_5000,
  10.118 +	e1000_bus_speed_reserved
  10.119 +};
  10.120 +
  10.121 +enum e1000_bus_width {
  10.122 +	e1000_bus_width_unknown = 0,
  10.123 +	e1000_bus_width_pcie_x1,
  10.124 +	e1000_bus_width_pcie_x2,
  10.125 +	e1000_bus_width_pcie_x4 = 4,
  10.126 +	e1000_bus_width_pcie_x8 = 8,
  10.127 +	e1000_bus_width_32,
  10.128 +	e1000_bus_width_64,
  10.129 +	e1000_bus_width_reserved
  10.130 +};
  10.131 +
  10.132 +enum e1000_1000t_rx_status {
  10.133 +	e1000_1000t_rx_status_not_ok = 0,
  10.134 +	e1000_1000t_rx_status_ok,
  10.135 +	e1000_1000t_rx_status_undefined = 0xFF
  10.136 +};
  10.137 +
  10.138 +enum e1000_rev_polarity {
  10.139 +	e1000_rev_polarity_normal = 0,
  10.140 +	e1000_rev_polarity_reversed,
  10.141 +	e1000_rev_polarity_undefined = 0xFF
  10.142 +};
  10.143 +
  10.144 +enum e1000_fc_type {
  10.145 +	e1000_fc_none = 0,
  10.146 +	e1000_fc_rx_pause,
  10.147 +	e1000_fc_tx_pause,
  10.148 +	e1000_fc_full,
  10.149 +	e1000_fc_default = 0xFF
  10.150 +};
  10.151 +
  10.152 +
  10.153 +/* Receive Descriptor */
  10.154 +struct e1000_rx_desc {
  10.155 +	__le64 buffer_addr; /* Address of the descriptor's data buffer */
  10.156 +	__le16 length;      /* Length of data DMAed into data buffer */
  10.157 +	__le16 csum;        /* Packet checksum */
  10.158 +	u8  status;      /* Descriptor status */
  10.159 +	u8  errors;      /* Descriptor Errors */
  10.160 +	__le16 special;
  10.161 +};
  10.162 +
  10.163 +/* Receive Descriptor - Extended */
  10.164 +union e1000_rx_desc_extended {
  10.165 +	struct {
  10.166 +		__le64 buffer_addr;
  10.167 +		__le64 reserved;
  10.168 +	} read;
  10.169 +	struct {
  10.170 +		struct {
  10.171 +			__le32 mrq;              /* Multiple Rx Queues */
  10.172 +			union {
  10.173 +				__le32 rss;            /* RSS Hash */
  10.174 +				struct {
  10.175 +					__le16 ip_id;  /* IP id */
  10.176 +					__le16 csum;   /* Packet Checksum */
  10.177 +				} csum_ip;
  10.178 +			} hi_dword;
  10.179 +		} lower;
  10.180 +		struct {
  10.181 +			__le32 status_error;     /* ext status/error */
  10.182 +			__le16 length;
  10.183 +			__le16 vlan;             /* VLAN tag */
  10.184 +		} upper;
  10.185 +	} wb;  /* writeback */
  10.186 +};
  10.187 +
  10.188 +#define MAX_PS_BUFFERS 4
  10.189 +/* Receive Descriptor - Packet Split */
  10.190 +union e1000_rx_desc_packet_split {
  10.191 +	struct {
  10.192 +		/* one buffer for protocol header(s), three data buffers */
  10.193 +		__le64 buffer_addr[MAX_PS_BUFFERS];
  10.194 +	} read;
  10.195 +	struct {
  10.196 +		struct {
  10.197 +			__le32 mrq;              /* Multiple Rx Queues */
  10.198 +			union {
  10.199 +				__le32 rss;              /* RSS Hash */
  10.200 +				struct {
  10.201 +					__le16 ip_id;    /* IP id */
  10.202 +					__le16 csum;     /* Packet Checksum */
  10.203 +				} csum_ip;
  10.204 +			} hi_dword;
  10.205 +		} lower;
  10.206 +		struct {
  10.207 +			__le32 status_error;     /* ext status/error */
  10.208 +			__le16 length0;          /* length of buffer 0 */
  10.209 +			__le16 vlan;             /* VLAN tag */
  10.210 +		} middle;
  10.211 +		struct {
  10.212 +			__le16 header_status;
  10.213 +			__le16 length[3];        /* length of buffers 1-3 */
  10.214 +		} upper;
  10.215 +		__le64 reserved;
  10.216 +	} wb; /* writeback */
  10.217 +};
  10.218 +
  10.219 +/* Transmit Descriptor */
  10.220 +struct e1000_tx_desc {
  10.221 +	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
  10.222 +	union {
  10.223 +		__le32 data;
  10.224 +		struct {
  10.225 +			__le16 length;    /* Data buffer length */
  10.226 +			u8 cso;        /* Checksum offset */
  10.227 +			u8 cmd;        /* Descriptor control */
  10.228 +		} flags;
  10.229 +	} lower;
  10.230 +	union {
  10.231 +		__le32 data;
  10.232 +		struct {
  10.233 +			u8 status;     /* Descriptor status */
  10.234 +			u8 css;        /* Checksum start */
  10.235 +			__le16 special;
  10.236 +		} fields;
  10.237 +	} upper;
  10.238 +};
  10.239 +
  10.240 +/* Offload Context Descriptor */
  10.241 +struct e1000_context_desc {
  10.242 +	union {
  10.243 +		__le32 ip_config;
  10.244 +		struct {
  10.245 +			u8 ipcss;      /* IP checksum start */
  10.246 +			u8 ipcso;      /* IP checksum offset */
  10.247 +			__le16 ipcse;     /* IP checksum end */
  10.248 +		} ip_fields;
  10.249 +	} lower_setup;
  10.250 +	union {
  10.251 +		__le32 tcp_config;
  10.252 +		struct {
  10.253 +			u8 tucss;      /* TCP checksum start */
  10.254 +			u8 tucso;      /* TCP checksum offset */
  10.255 +			__le16 tucse;     /* TCP checksum end */
  10.256 +		} tcp_fields;
  10.257 +	} upper_setup;
  10.258 +	__le32 cmd_and_length;
  10.259 +	union {
  10.260 +		__le32 data;
  10.261 +		struct {
  10.262 +			u8 status;     /* Descriptor status */
  10.263 +			u8 hdr_len;    /* Header length */
  10.264 +			__le16 mss;       /* Maximum segment size */
  10.265 +		} fields;
  10.266 +	} tcp_seg_setup;
  10.267 +};
  10.268 +
  10.269 +/* Offload data descriptor */
  10.270 +struct e1000_data_desc {
  10.271 +	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
  10.272 +	union {
  10.273 +		__le32 data;
  10.274 +		struct {
  10.275 +			__le16 length;    /* Data buffer length */
  10.276 +			u8 typ_len_ext;
  10.277 +			u8 cmd;
  10.278 +		} flags;
  10.279 +	} lower;
  10.280 +	union {
  10.281 +		__le32 data;
  10.282 +		struct {
  10.283 +			u8 status;     /* Descriptor status */
  10.284 +			u8 popts;      /* Packet Options */
  10.285 +			__le16 special;
  10.286 +		} fields;
  10.287 +	} upper;
  10.288 +};
  10.289 +
  10.290 +/* Statistics counters collected by the MAC */
  10.291 +struct e1000_hw_stats {
  10.292 +	u64 crcerrs;
  10.293 +	u64 algnerrc;
  10.294 +	u64 symerrs;
  10.295 +	u64 rxerrc;
  10.296 +	u64 mpc;
  10.297 +	u64 scc;
  10.298 +	u64 ecol;
  10.299 +	u64 mcc;
  10.300 +	u64 latecol;
  10.301 +	u64 colc;
  10.302 +	u64 dc;
  10.303 +	u64 tncrs;
  10.304 +	u64 sec;
  10.305 +	u64 cexterr;
  10.306 +	u64 rlec;
  10.307 +	u64 xonrxc;
  10.308 +	u64 xontxc;
  10.309 +	u64 xoffrxc;
  10.310 +	u64 xofftxc;
  10.311 +	u64 fcruc;
  10.312 +	u64 prc64;
  10.313 +	u64 prc127;
  10.314 +	u64 prc255;
  10.315 +	u64 prc511;
  10.316 +	u64 prc1023;
  10.317 +	u64 prc1522;
  10.318 +	u64 gprc;
  10.319 +	u64 bprc;
  10.320 +	u64 mprc;
  10.321 +	u64 gptc;
  10.322 +	u64 gorc;
  10.323 +	u64 gotc;
  10.324 +	u64 rnbc;
  10.325 +	u64 ruc;
  10.326 +	u64 rfc;
  10.327 +	u64 roc;
  10.328 +	u64 rjc;
  10.329 +	u64 mgprc;
  10.330 +	u64 mgpdc;
  10.331 +	u64 mgptc;
  10.332 +	u64 tor;
  10.333 +	u64 tot;
  10.334 +	u64 tpr;
  10.335 +	u64 tpt;
  10.336 +	u64 ptc64;
  10.337 +	u64 ptc127;
  10.338 +	u64 ptc255;
  10.339 +	u64 ptc511;
  10.340 +	u64 ptc1023;
  10.341 +	u64 ptc1522;
  10.342 +	u64 mptc;
  10.343 +	u64 bptc;
  10.344 +	u64 tsctc;
  10.345 +	u64 tsctfc;
  10.346 +	u64 iac;
  10.347 +	u64 icrxptc;
  10.348 +	u64 icrxatc;
  10.349 +	u64 ictxptc;
  10.350 +	u64 ictxatc;
  10.351 +	u64 ictxqec;
  10.352 +	u64 ictxqmtc;
  10.353 +	u64 icrxdmtc;
  10.354 +	u64 icrxoc;
  10.355 +	u64 cbtmpc;
  10.356 +	u64 htdpmc;
  10.357 +	u64 cbrdpc;
  10.358 +	u64 cbrmpc;
  10.359 +	u64 rpthc;
  10.360 +	u64 hgptc;
  10.361 +	u64 htcbdpc;
  10.362 +	u64 hgorc;
  10.363 +	u64 hgotc;
  10.364 +	u64 lenerrs;
  10.365 +	u64 scvpc;
  10.366 +	u64 hrmpc;
  10.367 +};
  10.368 +
  10.369 +struct e1000_phy_stats {
  10.370 +	u32 idle_errors;
  10.371 +	u32 receive_errors;
  10.372 +};
  10.373 +
  10.374 +struct e1000_host_mng_dhcp_cookie {
  10.375 +	u32 signature;
  10.376 +	u8  status;
  10.377 +	u8  reserved0;
  10.378 +	u16 vlan_id;
  10.379 +	u32 reserved1;
  10.380 +	u16 reserved2;
  10.381 +	u8  reserved3;
  10.382 +	u8  checksum;
  10.383 +};
  10.384 +
  10.385 +/* Host Interface "Rev 1" */
  10.386 +struct e1000_host_command_header {
  10.387 +	u8 command_id;
  10.388 +	u8 command_length;
  10.389 +	u8 command_options;
  10.390 +	u8 checksum;
  10.391 +};
  10.392 +
  10.393 +#define E1000_HI_MAX_DATA_LENGTH     252
  10.394 +struct e1000_host_command_info {
  10.395 +	struct e1000_host_command_header command_header;
  10.396 +	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
  10.397 +};
  10.398 +
  10.399 +/* Host Interface "Rev 2" */
  10.400 +struct e1000_host_mng_command_header {
  10.401 +	u8  command_id;
  10.402 +	u8  checksum;
  10.403 +	u16 reserved1;
  10.404 +	u16 reserved2;
  10.405 +	u16 command_length;
  10.406 +};
  10.407 +
  10.408 +#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
  10.409 +struct e1000_host_mng_command_info {
  10.410 +	struct e1000_host_mng_command_header command_header;
  10.411 +	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
  10.412 +};
  10.413 +
  10.414 +#include "e1000_mac.h"
  10.415 +#include "e1000_phy.h"
  10.416 +#include "e1000_nvm.h"
  10.417 +
  10.418 +struct e1000_mac_operations {
  10.419 +	s32  (*check_for_link)(struct e1000_hw *);
  10.420 +	s32  (*reset_hw)(struct e1000_hw *);
  10.421 +	s32  (*init_hw)(struct e1000_hw *);
  10.422 +	bool (*check_mng_mode)(struct e1000_hw *);
  10.423 +	s32  (*setup_physical_interface)(struct e1000_hw *);
  10.424 +	void (*rar_set)(struct e1000_hw *, u8 *, u32);
  10.425 +	s32  (*read_mac_addr)(struct e1000_hw *);
  10.426 +	s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
  10.427 +};
  10.428 +
  10.429 +struct e1000_phy_operations {
  10.430 +	s32  (*acquire_phy)(struct e1000_hw *);
  10.431 +	s32  (*check_reset_block)(struct e1000_hw *);
  10.432 +	s32  (*force_speed_duplex)(struct e1000_hw *);
  10.433 +	s32  (*get_cfg_done)(struct e1000_hw *hw);
  10.434 +	s32  (*get_cable_length)(struct e1000_hw *);
  10.435 +	s32  (*get_phy_info)(struct e1000_hw *);
  10.436 +	s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
  10.437 +	void (*release_phy)(struct e1000_hw *);
  10.438 +	s32  (*reset_phy)(struct e1000_hw *);
  10.439 +	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
  10.440 +	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
  10.441 +	s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
  10.442 +};
  10.443 +
  10.444 +struct e1000_nvm_operations {
  10.445 +	s32  (*acquire_nvm)(struct e1000_hw *);
  10.446 +	s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
  10.447 +	void (*release_nvm)(struct e1000_hw *);
  10.448 +	s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
  10.449 +};
  10.450 +
  10.451 +struct e1000_info {
  10.452 +	s32 (*get_invariants)(struct e1000_hw *);
  10.453 +	struct e1000_mac_operations *mac_ops;
  10.454 +	struct e1000_phy_operations *phy_ops;
  10.455 +	struct e1000_nvm_operations *nvm_ops;
  10.456 +};
  10.457 +
  10.458 +extern const struct e1000_info e1000_82575_info;
  10.459 +
  10.460 +struct e1000_mac_info {
  10.461 +	struct e1000_mac_operations ops;
  10.462 +
  10.463 +	u8 addr[6];
  10.464 +	u8 perm_addr[6];
  10.465 +
  10.466 +	enum e1000_mac_type type;
  10.467 +
  10.468 +	u32 collision_delta;
  10.469 +	u32 ledctl_default;
  10.470 +	u32 ledctl_mode1;
  10.471 +	u32 ledctl_mode2;
  10.472 +	u32 mc_filter_type;
  10.473 +	u32 tx_packet_delta;
  10.474 +	u32 txcw;
  10.475 +
  10.476 +	u16 current_ifs_val;
  10.477 +	u16 ifs_max_val;
  10.478 +	u16 ifs_min_val;
  10.479 +	u16 ifs_ratio;
  10.480 +	u16 ifs_step_size;
  10.481 +	u16 mta_reg_count;
  10.482 +	u16 rar_entry_count;
  10.483 +
  10.484 +	u8  forced_speed_duplex;
  10.485 +
  10.486 +	bool adaptive_ifs;
  10.487 +	bool arc_subsystem_valid;
  10.488 +	bool asf_firmware_present;
  10.489 +	bool autoneg;
  10.490 +	bool autoneg_failed;
  10.491 +	bool disable_av;
  10.492 +	bool disable_hw_init_bits;
  10.493 +	bool get_link_status;
  10.494 +	bool ifs_params_forced;
  10.495 +	bool in_ifs_mode;
  10.496 +	bool report_tx_early;
  10.497 +	bool serdes_has_link;
  10.498 +	bool tx_pkt_filtering;
  10.499 +};
  10.500 +
  10.501 +struct e1000_phy_info {
  10.502 +	struct e1000_phy_operations ops;
  10.503 +
  10.504 +	enum e1000_phy_type type;
  10.505 +
  10.506 +	enum e1000_1000t_rx_status local_rx;
  10.507 +	enum e1000_1000t_rx_status remote_rx;
  10.508 +	enum e1000_ms_type ms_type;
  10.509 +	enum e1000_ms_type original_ms_type;
  10.510 +	enum e1000_rev_polarity cable_polarity;
  10.511 +	enum e1000_smart_speed smart_speed;
  10.512 +
  10.513 +	u32 addr;
  10.514 +	u32 id;
  10.515 +	u32 reset_delay_us; /* in usec */
  10.516 +	u32 revision;
  10.517 +
  10.518 +	enum e1000_media_type media_type;
  10.519 +
  10.520 +	u16 autoneg_advertised;
  10.521 +	u16 autoneg_mask;
  10.522 +	u16 cable_length;
  10.523 +	u16 max_cable_length;
  10.524 +	u16 min_cable_length;
  10.525 +
  10.526 +	u8 mdix;
  10.527 +
  10.528 +	bool disable_polarity_correction;
  10.529 +	bool is_mdix;
  10.530 +	bool polarity_correction;
  10.531 +	bool reset_disable;
  10.532 +	bool speed_downgraded;
  10.533 +	bool autoneg_wait_to_complete;
  10.534 +};
  10.535 +
  10.536 +struct e1000_nvm_info {
  10.537 +	struct e1000_nvm_operations ops;
  10.538 +
  10.539 +	enum e1000_nvm_type type;
  10.540 +	enum e1000_nvm_override override;
  10.541 +
  10.542 +	u32 flash_bank_size;
  10.543 +	u32 flash_base_addr;
  10.544 +
  10.545 +	u16 word_size;
  10.546 +	u16 delay_usec;
  10.547 +	u16 address_bits;
  10.548 +	u16 opcode_bits;
  10.549 +	u16 page_size;
  10.550 +};
  10.551 +
  10.552 +struct e1000_bus_info {
  10.553 +	enum e1000_bus_type type;
  10.554 +	enum e1000_bus_speed speed;
  10.555 +	enum e1000_bus_width width;
  10.556 +
  10.557 +	u32 snoop;
  10.558 +
  10.559 +	u16 func;
  10.560 +	u16 pci_cmd_word;
  10.561 +};
  10.562 +
  10.563 +struct e1000_fc_info {
  10.564 +	u32 high_water;     /* Flow control high-water mark */
  10.565 +	u32 low_water;      /* Flow control low-water mark */
  10.566 +	u16 pause_time;     /* Flow control pause timer */
  10.567 +	bool send_xon;      /* Flow control send XON */
  10.568 +	bool strict_ieee;   /* Strict IEEE mode */
  10.569 +	enum e1000_fc_type type; /* Type of flow control */
  10.570 +	enum e1000_fc_type original_type;
  10.571 +};
  10.572 +
  10.573 +struct e1000_hw {
  10.574 +	void *back;
  10.575 +	void *dev_spec;
  10.576 +
  10.577 +	u8 __iomem *hw_addr;
  10.578 +	u8 __iomem *flash_address;
  10.579 +	unsigned long io_base;
  10.580 +
  10.581 +	struct e1000_mac_info  mac;
  10.582 +	struct e1000_fc_info   fc;
  10.583 +	struct e1000_phy_info  phy;
  10.584 +	struct e1000_nvm_info  nvm;
  10.585 +	struct e1000_bus_info  bus;
  10.586 +	struct e1000_host_mng_dhcp_cookie mng_cookie;
  10.587 +
  10.588 +	u32 dev_spec_size;
  10.589 +
  10.590 +	u16 device_id;
  10.591 +	u16 subsystem_vendor_id;
  10.592 +	u16 subsystem_device_id;
  10.593 +	u16 vendor_id;
  10.594 +
  10.595 +	u8  revision_id;
  10.596 +};
  10.597 +
  10.598 +#ifdef DEBUG
  10.599 +extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
  10.600 +#define hw_dbg(format, arg...) \
  10.601 +	printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
  10.602 +#else
  10.603 +#define hw_dbg(format, arg...)
  10.604 +#endif
  10.605 +
  10.606 +#endif
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/drivers/net/igb/e1000_mac.c	Tue Feb 17 11:25:51 2009 +0000
    11.3 @@ -0,0 +1,1421 @@
    11.4 +/*******************************************************************************
    11.5 +
    11.6 +  Intel(R) Gigabit Ethernet Linux driver
    11.7 +  Copyright(c) 2007 Intel Corporation.
    11.8 +
    11.9 +  This program is free software; you can redistribute it and/or modify it
   11.10 +  under the terms and conditions of the GNU General Public License,
   11.11 +  version 2, as published by the Free Software Foundation.
   11.12 +
   11.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   11.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   11.16 +  more details.
   11.17 +
   11.18 +  You should have received a copy of the GNU General Public License along with
   11.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   11.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   11.21 +
   11.22 +  The full GNU General Public License is included in this distribution in
   11.23 +  the file called "COPYING".
   11.24 +
   11.25 +  Contact Information:
   11.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   11.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   11.28 +
   11.29 +*******************************************************************************/
   11.30 +
   11.31 +#include <linux/if_ether.h>
   11.32 +#include <linux/delay.h>
   11.33 +#include <linux/pci.h>
   11.34 +#include <linux/netdevice.h>
   11.35 +
   11.36 +#include "e1000_mac.h"
   11.37 +
   11.38 +#include "igb.h"
   11.39 +
   11.40 +static s32 igb_set_default_fc(struct e1000_hw *hw);
   11.41 +static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
   11.42 +
   11.43 +/**
   11.44 + *  igb_remove_device - Free device specific structure
   11.45 + *  @hw: pointer to the HW structure
   11.46 + *
   11.47 + *  If a device specific structure was allocated, this function will
   11.48 + *  free it.
   11.49 + **/
   11.50 +void igb_remove_device(struct e1000_hw *hw)
   11.51 +{
   11.52 +	/* Freeing the dev_spec member of e1000_hw structure */
   11.53 +	kfree(hw->dev_spec);
   11.54 +}
   11.55 +
   11.56 +static void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
   11.57 +{
   11.58 +	struct igb_adapter *adapter = hw->back;
   11.59 +
   11.60 +	pci_read_config_word(adapter->pdev, reg, value);
   11.61 +}
   11.62 +
   11.63 +static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
   11.64 +{
   11.65 +	struct igb_adapter *adapter = hw->back;
   11.66 +	u16 cap_offset;
   11.67 +
   11.68 +	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
   11.69 +	if (!cap_offset)
   11.70 +		return -E1000_ERR_CONFIG;
   11.71 +
   11.72 +	pci_read_config_word(adapter->pdev, cap_offset + reg, value);
   11.73 +
   11.74 +	return 0;
   11.75 +}
   11.76 +
   11.77 +/**
   11.78 + *  igb_get_bus_info_pcie - Get PCIe bus information
   11.79 + *  @hw: pointer to the HW structure
   11.80 + *
   11.81 + *  Determines and stores the system bus information for a particular
   11.82 + *  network interface.  The following bus information is determined and stored:
   11.83 + *  bus speed, bus width, type (PCIe), and PCIe function.
   11.84 + **/
   11.85 +s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
   11.86 +{
   11.87 +	struct e1000_bus_info *bus = &hw->bus;
   11.88 +	s32 ret_val;
   11.89 +	u32 status;
   11.90 +	u16 pcie_link_status, pci_header_type;
   11.91 +
   11.92 +	bus->type = e1000_bus_type_pci_express;
   11.93 +	bus->speed = e1000_bus_speed_2500;
   11.94 +
   11.95 +	ret_val = igb_read_pcie_cap_reg(hw,
   11.96 +					  PCIE_LINK_STATUS,
   11.97 +					  &pcie_link_status);
   11.98 +	if (ret_val)
   11.99 +		bus->width = e1000_bus_width_unknown;
  11.100 +	else
  11.101 +		bus->width = (enum e1000_bus_width)((pcie_link_status &
  11.102 +						     PCIE_LINK_WIDTH_MASK) >>
  11.103 +						     PCIE_LINK_WIDTH_SHIFT);
  11.104 +
  11.105 +	igb_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
  11.106 +	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
  11.107 +		status = rd32(E1000_STATUS);
  11.108 +		bus->func = (status & E1000_STATUS_FUNC_MASK)
  11.109 +			    >> E1000_STATUS_FUNC_SHIFT;
  11.110 +	} else {
  11.111 +		bus->func = 0;
  11.112 +	}
  11.113 +
  11.114 +	return 0;
  11.115 +}
  11.116 +
  11.117 +/**
  11.118 + *  igb_clear_vfta - Clear VLAN filter table
  11.119 + *  @hw: pointer to the HW structure
  11.120 + *
  11.121 + *  Clears the register array which contains the VLAN filter table by
  11.122 + *  setting all the values to 0.
  11.123 + **/
  11.124 +void igb_clear_vfta(struct e1000_hw *hw)
  11.125 +{
  11.126 +	u32 offset;
  11.127 +
  11.128 +	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
  11.129 +		array_wr32(E1000_VFTA, offset, 0);
  11.130 +		wrfl();
  11.131 +	}
  11.132 +}
  11.133 +
  11.134 +/**
  11.135 + *  igb_write_vfta - Write value to VLAN filter table
  11.136 + *  @hw: pointer to the HW structure
  11.137 + *  @offset: register offset in VLAN filter table
  11.138 + *  @value: register value written to VLAN filter table
  11.139 + *
  11.140 + *  Writes value at the given offset in the register array which stores
  11.141 + *  the VLAN filter table.
  11.142 + **/
  11.143 +void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
  11.144 +{
  11.145 +	array_wr32(E1000_VFTA, offset, value);
  11.146 +	wrfl();
  11.147 +}
  11.148 +
  11.149 +/**
  11.150 + *  igb_check_alt_mac_addr - Check for alternate MAC addr
  11.151 + *  @hw: pointer to the HW structure
  11.152 + *
  11.153 + *  Checks the nvm for an alternate MAC address.  An alternate MAC address
  11.154 + *  can be setup by pre-boot software and must be treated like a permanent
  11.155 + *  address and must override the actual permanent MAC address.  If an
  11.156 + *  alternate MAC address is fopund it is saved in the hw struct and
  11.157 + *  prgrammed into RAR0 and the cuntion returns success, otherwise the
  11.158 + *  fucntion returns an error.
  11.159 + **/
  11.160 +s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
  11.161 +{
  11.162 +	u32 i;
  11.163 +	s32 ret_val = 0;
  11.164 +	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
  11.165 +	u8 alt_mac_addr[ETH_ALEN];
  11.166 +
  11.167 +	ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
  11.168 +				 &nvm_alt_mac_addr_offset);
  11.169 +	if (ret_val) {
  11.170 +		hw_dbg("NVM Read Error\n");
  11.171 +		goto out;
  11.172 +	}
  11.173 +
  11.174 +	if (nvm_alt_mac_addr_offset == 0xFFFF) {
  11.175 +		ret_val = -(E1000_NOT_IMPLEMENTED);
  11.176 +		goto out;
  11.177 +	}
  11.178 +
  11.179 +	if (hw->bus.func == E1000_FUNC_1)
  11.180 +		nvm_alt_mac_addr_offset += ETH_ALEN/sizeof(u16);
  11.181 +
  11.182 +	for (i = 0; i < ETH_ALEN; i += 2) {
  11.183 +		offset = nvm_alt_mac_addr_offset + (i >> 1);
  11.184 +		ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
  11.185 +		if (ret_val) {
  11.186 +			hw_dbg("NVM Read Error\n");
  11.187 +			goto out;
  11.188 +		}
  11.189 +
  11.190 +		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
  11.191 +		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
  11.192 +	}
  11.193 +
  11.194 +	/* if multicast bit is set, the alternate address will not be used */
  11.195 +	if (alt_mac_addr[0] & 0x01) {
  11.196 +		ret_val = -(E1000_NOT_IMPLEMENTED);
  11.197 +		goto out;
  11.198 +	}
  11.199 +
  11.200 +	for (i = 0; i < ETH_ALEN; i++)
  11.201 +		hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
  11.202 +
  11.203 +	hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0);
  11.204 +
  11.205 +out:
  11.206 +	return ret_val;
  11.207 +}
  11.208 +
  11.209 +/**
  11.210 + *  igb_rar_set - Set receive address register
  11.211 + *  @hw: pointer to the HW structure
  11.212 + *  @addr: pointer to the receive address
  11.213 + *  @index: receive address array register
  11.214 + *
  11.215 + *  Sets the receive address array register at index to the address passed
  11.216 + *  in by addr.
  11.217 + **/
  11.218 +void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
  11.219 +{
  11.220 +	u32 rar_low, rar_high;
  11.221 +
  11.222 +	/*
  11.223 +	 * HW expects these in little endian so we reverse the byte order
  11.224 +	 * from network order (big endian) to little endian
  11.225 +	 */
  11.226 +	rar_low = ((u32) addr[0] |
  11.227 +		   ((u32) addr[1] << 8) |
  11.228 +		    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
  11.229 +
  11.230 +	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
  11.231 +
  11.232 +	if (!hw->mac.disable_av)
  11.233 +		rar_high |= E1000_RAH_AV;
  11.234 +
  11.235 +	array_wr32(E1000_RA, (index << 1), rar_low);
  11.236 +	array_wr32(E1000_RA, ((index << 1) + 1), rar_high);
  11.237 +}
  11.238 +
  11.239 +/**
  11.240 + *  igb_mta_set - Set multicast filter table address
  11.241 + *  @hw: pointer to the HW structure
  11.242 + *  @hash_value: determines the MTA register and bit to set
  11.243 + *
  11.244 + *  The multicast table address is a register array of 32-bit registers.
  11.245 + *  The hash_value is used to determine what register the bit is in, the
  11.246 + *  current value is read, the new bit is OR'd in and the new value is
  11.247 + *  written back into the register.
  11.248 + **/
  11.249 +void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
  11.250 +{
  11.251 +	u32 hash_bit, hash_reg, mta;
  11.252 +
  11.253 +	/*
  11.254 +	 * The MTA is a register array of 32-bit registers. It is
  11.255 +	 * treated like an array of (32*mta_reg_count) bits.  We want to
  11.256 +	 * set bit BitArray[hash_value]. So we figure out what register
  11.257 +	 * the bit is in, read it, OR in the new bit, then write
  11.258 +	 * back the new value.  The (hw->mac.mta_reg_count - 1) serves as a
  11.259 +	 * mask to bits 31:5 of the hash value which gives us the
  11.260 +	 * register we're modifying.  The hash bit within that register
  11.261 +	 * is determined by the lower 5 bits of the hash value.
  11.262 +	 */
  11.263 +	hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
  11.264 +	hash_bit = hash_value & 0x1F;
  11.265 +
  11.266 +	mta = array_rd32(E1000_MTA, hash_reg);
  11.267 +
  11.268 +	mta |= (1 << hash_bit);
  11.269 +
  11.270 +	array_wr32(E1000_MTA, hash_reg, mta);
  11.271 +	wrfl();
  11.272 +}
  11.273 +
  11.274 +/**
  11.275 + *  igb_hash_mc_addr - Generate a multicast hash value
  11.276 + *  @hw: pointer to the HW structure
  11.277 + *  @mc_addr: pointer to a multicast address
  11.278 + *
  11.279 + *  Generates a multicast address hash value which is used to determine
  11.280 + *  the multicast filter table array address and new table value.  See
  11.281 + *  igb_mta_set()
  11.282 + **/
  11.283 +u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
  11.284 +{
  11.285 +	u32 hash_value, hash_mask;
  11.286 +	u8 bit_shift = 0;
  11.287 +
  11.288 +	/* Register count multiplied by bits per register */
  11.289 +	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
  11.290 +
  11.291 +	/*
  11.292 +	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
  11.293 +	 * where 0xFF would still fall within the hash mask.
  11.294 +	 */
  11.295 +	while (hash_mask >> bit_shift != 0xFF)
  11.296 +		bit_shift++;
  11.297 +
  11.298 +	/*
  11.299 +	 * The portion of the address that is used for the hash table
  11.300 +	 * is determined by the mc_filter_type setting.
  11.301 +	 * The algorithm is such that there is a total of 8 bits of shifting.
  11.302 +	 * The bit_shift for a mc_filter_type of 0 represents the number of
  11.303 +	 * left-shifts where the MSB of mc_addr[5] would still fall within
  11.304 +	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
  11.305 +	 * of 8 bits of shifting, then mc_addr[4] will shift right the
  11.306 +	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
  11.307 +	 * cases are a variation of this algorithm...essentially raising the
  11.308 +	 * number of bits to shift mc_addr[5] left, while still keeping the
  11.309 +	 * 8-bit shifting total.
  11.310 +	 *
  11.311 +	 * For example, given the following Destination MAC Address and an
  11.312 +	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
  11.313 +	 * we can see that the bit_shift for case 0 is 4.  These are the hash
  11.314 +	 * values resulting from each mc_filter_type...
  11.315 +	 * [0] [1] [2] [3] [4] [5]
  11.316 +	 * 01  AA  00  12  34  56
  11.317 +	 * LSB                 MSB
  11.318 +	 *
  11.319 +	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
  11.320 +	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
  11.321 +	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
  11.322 +	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
  11.323 +	 */
  11.324 +	switch (hw->mac.mc_filter_type) {
  11.325 +	default:
  11.326 +	case 0:
  11.327 +		break;
  11.328 +	case 1:
  11.329 +		bit_shift += 1;
  11.330 +		break;
  11.331 +	case 2:
  11.332 +		bit_shift += 2;
  11.333 +		break;
  11.334 +	case 3:
  11.335 +		bit_shift += 4;
  11.336 +		break;
  11.337 +	}
  11.338 +
  11.339 +	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
  11.340 +				  (((u16) mc_addr[5]) << bit_shift)));
  11.341 +
  11.342 +	return hash_value;
  11.343 +}
  11.344 +
  11.345 +/**
  11.346 + *  igb_clear_hw_cntrs_base - Clear base hardware counters
  11.347 + *  @hw: pointer to the HW structure
  11.348 + *
  11.349 + *  Clears the base hardware counters by reading the counter registers.
  11.350 + **/
  11.351 +void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
  11.352 +{
  11.353 +	u32 temp;
  11.354 +
  11.355 +	temp = rd32(E1000_CRCERRS);
  11.356 +	temp = rd32(E1000_SYMERRS);
  11.357 +	temp = rd32(E1000_MPC);
  11.358 +	temp = rd32(E1000_SCC);
  11.359 +	temp = rd32(E1000_ECOL);
  11.360 +	temp = rd32(E1000_MCC);
  11.361 +	temp = rd32(E1000_LATECOL);
  11.362 +	temp = rd32(E1000_COLC);
  11.363 +	temp = rd32(E1000_DC);
  11.364 +	temp = rd32(E1000_SEC);
  11.365 +	temp = rd32(E1000_RLEC);
  11.366 +	temp = rd32(E1000_XONRXC);
  11.367 +	temp = rd32(E1000_XONTXC);
  11.368 +	temp = rd32(E1000_XOFFRXC);
  11.369 +	temp = rd32(E1000_XOFFTXC);
  11.370 +	temp = rd32(E1000_FCRUC);
  11.371 +	temp = rd32(E1000_GPRC);
  11.372 +	temp = rd32(E1000_BPRC);
  11.373 +	temp = rd32(E1000_MPRC);
  11.374 +	temp = rd32(E1000_GPTC);
  11.375 +	temp = rd32(E1000_GORCL);
  11.376 +	temp = rd32(E1000_GORCH);
  11.377 +	temp = rd32(E1000_GOTCL);
  11.378 +	temp = rd32(E1000_GOTCH);
  11.379 +	temp = rd32(E1000_RNBC);
  11.380 +	temp = rd32(E1000_RUC);
  11.381 +	temp = rd32(E1000_RFC);
  11.382 +	temp = rd32(E1000_ROC);
  11.383 +	temp = rd32(E1000_RJC);
  11.384 +	temp = rd32(E1000_TORL);
  11.385 +	temp = rd32(E1000_TORH);
  11.386 +	temp = rd32(E1000_TOTL);
  11.387 +	temp = rd32(E1000_TOTH);
  11.388 +	temp = rd32(E1000_TPR);
  11.389 +	temp = rd32(E1000_TPT);
  11.390 +	temp = rd32(E1000_MPTC);
  11.391 +	temp = rd32(E1000_BPTC);
  11.392 +}
  11.393 +
  11.394 +/**
  11.395 + *  igb_check_for_copper_link - Check for link (Copper)
  11.396 + *  @hw: pointer to the HW structure
  11.397 + *
  11.398 + *  Checks to see of the link status of the hardware has changed.  If a
  11.399 + *  change in link status has been detected, then we read the PHY registers
  11.400 + *  to get the current speed/duplex if link exists.
  11.401 + **/
  11.402 +s32 igb_check_for_copper_link(struct e1000_hw *hw)
  11.403 +{
  11.404 +	struct e1000_mac_info *mac = &hw->mac;
  11.405 +	s32 ret_val;
  11.406 +	bool link;
  11.407 +
  11.408 +	/*
  11.409 +	 * We only want to go out to the PHY registers to see if Auto-Neg
  11.410 +	 * has completed and/or if our link status has changed.  The
  11.411 +	 * get_link_status flag is set upon receiving a Link Status
  11.412 +	 * Change or Rx Sequence Error interrupt.
  11.413 +	 */
  11.414 +	if (!mac->get_link_status) {
  11.415 +		ret_val = 0;
  11.416 +		goto out;
  11.417 +	}
  11.418 +
  11.419 +	/*
  11.420 +	 * First we want to see if the MII Status Register reports
  11.421 +	 * link.  If so, then we want to get the current speed/duplex
  11.422 +	 * of the PHY.
  11.423 +	 */
  11.424 +	ret_val = igb_phy_has_link(hw, 1, 0, &link);
  11.425 +	if (ret_val)
  11.426 +		goto out;
  11.427 +
  11.428 +	if (!link)
  11.429 +		goto out; /* No link detected */
  11.430 +
  11.431 +	mac->get_link_status = false;
  11.432 +
  11.433 +	/*
  11.434 +	 * Check if there was DownShift, must be checked
  11.435 +	 * immediately after link-up
  11.436 +	 */
  11.437 +	igb_check_downshift(hw);
  11.438 +
  11.439 +	/*
  11.440 +	 * If we are forcing speed/duplex, then we simply return since
  11.441 +	 * we have already determined whether we have link or not.
  11.442 +	 */
  11.443 +	if (!mac->autoneg) {
  11.444 +		ret_val = -E1000_ERR_CONFIG;
  11.445 +		goto out;
  11.446 +	}
  11.447 +
  11.448 +	/*
  11.449 +	 * Auto-Neg is enabled.  Auto Speed Detection takes care
  11.450 +	 * of MAC speed/duplex configuration.  So we only need to
  11.451 +	 * configure Collision Distance in the MAC.
  11.452 +	 */
  11.453 +	igb_config_collision_dist(hw);
  11.454 +
  11.455 +	/*
  11.456 +	 * Configure Flow Control now that Auto-Neg has completed.
  11.457 +	 * First, we need to restore the desired flow control
  11.458 +	 * settings because we may have had to re-autoneg with a
  11.459 +	 * different link partner.
  11.460 +	 */
  11.461 +	ret_val = igb_config_fc_after_link_up(hw);
  11.462 +	if (ret_val)
  11.463 +		hw_dbg("Error configuring flow control\n");
  11.464 +
  11.465 +out:
  11.466 +	return ret_val;
  11.467 +}
  11.468 +
  11.469 +/**
  11.470 + *  igb_setup_link - Setup flow control and link settings
  11.471 + *  @hw: pointer to the HW structure
  11.472 + *
  11.473 + *  Determines which flow control settings to use, then configures flow
  11.474 + *  control.  Calls the appropriate media-specific link configuration
  11.475 + *  function.  Assuming the adapter has a valid link partner, a valid link
  11.476 + *  should be established.  Assumes the hardware has previously been reset
  11.477 + *  and the transmitter and receiver are not enabled.
  11.478 + **/
  11.479 +s32 igb_setup_link(struct e1000_hw *hw)
  11.480 +{
  11.481 +	s32 ret_val = 0;
  11.482 +
  11.483 +	/*
  11.484 +	 * In the case of the phy reset being blocked, we already have a link.
  11.485 +	 * We do not need to set it up again.
  11.486 +	 */
  11.487 +	if (igb_check_reset_block(hw))
  11.488 +		goto out;
  11.489 +
  11.490 +	ret_val = igb_set_default_fc(hw);
  11.491 +	if (ret_val)
  11.492 +		goto out;
  11.493 +
  11.494 +	/*
  11.495 +	 * We want to save off the original Flow Control configuration just
  11.496 +	 * in case we get disconnected and then reconnected into a different
  11.497 +	 * hub or switch with different Flow Control capabilities.
  11.498 +	 */
  11.499 +	hw->fc.original_type = hw->fc.type;
  11.500 +
  11.501 +	hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type);
  11.502 +
  11.503 +	/* Call the necessary media_type subroutine to configure the link. */
  11.504 +	ret_val = hw->mac.ops.setup_physical_interface(hw);
  11.505 +	if (ret_val)
  11.506 +		goto out;
  11.507 +
  11.508 +	/*
  11.509 +	 * Initialize the flow control address, type, and PAUSE timer
  11.510 +	 * registers to their default values.  This is done even if flow
  11.511 +	 * control is disabled, because it does not hurt anything to
  11.512 +	 * initialize these registers.
  11.513 +	 */
  11.514 +	hw_dbg("Initializing the Flow Control address, type and timer regs\n");
  11.515 +	wr32(E1000_FCT, FLOW_CONTROL_TYPE);
  11.516 +	wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  11.517 +	wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
  11.518 +
  11.519 +	wr32(E1000_FCTTV, hw->fc.pause_time);
  11.520 +
  11.521 +	ret_val = igb_set_fc_watermarks(hw);
  11.522 +
  11.523 +out:
  11.524 +	return ret_val;
  11.525 +}
  11.526 +
  11.527 +/**
  11.528 + *  igb_config_collision_dist - Configure collision distance
  11.529 + *  @hw: pointer to the HW structure
  11.530 + *
  11.531 + *  Configures the collision distance to the default value and is used
  11.532 + *  during link setup. Currently no func pointer exists and all
  11.533 + *  implementations are handled in the generic version of this function.
  11.534 + **/
  11.535 +void igb_config_collision_dist(struct e1000_hw *hw)
  11.536 +{
  11.537 +	u32 tctl;
  11.538 +
  11.539 +	tctl = rd32(E1000_TCTL);
  11.540 +
  11.541 +	tctl &= ~E1000_TCTL_COLD;
  11.542 +	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
  11.543 +
  11.544 +	wr32(E1000_TCTL, tctl);
  11.545 +	wrfl();
  11.546 +}
  11.547 +
  11.548 +/**
  11.549 + *  igb_set_fc_watermarks - Set flow control high/low watermarks
  11.550 + *  @hw: pointer to the HW structure
  11.551 + *
  11.552 + *  Sets the flow control high/low threshold (watermark) registers.  If
  11.553 + *  flow control XON frame transmission is enabled, then set XON frame
  11.554 + *  tansmission as well.
  11.555 + **/
  11.556 +static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
  11.557 +{
  11.558 +	s32 ret_val = 0;
  11.559 +	u32 fcrtl = 0, fcrth = 0;
  11.560 +
  11.561 +	/*
  11.562 +	 * Set the flow control receive threshold registers.  Normally,
  11.563 +	 * these registers will be set to a default threshold that may be
  11.564 +	 * adjusted later by the driver's runtime code.  However, if the
  11.565 +	 * ability to transmit pause frames is not enabled, then these
  11.566 +	 * registers will be set to 0.
  11.567 +	 */
  11.568 +	if (hw->fc.type & e1000_fc_tx_pause) {
  11.569 +		/*
  11.570 +		 * We need to set up the Receive Threshold high and low water
  11.571 +		 * marks as well as (optionally) enabling the transmission of
  11.572 +		 * XON frames.
  11.573 +		 */
  11.574 +		fcrtl = hw->fc.low_water;
  11.575 +		if (hw->fc.send_xon)
  11.576 +			fcrtl |= E1000_FCRTL_XONE;
  11.577 +
  11.578 +		fcrth = hw->fc.high_water;
  11.579 +	}
  11.580 +	wr32(E1000_FCRTL, fcrtl);
  11.581 +	wr32(E1000_FCRTH, fcrth);
  11.582 +
  11.583 +	return ret_val;
  11.584 +}
  11.585 +
  11.586 +/**
  11.587 + *  igb_set_default_fc - Set flow control default values
  11.588 + *  @hw: pointer to the HW structure
  11.589 + *
  11.590 + *  Read the EEPROM for the default values for flow control and store the
  11.591 + *  values.
  11.592 + **/
  11.593 +static s32 igb_set_default_fc(struct e1000_hw *hw)
  11.594 +{
  11.595 +	s32 ret_val = 0;
  11.596 +	u16 nvm_data;
  11.597 +
  11.598 +	/*
  11.599 +	 * Read and store word 0x0F of the EEPROM. This word contains bits
  11.600 +	 * that determine the hardware's default PAUSE (flow control) mode,
  11.601 +	 * a bit that determines whether the HW defaults to enabling or
  11.602 +	 * disabling auto-negotiation, and the direction of the
  11.603 +	 * SW defined pins. If there is no SW over-ride of the flow
  11.604 +	 * control setting, then the variable hw->fc will
  11.605 +	 * be initialized based on a value in the EEPROM.
  11.606 +	 */
  11.607 +	ret_val = hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL2_REG, 1,
  11.608 +				       &nvm_data);
  11.609 +
  11.610 +	if (ret_val) {
  11.611 +		hw_dbg("NVM Read Error\n");
  11.612 +		goto out;
  11.613 +	}
  11.614 +
  11.615 +	if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
  11.616 +		hw->fc.type = e1000_fc_none;
  11.617 +	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
  11.618 +		 NVM_WORD0F_ASM_DIR)
  11.619 +		hw->fc.type = e1000_fc_tx_pause;
  11.620 +	else
  11.621 +		hw->fc.type = e1000_fc_full;
  11.622 +
  11.623 +out:
  11.624 +	return ret_val;
  11.625 +}
  11.626 +
  11.627 +/**
  11.628 + *  igb_force_mac_fc - Force the MAC's flow control settings
  11.629 + *  @hw: pointer to the HW structure
  11.630 + *
  11.631 + *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
  11.632 + *  device control register to reflect the adapter settings.  TFCE and RFCE
  11.633 + *  need to be explicitly set by software when a copper PHY is used because
  11.634 + *  autonegotiation is managed by the PHY rather than the MAC.  Software must
  11.635 + *  also configure these bits when link is forced on a fiber connection.
  11.636 + **/
  11.637 +s32 igb_force_mac_fc(struct e1000_hw *hw)
  11.638 +{
  11.639 +	u32 ctrl;
  11.640 +	s32 ret_val = 0;
  11.641 +
  11.642 +	ctrl = rd32(E1000_CTRL);
  11.643 +
  11.644 +	/*
  11.645 +	 * Because we didn't get link via the internal auto-negotiation
  11.646 +	 * mechanism (we either forced link or we got link via PHY
  11.647 +	 * auto-neg), we have to manually enable/disable transmit an
  11.648 +	 * receive flow control.
  11.649 +	 *
  11.650 +	 * The "Case" statement below enables/disable flow control
  11.651 +	 * according to the "hw->fc.type" parameter.
  11.652 +	 *
  11.653 +	 * The possible values of the "fc" parameter are:
  11.654 +	 *      0:  Flow control is completely disabled
  11.655 +	 *      1:  Rx flow control is enabled (we can receive pause
  11.656 +	 *          frames but not send pause frames).
  11.657 +	 *      2:  Tx flow control is enabled (we can send pause frames
  11.658 +	 *          frames but we do not receive pause frames).
  11.659 +	 *      3:  Both Rx and TX flow control (symmetric) is enabled.
  11.660 +	 *  other:  No other values should be possible at this point.
  11.661 +	 */
  11.662 +	hw_dbg("hw->fc.type = %u\n", hw->fc.type);
  11.663 +
  11.664 +	switch (hw->fc.type) {
  11.665 +	case e1000_fc_none:
  11.666 +		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  11.667 +		break;
  11.668 +	case e1000_fc_rx_pause:
  11.669 +		ctrl &= (~E1000_CTRL_TFCE);
  11.670 +		ctrl |= E1000_CTRL_RFCE;
  11.671 +		break;
  11.672 +	case e1000_fc_tx_pause:
  11.673 +		ctrl &= (~E1000_CTRL_RFCE);
  11.674 +		ctrl |= E1000_CTRL_TFCE;
  11.675 +		break;
  11.676 +	case e1000_fc_full:
  11.677 +		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  11.678 +		break;
  11.679 +	default:
  11.680 +		hw_dbg("Flow control param set incorrectly\n");
  11.681 +		ret_val = -E1000_ERR_CONFIG;
  11.682 +		goto out;
  11.683 +	}
  11.684 +
  11.685 +	wr32(E1000_CTRL, ctrl);
  11.686 +
  11.687 +out:
  11.688 +	return ret_val;
  11.689 +}
  11.690 +
  11.691 +/**
  11.692 + *  igb_config_fc_after_link_up - Configures flow control after link
  11.693 + *  @hw: pointer to the HW structure
  11.694 + *
  11.695 + *  Checks the status of auto-negotiation after link up to ensure that the
  11.696 + *  speed and duplex were not forced.  If the link needed to be forced, then
  11.697 + *  flow control needs to be forced also.  If auto-negotiation is enabled
  11.698 + *  and did not fail, then we configure flow control based on our link
  11.699 + *  partner.
  11.700 + **/
  11.701 +s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
  11.702 +{
  11.703 +	struct e1000_mac_info *mac = &hw->mac;
  11.704 +	s32 ret_val = 0;
  11.705 +	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
  11.706 +	u16 speed, duplex;
  11.707 +
  11.708 +	/*
  11.709 +	 * Check for the case where we have fiber media and auto-neg failed
  11.710 +	 * so we had to force link.  In this case, we need to force the
  11.711 +	 * configuration of the MAC to match the "fc" parameter.
  11.712 +	 */
  11.713 +	if (mac->autoneg_failed) {
  11.714 +		if (hw->phy.media_type == e1000_media_type_fiber ||
  11.715 +		    hw->phy.media_type == e1000_media_type_internal_serdes)
  11.716 +			ret_val = igb_force_mac_fc(hw);
  11.717 +	} else {
  11.718 +		if (hw->phy.media_type == e1000_media_type_copper)
  11.719 +			ret_val = igb_force_mac_fc(hw);
  11.720 +	}
  11.721 +
  11.722 +	if (ret_val) {
  11.723 +		hw_dbg("Error forcing flow control settings\n");
  11.724 +		goto out;
  11.725 +	}
  11.726 +
  11.727 +	/*
  11.728 +	 * Check for the case where we have copper media and auto-neg is
  11.729 +	 * enabled.  In this case, we need to check and see if Auto-Neg
  11.730 +	 * has completed, and if so, how the PHY and link partner has
  11.731 +	 * flow control configured.
  11.732 +	 */
  11.733 +	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
  11.734 +		/*
  11.735 +		 * Read the MII Status Register and check to see if AutoNeg
  11.736 +		 * has completed.  We read this twice because this reg has
  11.737 +		 * some "sticky" (latched) bits.
  11.738 +		 */
  11.739 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS,
  11.740 +						   &mii_status_reg);
  11.741 +		if (ret_val)
  11.742 +			goto out;
  11.743 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS,
  11.744 +						   &mii_status_reg);
  11.745 +		if (ret_val)
  11.746 +			goto out;
  11.747 +
  11.748 +		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
  11.749 +			hw_dbg("Copper PHY and Auto Neg "
  11.750 +				 "has not completed.\n");
  11.751 +			goto out;
  11.752 +		}
  11.753 +
  11.754 +		/*
  11.755 +		 * The AutoNeg process has completed, so we now need to
  11.756 +		 * read both the Auto Negotiation Advertisement
  11.757 +		 * Register (Address 4) and the Auto_Negotiation Base
  11.758 +		 * Page Ability Register (Address 5) to determine how
  11.759 +		 * flow control was negotiated.
  11.760 +		 */
  11.761 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV,
  11.762 +					    &mii_nway_adv_reg);
  11.763 +		if (ret_val)
  11.764 +			goto out;
  11.765 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_LP_ABILITY,
  11.766 +					    &mii_nway_lp_ability_reg);
  11.767 +		if (ret_val)
  11.768 +			goto out;
  11.769 +
  11.770 +		/*
  11.771 +		 * Two bits in the Auto Negotiation Advertisement Register
  11.772 +		 * (Address 4) and two bits in the Auto Negotiation Base
  11.773 +		 * Page Ability Register (Address 5) determine flow control
  11.774 +		 * for both the PHY and the link partner.  The following
  11.775 +		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  11.776 +		 * 1999, describes these PAUSE resolution bits and how flow
  11.777 +		 * control is determined based upon these settings.
  11.778 +		 * NOTE:  DC = Don't Care
  11.779 +		 *
  11.780 +		 *   LOCAL DEVICE  |   LINK PARTNER
  11.781 +		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  11.782 +		 *-------|---------|-------|---------|--------------------
  11.783 +		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
  11.784 +		 *   0   |    1    |   0   |   DC    | e1000_fc_none
  11.785 +		 *   0   |    1    |   1   |    0    | e1000_fc_none
  11.786 +		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
  11.787 +		 *   1   |    0    |   0   |   DC    | e1000_fc_none
  11.788 +		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
  11.789 +		 *   1   |    1    |   0   |    0    | e1000_fc_none
  11.790 +		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
  11.791 +		 *
  11.792 +		 * Are both PAUSE bits set to 1?  If so, this implies
  11.793 +		 * Symmetric Flow Control is enabled at both ends.  The
  11.794 +		 * ASM_DIR bits are irrelevant per the spec.
  11.795 +		 *
  11.796 +		 * For Symmetric Flow Control:
  11.797 +		 *
  11.798 +		 *   LOCAL DEVICE  |   LINK PARTNER
  11.799 +		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  11.800 +		 *-------|---------|-------|---------|--------------------
  11.801 +		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
  11.802 +		 *
  11.803 +		 */
  11.804 +		if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  11.805 +		    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  11.806 +			/*
  11.807 +			 * Now we need to check if the user selected RX ONLY
  11.808 +			 * of pause frames.  In this case, we had to advertise
  11.809 +			 * FULL flow control because we could not advertise RX
  11.810 +			 * ONLY. Hence, we must now check to see if we need to
  11.811 +			 * turn OFF  the TRANSMISSION of PAUSE frames.
  11.812 +			 */
  11.813 +			if (hw->fc.original_type == e1000_fc_full) {
  11.814 +				hw->fc.type = e1000_fc_full;
  11.815 +				hw_dbg("Flow Control = FULL.\r\n");
  11.816 +			} else {
  11.817 +				hw->fc.type = e1000_fc_rx_pause;
  11.818 +				hw_dbg("Flow Control = "
  11.819 +				       "RX PAUSE frames only.\r\n");
  11.820 +			}
  11.821 +		}
  11.822 +		/*
  11.823 +		 * For receiving PAUSE frames ONLY.
  11.824 +		 *
  11.825 +		 *   LOCAL DEVICE  |   LINK PARTNER
  11.826 +		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  11.827 +		 *-------|---------|-------|---------|--------------------
  11.828 +		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
  11.829 +		 */
  11.830 +		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  11.831 +			  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  11.832 +			  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  11.833 +			  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
  11.834 +			hw->fc.type = e1000_fc_tx_pause;
  11.835 +			hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
  11.836 +		}
  11.837 +		/*
  11.838 +		 * For transmitting PAUSE frames ONLY.
  11.839 +		 *
  11.840 +		 *   LOCAL DEVICE  |   LINK PARTNER
  11.841 +		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  11.842 +		 *-------|---------|-------|---------|--------------------
  11.843 +		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
  11.844 +		 */
  11.845 +		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  11.846 +			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  11.847 +			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  11.848 +			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
  11.849 +			hw->fc.type = e1000_fc_rx_pause;
  11.850 +			hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
  11.851 +		}
  11.852 +		/*
  11.853 +		 * Per the IEEE spec, at this point flow control should be
  11.854 +		 * disabled.  However, we want to consider that we could
  11.855 +		 * be connected to a legacy switch that doesn't advertise
  11.856 +		 * desired flow control, but can be forced on the link
  11.857 +		 * partner.  So if we advertised no flow control, that is
  11.858 +		 * what we will resolve to.  If we advertised some kind of
  11.859 +		 * receive capability (Rx Pause Only or Full Flow Control)
  11.860 +		 * and the link partner advertised none, we will configure
  11.861 +		 * ourselves to enable Rx Flow Control only.  We can do
  11.862 +		 * this safely for two reasons:  If the link partner really
  11.863 +		 * didn't want flow control enabled, and we enable Rx, no
  11.864 +		 * harm done since we won't be receiving any PAUSE frames
  11.865 +		 * anyway.  If the intent on the link partner was to have
  11.866 +		 * flow control enabled, then by us enabling RX only, we
  11.867 +		 * can at least receive pause frames and process them.
  11.868 +		 * This is a good idea because in most cases, since we are
  11.869 +		 * predominantly a server NIC, more times than not we will
  11.870 +		 * be asked to delay transmission of packets than asking
  11.871 +		 * our link partner to pause transmission of frames.
  11.872 +		 */
  11.873 +		else if ((hw->fc.original_type == e1000_fc_none ||
  11.874 +			  hw->fc.original_type == e1000_fc_tx_pause) ||
  11.875 +			 hw->fc.strict_ieee) {
  11.876 +			hw->fc.type = e1000_fc_none;
  11.877 +			hw_dbg("Flow Control = NONE.\r\n");
  11.878 +		} else {
  11.879 +			hw->fc.type = e1000_fc_rx_pause;
  11.880 +			hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
  11.881 +		}
  11.882 +
  11.883 +		/*
  11.884 +		 * Now we need to do one last check...  If we auto-
  11.885 +		 * negotiated to HALF DUPLEX, flow control should not be
  11.886 +		 * enabled per IEEE 802.3 spec.
  11.887 +		 */
  11.888 +		ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
  11.889 +		if (ret_val) {
  11.890 +			hw_dbg("Error getting link speed and duplex\n");
  11.891 +			goto out;
  11.892 +		}
  11.893 +
  11.894 +		if (duplex == HALF_DUPLEX)
  11.895 +			hw->fc.type = e1000_fc_none;
  11.896 +
  11.897 +		/*
  11.898 +		 * Now we call a subroutine to actually force the MAC
  11.899 +		 * controller to use the correct flow control settings.
  11.900 +		 */
  11.901 +		ret_val = igb_force_mac_fc(hw);
  11.902 +		if (ret_val) {
  11.903 +			hw_dbg("Error forcing flow control settings\n");
  11.904 +			goto out;
  11.905 +		}
  11.906 +	}
  11.907 +
  11.908 +out:
  11.909 +	return ret_val;
  11.910 +}
  11.911 +
  11.912 +/**
  11.913 + *  igb_get_speed_and_duplex_copper - Retreive current speed/duplex
  11.914 + *  @hw: pointer to the HW structure
  11.915 + *  @speed: stores the current speed
  11.916 + *  @duplex: stores the current duplex
  11.917 + *
  11.918 + *  Read the status register for the current speed/duplex and store the current
  11.919 + *  speed and duplex for copper connections.
  11.920 + **/
  11.921 +s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
  11.922 +				      u16 *duplex)
  11.923 +{
  11.924 +	u32 status;
  11.925 +
  11.926 +	status = rd32(E1000_STATUS);
  11.927 +	if (status & E1000_STATUS_SPEED_1000) {
  11.928 +		*speed = SPEED_1000;
  11.929 +		hw_dbg("1000 Mbs, ");
  11.930 +	} else if (status & E1000_STATUS_SPEED_100) {
  11.931 +		*speed = SPEED_100;
  11.932 +		hw_dbg("100 Mbs, ");
  11.933 +	} else {
  11.934 +		*speed = SPEED_10;
  11.935 +		hw_dbg("10 Mbs, ");
  11.936 +	}
  11.937 +
  11.938 +	if (status & E1000_STATUS_FD) {
  11.939 +		*duplex = FULL_DUPLEX;
  11.940 +		hw_dbg("Full Duplex\n");
  11.941 +	} else {
  11.942 +		*duplex = HALF_DUPLEX;
  11.943 +		hw_dbg("Half Duplex\n");
  11.944 +	}
  11.945 +
  11.946 +	return 0;
  11.947 +}
  11.948 +
  11.949 +/**
  11.950 + *  igb_get_hw_semaphore - Acquire hardware semaphore
  11.951 + *  @hw: pointer to the HW structure
  11.952 + *
  11.953 + *  Acquire the HW semaphore to access the PHY or NVM
  11.954 + **/
  11.955 +s32 igb_get_hw_semaphore(struct e1000_hw *hw)
  11.956 +{
  11.957 +	u32 swsm;
  11.958 +	s32 ret_val = 0;
  11.959 +	s32 timeout = hw->nvm.word_size + 1;
  11.960 +	s32 i = 0;
  11.961 +
  11.962 +	/* Get the SW semaphore */
  11.963 +	while (i < timeout) {
  11.964 +		swsm = rd32(E1000_SWSM);
  11.965 +		if (!(swsm & E1000_SWSM_SMBI))
  11.966 +			break;
  11.967 +
  11.968 +		udelay(50);
  11.969 +		i++;
  11.970 +	}
  11.971 +
  11.972 +	if (i == timeout) {
  11.973 +		hw_dbg("Driver can't access device - SMBI bit is set.\n");
  11.974 +		ret_val = -E1000_ERR_NVM;
  11.975 +		goto out;
  11.976 +	}
  11.977 +
  11.978 +	/* Get the FW semaphore. */
  11.979 +	for (i = 0; i < timeout; i++) {
  11.980 +		swsm = rd32(E1000_SWSM);
  11.981 +		wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
  11.982 +
  11.983 +		/* Semaphore acquired if bit latched */
  11.984 +		if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
  11.985 +			break;
  11.986 +
  11.987 +		udelay(50);
  11.988 +	}
  11.989 +
  11.990 +	if (i == timeout) {
  11.991 +		/* Release semaphores */
  11.992 +		igb_put_hw_semaphore(hw);
  11.993 +		hw_dbg("Driver can't access the NVM\n");
  11.994 +		ret_val = -E1000_ERR_NVM;
  11.995 +		goto out;
  11.996 +	}
  11.997 +
  11.998 +out:
  11.999 +	return ret_val;
 11.1000 +}
 11.1001 +
 11.1002 +/**
 11.1003 + *  igb_put_hw_semaphore - Release hardware semaphore
 11.1004 + *  @hw: pointer to the HW structure
 11.1005 + *
 11.1006 + *  Release hardware semaphore used to access the PHY or NVM
 11.1007 + **/
 11.1008 +void igb_put_hw_semaphore(struct e1000_hw *hw)
 11.1009 +{
 11.1010 +	u32 swsm;
 11.1011 +
 11.1012 +	swsm = rd32(E1000_SWSM);
 11.1013 +
 11.1014 +	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 11.1015 +
 11.1016 +	wr32(E1000_SWSM, swsm);
 11.1017 +}
 11.1018 +
 11.1019 +/**
 11.1020 + *  igb_get_auto_rd_done - Check for auto read completion
 11.1021 + *  @hw: pointer to the HW structure
 11.1022 + *
 11.1023 + *  Check EEPROM for Auto Read done bit.
 11.1024 + **/
 11.1025 +s32 igb_get_auto_rd_done(struct e1000_hw *hw)
 11.1026 +{
 11.1027 +	s32 i = 0;
 11.1028 +	s32 ret_val = 0;
 11.1029 +
 11.1030 +
 11.1031 +	while (i < AUTO_READ_DONE_TIMEOUT) {
 11.1032 +		if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
 11.1033 +			break;
 11.1034 +		msleep(1);
 11.1035 +		i++;
 11.1036 +	}
 11.1037 +
 11.1038 +	if (i == AUTO_READ_DONE_TIMEOUT) {
 11.1039 +		hw_dbg("Auto read by HW from NVM has not completed.\n");
 11.1040 +		ret_val = -E1000_ERR_RESET;
 11.1041 +		goto out;
 11.1042 +	}
 11.1043 +
 11.1044 +out:
 11.1045 +	return ret_val;
 11.1046 +}
 11.1047 +
 11.1048 +/**
 11.1049 + *  igb_valid_led_default - Verify a valid default LED config
 11.1050 + *  @hw: pointer to the HW structure
 11.1051 + *  @data: pointer to the NVM (EEPROM)
 11.1052 + *
 11.1053 + *  Read the EEPROM for the current default LED configuration.  If the
 11.1054 + *  LED configuration is not valid, set to a valid LED configuration.
 11.1055 + **/
 11.1056 +static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
 11.1057 +{
 11.1058 +	s32 ret_val;
 11.1059 +
 11.1060 +	ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
 11.1061 +	if (ret_val) {
 11.1062 +		hw_dbg("NVM Read Error\n");
 11.1063 +		goto out;
 11.1064 +	}
 11.1065 +
 11.1066 +	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
 11.1067 +		*data = ID_LED_DEFAULT;
 11.1068 +
 11.1069 +out:
 11.1070 +	return ret_val;
 11.1071 +}
 11.1072 +
 11.1073 +/**
 11.1074 + *  igb_id_led_init -
 11.1075 + *  @hw: pointer to the HW structure
 11.1076 + *
 11.1077 + **/
 11.1078 +s32 igb_id_led_init(struct e1000_hw *hw)
 11.1079 +{
 11.1080 +	struct e1000_mac_info *mac = &hw->mac;
 11.1081 +	s32 ret_val;
 11.1082 +	const u32 ledctl_mask = 0x000000FF;
 11.1083 +	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
 11.1084 +	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
 11.1085 +	u16 data, i, temp;
 11.1086 +	const u16 led_mask = 0x0F;
 11.1087 +
 11.1088 +	ret_val = igb_valid_led_default(hw, &data);
 11.1089 +	if (ret_val)
 11.1090 +		goto out;
 11.1091 +
 11.1092 +	mac->ledctl_default = rd32(E1000_LEDCTL);
 11.1093 +	mac->ledctl_mode1 = mac->ledctl_default;
 11.1094 +	mac->ledctl_mode2 = mac->ledctl_default;
 11.1095 +
 11.1096 +	for (i = 0; i < 4; i++) {
 11.1097 +		temp = (data >> (i << 2)) & led_mask;
 11.1098 +		switch (temp) {
 11.1099 +		case ID_LED_ON1_DEF2:
 11.1100 +		case ID_LED_ON1_ON2:
 11.1101 +		case ID_LED_ON1_OFF2:
 11.1102 +			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
 11.1103 +			mac->ledctl_mode1 |= ledctl_on << (i << 3);
 11.1104 +			break;
 11.1105 +		case ID_LED_OFF1_DEF2:
 11.1106 +		case ID_LED_OFF1_ON2:
 11.1107 +		case ID_LED_OFF1_OFF2:
 11.1108 +			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
 11.1109 +			mac->ledctl_mode1 |= ledctl_off << (i << 3);
 11.1110 +			break;
 11.1111 +		default:
 11.1112 +			/* Do nothing */
 11.1113 +			break;
 11.1114 +		}
 11.1115 +		switch (temp) {
 11.1116 +		case ID_LED_DEF1_ON2:
 11.1117 +		case ID_LED_ON1_ON2:
 11.1118 +		case ID_LED_OFF1_ON2:
 11.1119 +			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
 11.1120 +			mac->ledctl_mode2 |= ledctl_on << (i << 3);
 11.1121 +			break;
 11.1122 +		case ID_LED_DEF1_OFF2:
 11.1123 +		case ID_LED_ON1_OFF2:
 11.1124 +		case ID_LED_OFF1_OFF2:
 11.1125 +			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
 11.1126 +			mac->ledctl_mode2 |= ledctl_off << (i << 3);
 11.1127 +			break;
 11.1128 +		default:
 11.1129 +			/* Do nothing */
 11.1130 +			break;
 11.1131 +		}
 11.1132 +	}
 11.1133 +
 11.1134 +out:
 11.1135 +	return ret_val;
 11.1136 +}
 11.1137 +
 11.1138 +/**
 11.1139 + *  igb_cleanup_led - Set LED config to default operation
 11.1140 + *  @hw: pointer to the HW structure
 11.1141 + *
 11.1142 + *  Remove the current LED configuration and set the LED configuration
 11.1143 + *  to the default value, saved from the EEPROM.
 11.1144 + **/
 11.1145 +s32 igb_cleanup_led(struct e1000_hw *hw)
 11.1146 +{
 11.1147 +	wr32(E1000_LEDCTL, hw->mac.ledctl_default);
 11.1148 +	return 0;
 11.1149 +}
 11.1150 +
 11.1151 +/**
 11.1152 + *  igb_blink_led - Blink LED
 11.1153 + *  @hw: pointer to the HW structure
 11.1154 + *
 11.1155 + *  Blink the led's which are set to be on.
 11.1156 + **/
 11.1157 +s32 igb_blink_led(struct e1000_hw *hw)
 11.1158 +{
 11.1159 +	u32 ledctl_blink = 0;
 11.1160 +	u32 i;
 11.1161 +
 11.1162 +	if (hw->phy.media_type == e1000_media_type_fiber) {
 11.1163 +		/* always blink LED0 for PCI-E fiber */
 11.1164 +		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
 11.1165 +		     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
 11.1166 +	} else {
 11.1167 +		/*
 11.1168 +		 * set the blink bit for each LED that's "on" (0x0E)
 11.1169 +		 * in ledctl_mode2
 11.1170 +		 */
 11.1171 +		ledctl_blink = hw->mac.ledctl_mode2;
 11.1172 +		for (i = 0; i < 4; i++)
 11.1173 +			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
 11.1174 +			    E1000_LEDCTL_MODE_LED_ON)
 11.1175 +				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
 11.1176 +						 (i * 8));
 11.1177 +	}
 11.1178 +
 11.1179 +	wr32(E1000_LEDCTL, ledctl_blink);
 11.1180 +
 11.1181 +	return 0;
 11.1182 +}
 11.1183 +
 11.1184 +/**
 11.1185 + *  igb_led_off - Turn LED off
 11.1186 + *  @hw: pointer to the HW structure
 11.1187 + *
 11.1188 + *  Turn LED off.
 11.1189 + **/
 11.1190 +s32 igb_led_off(struct e1000_hw *hw)
 11.1191 +{
 11.1192 +	u32 ctrl;
 11.1193 +
 11.1194 +	switch (hw->phy.media_type) {
 11.1195 +	case e1000_media_type_fiber:
 11.1196 +		ctrl = rd32(E1000_CTRL);
 11.1197 +		ctrl |= E1000_CTRL_SWDPIN0;
 11.1198 +		ctrl |= E1000_CTRL_SWDPIO0;
 11.1199 +		wr32(E1000_CTRL, ctrl);
 11.1200 +		break;
 11.1201 +	case e1000_media_type_copper:
 11.1202 +		wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
 11.1203 +		break;
 11.1204 +	default:
 11.1205 +		break;
 11.1206 +	}
 11.1207 +
 11.1208 +	return 0;
 11.1209 +}
 11.1210 +
 11.1211 +/**
 11.1212 + *  igb_disable_pcie_master - Disables PCI-express master access
 11.1213 + *  @hw: pointer to the HW structure
 11.1214 + *
 11.1215 + *  Returns 0 (0) if successful, else returns -10
 11.1216 + *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
 11.1217 + *  the master requests to be disabled.
 11.1218 + *
 11.1219 + *  Disables PCI-Express master access and verifies there are no pending
 11.1220 + *  requests.
 11.1221 + **/
 11.1222 +s32 igb_disable_pcie_master(struct e1000_hw *hw)
 11.1223 +{
 11.1224 +	u32 ctrl;
 11.1225 +	s32 timeout = MASTER_DISABLE_TIMEOUT;
 11.1226 +	s32 ret_val = 0;
 11.1227 +
 11.1228 +	if (hw->bus.type != e1000_bus_type_pci_express)
 11.1229 +		goto out;
 11.1230 +
 11.1231 +	ctrl = rd32(E1000_CTRL);
 11.1232 +	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
 11.1233 +	wr32(E1000_CTRL, ctrl);
 11.1234 +
 11.1235 +	while (timeout) {
 11.1236 +		if (!(rd32(E1000_STATUS) &
 11.1237 +		      E1000_STATUS_GIO_MASTER_ENABLE))
 11.1238 +			break;
 11.1239 +		udelay(100);
 11.1240 +		timeout--;
 11.1241 +	}
 11.1242 +
 11.1243 +	if (!timeout) {
 11.1244 +		hw_dbg("Master requests are pending.\n");
 11.1245 +		ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
 11.1246 +		goto out;
 11.1247 +	}
 11.1248 +
 11.1249 +out:
 11.1250 +	return ret_val;
 11.1251 +}
 11.1252 +
 11.1253 +/**
 11.1254 + *  igb_reset_adaptive - Reset Adaptive Interframe Spacing
 11.1255 + *  @hw: pointer to the HW structure
 11.1256 + *
 11.1257 + *  Reset the Adaptive Interframe Spacing throttle to default values.
 11.1258 + **/
 11.1259 +void igb_reset_adaptive(struct e1000_hw *hw)
 11.1260 +{
 11.1261 +	struct e1000_mac_info *mac = &hw->mac;
 11.1262 +
 11.1263 +	if (!mac->adaptive_ifs) {
 11.1264 +		hw_dbg("Not in Adaptive IFS mode!\n");
 11.1265 +		goto out;
 11.1266 +	}
 11.1267 +
 11.1268 +	if (!mac->ifs_params_forced) {
 11.1269 +		mac->current_ifs_val = 0;
 11.1270 +		mac->ifs_min_val = IFS_MIN;
 11.1271 +		mac->ifs_max_val = IFS_MAX;
 11.1272 +		mac->ifs_step_size = IFS_STEP;
 11.1273 +		mac->ifs_ratio = IFS_RATIO;
 11.1274 +	}
 11.1275 +
 11.1276 +	mac->in_ifs_mode = false;
 11.1277 +	wr32(E1000_AIT, 0);
 11.1278 +out:
 11.1279 +	return;
 11.1280 +}
 11.1281 +
 11.1282 +/**
 11.1283 + *  igb_update_adaptive - Update Adaptive Interframe Spacing
 11.1284 + *  @hw: pointer to the HW structure
 11.1285 + *
 11.1286 + *  Update the Adaptive Interframe Spacing Throttle value based on the
 11.1287 + *  time between transmitted packets and time between collisions.
 11.1288 + **/
 11.1289 +void igb_update_adaptive(struct e1000_hw *hw)
 11.1290 +{
 11.1291 +	struct e1000_mac_info *mac = &hw->mac;
 11.1292 +
 11.1293 +	if (!mac->adaptive_ifs) {
 11.1294 +		hw_dbg("Not in Adaptive IFS mode!\n");
 11.1295 +		goto out;
 11.1296 +	}
 11.1297 +
 11.1298 +	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
 11.1299 +		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
 11.1300 +			mac->in_ifs_mode = true;
 11.1301 +			if (mac->current_ifs_val < mac->ifs_max_val) {
 11.1302 +				if (!mac->current_ifs_val)
 11.1303 +					mac->current_ifs_val = mac->ifs_min_val;
 11.1304 +				else
 11.1305 +					mac->current_ifs_val +=
 11.1306 +						mac->ifs_step_size;
 11.1307 +				wr32(E1000_AIT,
 11.1308 +						mac->current_ifs_val);
 11.1309 +			}
 11.1310 +		}
 11.1311 +	} else {
 11.1312 +		if (mac->in_ifs_mode &&
 11.1313 +		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
 11.1314 +			mac->current_ifs_val = 0;
 11.1315 +			mac->in_ifs_mode = false;
 11.1316 +			wr32(E1000_AIT, 0);
 11.1317 +		}
 11.1318 +	}
 11.1319 +out:
 11.1320 +	return;
 11.1321 +}
 11.1322 +
 11.1323 +/**
 11.1324 + *  igb_validate_mdi_setting - Verify MDI/MDIx settings
 11.1325 + *  @hw: pointer to the HW structure
 11.1326 + *
 11.1327 + *  Verify that when not using auto-negotitation that MDI/MDIx is correctly
 11.1328 + *  set, which is forced to MDI mode only.
 11.1329 + **/
 11.1330 +s32 igb_validate_mdi_setting(struct e1000_hw *hw)
 11.1331 +{
 11.1332 +	s32 ret_val = 0;
 11.1333 +
 11.1334 +	if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
 11.1335 +		hw_dbg("Invalid MDI setting detected\n");
 11.1336 +		hw->phy.mdix = 1;
 11.1337 +		ret_val = -E1000_ERR_CONFIG;
 11.1338 +		goto out;
 11.1339 +	}
 11.1340 +
 11.1341 +out:
 11.1342 +	return ret_val;
 11.1343 +}
 11.1344 +
 11.1345 +/**
 11.1346 + *  igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
 11.1347 + *  @hw: pointer to the HW structure
 11.1348 + *  @reg: 32bit register offset such as E1000_SCTL
 11.1349 + *  @offset: register offset to write to
 11.1350 + *  @data: data to write at register offset
 11.1351 + *
 11.1352 + *  Writes an address/data control type register.  There are several of these
 11.1353 + *  and they all have the format address << 8 | data and bit 31 is polled for
 11.1354 + *  completion.
 11.1355 + **/
 11.1356 +s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
 11.1357 +			      u32 offset, u8 data)
 11.1358 +{
 11.1359 +	u32 i, regvalue = 0;
 11.1360 +	s32 ret_val = 0;
 11.1361 +
 11.1362 +	/* Set up the address and data */
 11.1363 +	regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
 11.1364 +	wr32(reg, regvalue);
 11.1365 +
 11.1366 +	/* Poll the ready bit to see if the MDI read completed */
 11.1367 +	for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
 11.1368 +		udelay(5);
 11.1369 +		regvalue = rd32(reg);
 11.1370 +		if (regvalue & E1000_GEN_CTL_READY)
 11.1371 +			break;
 11.1372 +	}
 11.1373 +	if (!(regvalue & E1000_GEN_CTL_READY)) {
 11.1374 +		hw_dbg("Reg %08x did not indicate ready\n", reg);
 11.1375 +		ret_val = -E1000_ERR_PHY;
 11.1376 +		goto out;
 11.1377 +	}
 11.1378 +
 11.1379 +out:
 11.1380 +	return ret_val;
 11.1381 +}
 11.1382 +
 11.1383 +/**
 11.1384 + *  igb_enable_mng_pass_thru - Enable processing of ARP's
 11.1385 + *  @hw: pointer to the HW structure
 11.1386 + *
 11.1387 + *  Verifies the hardware needs to allow ARPs to be processed by the host.
 11.1388 + **/
 11.1389 +bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
 11.1390 +{
 11.1391 +	u32 manc;
 11.1392 +	u32 fwsm, factps;
 11.1393 +	bool ret_val = false;
 11.1394 +
 11.1395 +	if (!hw->mac.asf_firmware_present)
 11.1396 +		goto out;
 11.1397 +
 11.1398 +	manc = rd32(E1000_MANC);
 11.1399 +
 11.1400 +	if (!(manc & E1000_MANC_RCV_TCO_EN) ||
 11.1401 +	    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
 11.1402 +		goto out;
 11.1403 +
 11.1404 +	if (hw->mac.arc_subsystem_valid) {
 11.1405 +		fwsm = rd32(E1000_FWSM);
 11.1406 +		factps = rd32(E1000_FACTPS);
 11.1407 +
 11.1408 +		if (!(factps & E1000_FACTPS_MNGCG) &&
 11.1409 +		    ((fwsm & E1000_FWSM_MODE_MASK) ==
 11.1410 +		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
 11.1411 +			ret_val = true;
 11.1412 +			goto out;
 11.1413 +		}
 11.1414 +	} else {
 11.1415 +		if ((manc & E1000_MANC_SMBUS_EN) &&
 11.1416 +		    !(manc & E1000_MANC_ASF_EN)) {
 11.1417 +			ret_val = true;
 11.1418 +			goto out;
 11.1419 +		}
 11.1420 +	}
 11.1421 +
 11.1422 +out:
 11.1423 +	return ret_val;
 11.1424 +}
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/drivers/net/igb/e1000_mac.h	Tue Feb 17 11:25:51 2009 +0000
    12.3 @@ -0,0 +1,96 @@
    12.4 +/*******************************************************************************
    12.5 +
    12.6 +  Intel(R) Gigabit Ethernet Linux driver
    12.7 +  Copyright(c) 2007 Intel Corporation.
    12.8 +
    12.9 +  This program is free software; you can redistribute it and/or modify it
   12.10 +  under the terms and conditions of the GNU General Public License,
   12.11 +  version 2, as published by the Free Software Foundation.
   12.12 +
   12.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   12.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   12.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   12.16 +  more details.
   12.17 +
   12.18 +  You should have received a copy of the GNU General Public License along with
   12.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   12.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   12.21 +
   12.22 +  The full GNU General Public License is included in this distribution in
   12.23 +  the file called "COPYING".
   12.24 +
   12.25 +  Contact Information:
   12.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   12.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   12.28 +
   12.29 +*******************************************************************************/
   12.30 +
   12.31 +#ifndef _E1000_MAC_H_
   12.32 +#define _E1000_MAC_H_
   12.33 +
   12.34 +#include "e1000_hw.h"
   12.35 +
   12.36 +#include "e1000_phy.h"
   12.37 +#include "e1000_nvm.h"
   12.38 +#include "e1000_defines.h"
   12.39 +
   12.40 +/*
   12.41 + * Functions that should not be called directly from drivers but can be used
   12.42 + * by other files in this 'shared code'
   12.43 + */
   12.44 +s32  igb_blink_led(struct e1000_hw *hw);
   12.45 +s32  igb_check_for_copper_link(struct e1000_hw *hw);
   12.46 +s32  igb_cleanup_led(struct e1000_hw *hw);
   12.47 +s32  igb_config_fc_after_link_up(struct e1000_hw *hw);
   12.48 +s32  igb_disable_pcie_master(struct e1000_hw *hw);
   12.49 +s32  igb_force_mac_fc(struct e1000_hw *hw);
   12.50 +s32  igb_get_auto_rd_done(struct e1000_hw *hw);
   12.51 +s32  igb_get_bus_info_pcie(struct e1000_hw *hw);
   12.52 +s32  igb_get_hw_semaphore(struct e1000_hw *hw);
   12.53 +s32  igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
   12.54 +				       u16 *duplex);
   12.55 +s32  igb_id_led_init(struct e1000_hw *hw);
   12.56 +s32  igb_led_off(struct e1000_hw *hw);
   12.57 +s32  igb_setup_link(struct e1000_hw *hw);
   12.58 +s32  igb_validate_mdi_setting(struct e1000_hw *hw);
   12.59 +s32  igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
   12.60 +			       u32 offset, u8 data);
   12.61 +
   12.62 +void igb_clear_hw_cntrs_base(struct e1000_hw *hw);
   12.63 +void igb_clear_vfta(struct e1000_hw *hw);
   12.64 +void igb_config_collision_dist(struct e1000_hw *hw);
   12.65 +void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
   12.66 +void igb_put_hw_semaphore(struct e1000_hw *hw);
   12.67 +void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
   12.68 +s32  igb_check_alt_mac_addr(struct e1000_hw *hw);
   12.69 +void igb_remove_device(struct e1000_hw *hw);
   12.70 +void igb_reset_adaptive(struct e1000_hw *hw);
   12.71 +void igb_update_adaptive(struct e1000_hw *hw);
   12.72 +void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
   12.73 +
   12.74 +bool igb_enable_mng_pass_thru(struct e1000_hw *hw);
   12.75 +
   12.76 +enum e1000_mng_mode {
   12.77 +	e1000_mng_mode_none = 0,
   12.78 +	e1000_mng_mode_asf,
   12.79 +	e1000_mng_mode_pt,
   12.80 +	e1000_mng_mode_ipmi,
   12.81 +	e1000_mng_mode_host_if_only
   12.82 +};
   12.83 +
   12.84 +#define E1000_FACTPS_MNGCG    0x20000000
   12.85 +
   12.86 +#define E1000_FWSM_MODE_MASK  0xE
   12.87 +#define E1000_FWSM_MODE_SHIFT 1
   12.88 +
   12.89 +#define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
   12.90 +#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
   12.91 +
   12.92 +#define E1000_HICR_EN              0x01  /* Enable bit - RO */
   12.93 +/* Driver sets this bit when done to put command in RAM */
   12.94 +#define E1000_HICR_C               0x02
   12.95 +
   12.96 +extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
   12.97 +extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
   12.98 +
   12.99 +#endif
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/drivers/net/igb/e1000_nvm.c	Tue Feb 17 11:25:51 2009 +0000
    13.3 @@ -0,0 +1,605 @@
    13.4 +/*******************************************************************************
    13.5 +
    13.6 +  Intel(R) Gigabit Ethernet Linux driver
    13.7 +  Copyright(c) 2007 Intel Corporation.
    13.8 +
    13.9 +  This program is free software; you can redistribute it and/or modify it
   13.10 +  under the terms and conditions of the GNU General Public License,
   13.11 +  version 2, as published by the Free Software Foundation.
   13.12 +
   13.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   13.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   13.16 +  more details.
   13.17 +
   13.18 +  You should have received a copy of the GNU General Public License along with
   13.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   13.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   13.21 +
   13.22 +  The full GNU General Public License is included in this distribution in
   13.23 +  the file called "COPYING".
   13.24 +
   13.25 +  Contact Information:
   13.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   13.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   13.28 +
   13.29 +*******************************************************************************/
   13.30 +
   13.31 +#include <linux/if_ether.h>
   13.32 +#include <linux/delay.h>
   13.33 +
   13.34 +#include "e1000_mac.h"
   13.35 +#include "e1000_nvm.h"
   13.36 +
   13.37 +/**
   13.38 + *  igb_raise_eec_clk - Raise EEPROM clock
   13.39 + *  @hw: pointer to the HW structure
   13.40 + *  @eecd: pointer to the EEPROM
   13.41 + *
   13.42 + *  Enable/Raise the EEPROM clock bit.
   13.43 + **/
   13.44 +static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
   13.45 +{
   13.46 +	*eecd = *eecd | E1000_EECD_SK;
   13.47 +	wr32(E1000_EECD, *eecd);
   13.48 +	wrfl();
   13.49 +	udelay(hw->nvm.delay_usec);
   13.50 +}
   13.51 +
   13.52 +/**
   13.53 + *  igb_lower_eec_clk - Lower EEPROM clock
   13.54 + *  @hw: pointer to the HW structure
   13.55 + *  @eecd: pointer to the EEPROM
   13.56 + *
   13.57 + *  Clear/Lower the EEPROM clock bit.
   13.58 + **/
   13.59 +static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
   13.60 +{
   13.61 +	*eecd = *eecd & ~E1000_EECD_SK;
   13.62 +	wr32(E1000_EECD, *eecd);
   13.63 +	wrfl();
   13.64 +	udelay(hw->nvm.delay_usec);
   13.65 +}
   13.66 +
   13.67 +/**
   13.68 + *  igb_shift_out_eec_bits - Shift data bits our to the EEPROM
   13.69 + *  @hw: pointer to the HW structure
   13.70 + *  @data: data to send to the EEPROM
   13.71 + *  @count: number of bits to shift out
   13.72 + *
   13.73 + *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
   13.74 + *  "data" parameter will be shifted out to the EEPROM one bit at a time.
   13.75 + *  In order to do this, "data" must be broken down into bits.
   13.76 + **/
   13.77 +static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
   13.78 +{
   13.79 +	struct e1000_nvm_info *nvm = &hw->nvm;
   13.80 +	u32 eecd = rd32(E1000_EECD);
   13.81 +	u32 mask;
   13.82 +
   13.83 +	mask = 0x01 << (count - 1);
   13.84 +	if (nvm->type == e1000_nvm_eeprom_microwire)
   13.85 +		eecd &= ~E1000_EECD_DO;
   13.86 +	else if (nvm->type == e1000_nvm_eeprom_spi)
   13.87 +		eecd |= E1000_EECD_DO;
   13.88 +
   13.89 +	do {
   13.90 +		eecd &= ~E1000_EECD_DI;
   13.91 +
   13.92 +		if (data & mask)
   13.93 +			eecd |= E1000_EECD_DI;
   13.94 +
   13.95 +		wr32(E1000_EECD, eecd);
   13.96 +		wrfl();
   13.97 +
   13.98 +		udelay(nvm->delay_usec);
   13.99 +
  13.100 +		igb_raise_eec_clk(hw, &eecd);
  13.101 +		igb_lower_eec_clk(hw, &eecd);
  13.102 +
  13.103 +		mask >>= 1;
  13.104 +	} while (mask);
  13.105 +
  13.106 +	eecd &= ~E1000_EECD_DI;
  13.107 +	wr32(E1000_EECD, eecd);
  13.108 +}
  13.109 +
  13.110 +/**
  13.111 + *  igb_shift_in_eec_bits - Shift data bits in from the EEPROM
  13.112 + *  @hw: pointer to the HW structure
  13.113 + *  @count: number of bits to shift in
  13.114 + *
  13.115 + *  In order to read a register from the EEPROM, we need to shift 'count' bits
  13.116 + *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
  13.117 + *  the EEPROM (setting the SK bit), and then reading the value of the data out
  13.118 + *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
  13.119 + *  always be clear.
  13.120 + **/
  13.121 +static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
  13.122 +{
  13.123 +	u32 eecd;
  13.124 +	u32 i;
  13.125 +	u16 data;
  13.126 +
  13.127 +	eecd = rd32(E1000_EECD);
  13.128 +
  13.129 +	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  13.130 +	data = 0;
  13.131 +
  13.132 +	for (i = 0; i < count; i++) {
  13.133 +		data <<= 1;
  13.134 +		igb_raise_eec_clk(hw, &eecd);
  13.135 +
  13.136 +		eecd = rd32(E1000_EECD);
  13.137 +
  13.138 +		eecd &= ~E1000_EECD_DI;
  13.139 +		if (eecd & E1000_EECD_DO)
  13.140 +			data |= 1;
  13.141 +
  13.142 +		igb_lower_eec_clk(hw, &eecd);
  13.143 +	}
  13.144 +
  13.145 +	return data;
  13.146 +}
  13.147 +
  13.148 +/**
  13.149 + *  igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
  13.150 + *  @hw: pointer to the HW structure
  13.151 + *  @ee_reg: EEPROM flag for polling
  13.152 + *
  13.153 + *  Polls the EEPROM status bit for either read or write completion based
  13.154 + *  upon the value of 'ee_reg'.
  13.155 + **/
  13.156 +static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
  13.157 +{
  13.158 +	u32 attempts = 100000;
  13.159 +	u32 i, reg = 0;
  13.160 +	s32 ret_val = -E1000_ERR_NVM;
  13.161 +
  13.162 +	for (i = 0; i < attempts; i++) {
  13.163 +		if (ee_reg == E1000_NVM_POLL_READ)
  13.164 +			reg = rd32(E1000_EERD);
  13.165 +		else
  13.166 +			reg = rd32(E1000_EEWR);
  13.167 +
  13.168 +		if (reg & E1000_NVM_RW_REG_DONE) {
  13.169 +			ret_val = 0;
  13.170 +			break;
  13.171 +		}
  13.172 +
  13.173 +		udelay(5);
  13.174 +	}
  13.175 +
  13.176 +	return ret_val;
  13.177 +}
  13.178 +
  13.179 +/**
  13.180 + *  igb_acquire_nvm - Generic request for access to EEPROM
  13.181 + *  @hw: pointer to the HW structure
  13.182 + *
  13.183 + *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
  13.184 + *  Return successful if access grant bit set, else clear the request for
  13.185 + *  EEPROM access and return -E1000_ERR_NVM (-1).
  13.186 + **/
  13.187 +s32 igb_acquire_nvm(struct e1000_hw *hw)
  13.188 +{
  13.189 +	u32 eecd = rd32(E1000_EECD);
  13.190 +	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
  13.191 +	s32 ret_val = 0;
  13.192 +
  13.193 +
  13.194 +	wr32(E1000_EECD, eecd | E1000_EECD_REQ);
  13.195 +	eecd = rd32(E1000_EECD);
  13.196 +
  13.197 +	while (timeout) {
  13.198 +		if (eecd & E1000_EECD_GNT)
  13.199 +			break;
  13.200 +		udelay(5);
  13.201 +		eecd = rd32(E1000_EECD);
  13.202 +		timeout--;
  13.203 +	}
  13.204 +
  13.205 +	if (!timeout) {
  13.206 +		eecd &= ~E1000_EECD_REQ;
  13.207 +		wr32(E1000_EECD, eecd);
  13.208 +		hw_dbg("Could not acquire NVM grant\n");
  13.209 +		ret_val = -E1000_ERR_NVM;
  13.210 +	}
  13.211 +
  13.212 +	return ret_val;
  13.213 +}
  13.214 +
  13.215 +/**
  13.216 + *  igb_standby_nvm - Return EEPROM to standby state
  13.217 + *  @hw: pointer to the HW structure
  13.218 + *
  13.219 + *  Return the EEPROM to a standby state.
  13.220 + **/
  13.221 +static void igb_standby_nvm(struct e1000_hw *hw)
  13.222 +{
  13.223 +	struct e1000_nvm_info *nvm = &hw->nvm;
  13.224 +	u32 eecd = rd32(E1000_EECD);
  13.225 +
  13.226 +	if (nvm->type == e1000_nvm_eeprom_microwire) {
  13.227 +		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  13.228 +		wr32(E1000_EECD, eecd);
  13.229 +		wrfl();
  13.230 +		udelay(nvm->delay_usec);
  13.231 +
  13.232 +		igb_raise_eec_clk(hw, &eecd);
  13.233 +
  13.234 +		/* Select EEPROM */
  13.235 +		eecd |= E1000_EECD_CS;
  13.236 +		wr32(E1000_EECD, eecd);
  13.237 +		wrfl();
  13.238 +		udelay(nvm->delay_usec);
  13.239 +
  13.240 +		igb_lower_eec_clk(hw, &eecd);
  13.241 +	} else if (nvm->type == e1000_nvm_eeprom_spi) {
  13.242 +		/* Toggle CS to flush commands */
  13.243 +		eecd |= E1000_EECD_CS;
  13.244 +		wr32(E1000_EECD, eecd);
  13.245 +		wrfl();
  13.246 +		udelay(nvm->delay_usec);
  13.247 +		eecd &= ~E1000_EECD_CS;
  13.248 +		wr32(E1000_EECD, eecd);
  13.249 +		wrfl();
  13.250 +		udelay(nvm->delay_usec);
  13.251 +	}
  13.252 +}
  13.253 +
  13.254 +/**
  13.255 + *  e1000_stop_nvm - Terminate EEPROM command
  13.256 + *  @hw: pointer to the HW structure
  13.257 + *
  13.258 + *  Terminates the current command by inverting the EEPROM's chip select pin.
  13.259 + **/
  13.260 +static void e1000_stop_nvm(struct e1000_hw *hw)
  13.261 +{
  13.262 +	u32 eecd;
  13.263 +
  13.264 +	eecd = rd32(E1000_EECD);
  13.265 +	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
  13.266 +		/* Pull CS high */
  13.267 +		eecd |= E1000_EECD_CS;
  13.268 +		igb_lower_eec_clk(hw, &eecd);
  13.269 +	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
  13.270 +		/* CS on Microcwire is active-high */
  13.271 +		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  13.272 +		wr32(E1000_EECD, eecd);
  13.273 +		igb_raise_eec_clk(hw, &eecd);
  13.274 +		igb_lower_eec_clk(hw, &eecd);
  13.275 +	}
  13.276 +}
  13.277 +
  13.278 +/**
  13.279 + *  igb_release_nvm - Release exclusive access to EEPROM
  13.280 + *  @hw: pointer to the HW structure
  13.281 + *
  13.282 + *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
  13.283 + **/
  13.284 +void igb_release_nvm(struct e1000_hw *hw)
  13.285 +{
  13.286 +	u32 eecd;
  13.287 +
  13.288 +	e1000_stop_nvm(hw);
  13.289 +
  13.290 +	eecd = rd32(E1000_EECD);
  13.291 +	eecd &= ~E1000_EECD_REQ;
  13.292 +	wr32(E1000_EECD, eecd);
  13.293 +}
  13.294 +
  13.295 +/**
  13.296 + *  igb_ready_nvm_eeprom - Prepares EEPROM for read/write
  13.297 + *  @hw: pointer to the HW structure
  13.298 + *
  13.299 + *  Setups the EEPROM for reading and writing.
  13.300 + **/
  13.301 +static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
  13.302 +{
  13.303 +	struct e1000_nvm_info *nvm = &hw->nvm;
  13.304 +	u32 eecd = rd32(E1000_EECD);
  13.305 +	s32 ret_val = 0;
  13.306 +	u16 timeout = 0;
  13.307 +	u8 spi_stat_reg;
  13.308 +
  13.309 +
  13.310 +	if (nvm->type == e1000_nvm_eeprom_microwire) {
  13.311 +		/* Clear SK and DI */
  13.312 +		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  13.313 +		wr32(E1000_EECD, eecd);
  13.314 +		/* Set CS */
  13.315 +		eecd |= E1000_EECD_CS;
  13.316 +		wr32(E1000_EECD, eecd);
  13.317 +	} else if (nvm->type == e1000_nvm_eeprom_spi) {
  13.318 +		/* Clear SK and CS */
  13.319 +		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  13.320 +		wr32(E1000_EECD, eecd);
  13.321 +		udelay(1);
  13.322 +		timeout = NVM_MAX_RETRY_SPI;
  13.323 +
  13.324 +		/*
  13.325 +		 * Read "Status Register" repeatedly until the LSB is cleared.
  13.326 +		 * The EEPROM will signal that the command has been completed
  13.327 +		 * by clearing bit 0 of the internal status register.  If it's
  13.328 +		 * not cleared within 'timeout', then error out.
  13.329 +		 */
  13.330 +		while (timeout) {
  13.331 +			igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
  13.332 +						 hw->nvm.opcode_bits);
  13.333 +			spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
  13.334 +			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
  13.335 +				break;
  13.336 +
  13.337 +			udelay(5);
  13.338 +			igb_standby_nvm(hw);
  13.339 +			timeout--;
  13.340 +		}
  13.341 +
  13.342 +		if (!timeout) {
  13.343 +			hw_dbg("SPI NVM Status error\n");
  13.344 +			ret_val = -E1000_ERR_NVM;
  13.345 +			goto out;
  13.346 +		}
  13.347 +	}
  13.348 +
  13.349 +out:
  13.350 +	return ret_val;
  13.351 +}
  13.352 +
  13.353 +/**
  13.354 + *  igb_read_nvm_eerd - Reads EEPROM using EERD register
  13.355 + *  @hw: pointer to the HW structure
  13.356 + *  @offset: offset of word in the EEPROM to read
  13.357 + *  @words: number of words to read
  13.358 + *  @data: word read from the EEPROM
  13.359 + *
  13.360 + *  Reads a 16 bit word from the EEPROM using the EERD register.
  13.361 + **/
  13.362 +s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
  13.363 +{
  13.364 +	struct e1000_nvm_info *nvm = &hw->nvm;
  13.365 +	u32 i, eerd = 0;
  13.366 +	s32 ret_val = 0;
  13.367 +
  13.368 +	/*
  13.369 +	 * A check for invalid values:  offset too large, too many words,
  13.370 +	 * and not enough words.
  13.371 +	 */
  13.372 +	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
  13.373 +	    (words == 0)) {
  13.374 +		hw_dbg("nvm parameter(s) out of bounds\n");
  13.375 +		ret_val = -E1000_ERR_NVM;
  13.376 +		goto out;
  13.377 +	}
  13.378 +
  13.379 +	for (i = 0; i < words; i++) {
  13.380 +		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
  13.381 +		       E1000_NVM_RW_REG_START;
  13.382 +
  13.383 +		wr32(E1000_EERD, eerd);
  13.384 +		ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
  13.385 +		if (ret_val)
  13.386 +			break;
  13.387 +
  13.388 +		data[i] = (rd32(E1000_EERD) >>
  13.389 +			   E1000_NVM_RW_REG_DATA);
  13.390 +	}
  13.391 +
  13.392 +out:
  13.393 +	return ret_val;
  13.394 +}
  13.395 +
  13.396 +/**
  13.397 + *  igb_write_nvm_spi - Write to EEPROM using SPI
  13.398 + *  @hw: pointer to the HW structure
  13.399 + *  @offset: offset within the EEPROM to be written to
  13.400 + *  @words: number of words to write
  13.401 + *  @data: 16 bit word(s) to be written to the EEPROM
  13.402 + *
  13.403 + *  Writes data to EEPROM at offset using SPI interface.
  13.404 + *
  13.405 + *  If e1000_update_nvm_checksum is not called after this function , the
  13.406 + *  EEPROM will most likley contain an invalid checksum.
  13.407 + **/
  13.408 +s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
  13.409 +{
  13.410 +	struct e1000_nvm_info *nvm = &hw->nvm;
  13.411 +	s32 ret_val;
  13.412 +	u16 widx = 0;
  13.413 +
  13.414 +	/*
  13.415 +	 * A check for invalid values:  offset too large, too many words,
  13.416 +	 * and not enough words.
  13.417 +	 */
  13.418 +	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
  13.419 +	    (words == 0)) {
  13.420 +		hw_dbg("nvm parameter(s) out of bounds\n");
  13.421 +		ret_val = -E1000_ERR_NVM;
  13.422 +		goto out;
  13.423 +	}
  13.424 +
  13.425 +	ret_val = hw->nvm.ops.acquire_nvm(hw);
  13.426 +	if (ret_val)
  13.427 +		goto out;
  13.428 +
  13.429 +	msleep(10);
  13.430 +
  13.431 +	while (widx < words) {
  13.432 +		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
  13.433 +
  13.434 +		ret_val = igb_ready_nvm_eeprom(hw);
  13.435 +		if (ret_val)
  13.436 +			goto release;
  13.437 +
  13.438 +		igb_standby_nvm(hw);
  13.439 +
  13.440 +		/* Send the WRITE ENABLE command (8 bit opcode) */
  13.441 +		igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
  13.442 +					 nvm->opcode_bits);
  13.443 +
  13.444 +		igb_standby_nvm(hw);
  13.445 +
  13.446 +		/*
  13.447 +		 * Some SPI eeproms use the 8th address bit embedded in the
  13.448 +		 * opcode
  13.449 +		 */
  13.450 +		if ((nvm->address_bits == 8) && (offset >= 128))
  13.451 +			write_opcode |= NVM_A8_OPCODE_SPI;
  13.452 +
  13.453 +		/* Send the Write command (8-bit opcode + addr) */
  13.454 +		igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
  13.455 +		igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
  13.456 +					 nvm->address_bits);
  13.457 +
  13.458 +		/* Loop to allow for up to whole page write of eeprom */
  13.459 +		while (widx < words) {
  13.460 +			u16 word_out = data[widx];
  13.461 +			word_out = (word_out >> 8) | (word_out << 8);
  13.462 +			igb_shift_out_eec_bits(hw, word_out, 16);
  13.463 +			widx++;
  13.464 +
  13.465 +			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
  13.466 +				igb_standby_nvm(hw);
  13.467 +				break;
  13.468 +			}
  13.469 +		}
  13.470 +	}
  13.471 +
  13.472 +	msleep(10);
  13.473 +release:
  13.474 +	hw->nvm.ops.release_nvm(hw);
  13.475 +
  13.476 +out:
  13.477 +	return ret_val;
  13.478 +}
  13.479 +
  13.480 +/**
  13.481 + *  igb_read_part_num - Read device part number
  13.482 + *  @hw: pointer to the HW structure
  13.483 + *  @part_num: pointer to device part number
  13.484 + *
  13.485 + *  Reads the product board assembly (PBA) number from the EEPROM and stores
  13.486 + *  the value in part_num.
  13.487 + **/
  13.488 +s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num)
  13.489 +{
  13.490 +	s32  ret_val;
  13.491 +	u16 nvm_data;
  13.492 +
  13.493 +	ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
  13.494 +	if (ret_val) {
  13.495 +		hw_dbg("NVM Read Error\n");
  13.496 +		goto out;
  13.497 +	}
  13.498 +	*part_num = (u32)(nvm_data << 16);
  13.499 +
  13.500 +	ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
  13.501 +	if (ret_val) {
  13.502 +		hw_dbg("NVM Read Error\n");
  13.503 +		goto out;
  13.504 +	}
  13.505 +	*part_num |= nvm_data;
  13.506 +
  13.507 +out:
  13.508 +	return ret_val;
  13.509 +}
  13.510 +
  13.511 +/**
  13.512 + *  igb_read_mac_addr - Read device MAC address
  13.513 + *  @hw: pointer to the HW structure
  13.514 + *
  13.515 + *  Reads the device MAC address from the EEPROM and stores the value.
  13.516 + *  Since devices with two ports use the same EEPROM, we increment the
  13.517 + *  last bit in the MAC address for the second port.
  13.518 + **/
  13.519 +s32 igb_read_mac_addr(struct e1000_hw *hw)
  13.520 +{
  13.521 +	s32  ret_val = 0;
  13.522 +	u16 offset, nvm_data, i;
  13.523 +
  13.524 +	for (i = 0; i < ETH_ALEN; i += 2) {
  13.525 +		offset = i >> 1;
  13.526 +		ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
  13.527 +		if (ret_val) {
  13.528 +			hw_dbg("NVM Read Error\n");
  13.529 +			goto out;
  13.530 +		}
  13.531 +		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
  13.532 +		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
  13.533 +	}
  13.534 +
  13.535 +	/* Flip last bit of mac address if we're on second port */
  13.536 +	if (hw->bus.func == E1000_FUNC_1)
  13.537 +		hw->mac.perm_addr[5] ^= 1;
  13.538 +
  13.539 +	for (i = 0; i < ETH_ALEN; i++)
  13.540 +		hw->mac.addr[i] = hw->mac.perm_addr[i];
  13.541 +
  13.542 +out:
  13.543 +	return ret_val;
  13.544 +}
  13.545 +
  13.546 +/**
  13.547 + *  igb_validate_nvm_checksum - Validate EEPROM checksum
  13.548 + *  @hw: pointer to the HW structure
  13.549 + *
  13.550 + *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
  13.551 + *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
  13.552 + **/
  13.553 +s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
  13.554 +{
  13.555 +	s32 ret_val = 0;
  13.556 +	u16 checksum = 0;
  13.557 +	u16 i, nvm_data;
  13.558 +
  13.559 +	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
  13.560 +		ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
  13.561 +		if (ret_val) {
  13.562 +			hw_dbg("NVM Read Error\n");
  13.563 +			goto out;
  13.564 +		}
  13.565 +		checksum += nvm_data;
  13.566 +	}
  13.567 +
  13.568 +	if (checksum != (u16) NVM_SUM) {
  13.569 +		hw_dbg("NVM Checksum Invalid\n");
  13.570 +		ret_val = -E1000_ERR_NVM;
  13.571 +		goto out;
  13.572 +	}
  13.573 +
  13.574 +out:
  13.575 +	return ret_val;
  13.576 +}
  13.577 +
  13.578 +/**
  13.579 + *  igb_update_nvm_checksum - Update EEPROM checksum
  13.580 + *  @hw: pointer to the HW structure
  13.581 + *
  13.582 + *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
  13.583 + *  up to the checksum.  Then calculates the EEPROM checksum and writes the
  13.584 + *  value to the EEPROM.
  13.585 + **/
  13.586 +s32 igb_update_nvm_checksum(struct e1000_hw *hw)
  13.587 +{
  13.588 +	s32  ret_val;
  13.589 +	u16 checksum = 0;
  13.590 +	u16 i, nvm_data;
  13.591 +
  13.592 +	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
  13.593 +		ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
  13.594 +		if (ret_val) {
  13.595 +			hw_dbg("NVM Read Error while updating checksum.\n");
  13.596 +			goto out;
  13.597 +		}
  13.598 +		checksum += nvm_data;
  13.599 +	}
  13.600 +	checksum = (u16) NVM_SUM - checksum;
  13.601 +	ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
  13.602 +	if (ret_val)
  13.603 +		hw_dbg("NVM Write Error while updating checksum.\n");
  13.604 +
  13.605 +out:
  13.606 +	return ret_val;
  13.607 +}
  13.608 +
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/drivers/net/igb/e1000_nvm.h	Tue Feb 17 11:25:51 2009 +0000
    14.3 @@ -0,0 +1,40 @@
    14.4 +/*******************************************************************************
    14.5 +
    14.6 +  Intel(R) Gigabit Ethernet Linux driver
    14.7 +  Copyright(c) 2007 Intel Corporation.
    14.8 +
    14.9 +  This program is free software; you can redistribute it and/or modify it
   14.10 +  under the terms and conditions of the GNU General Public License,
   14.11 +  version 2, as published by the Free Software Foundation.
   14.12 +
   14.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   14.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   14.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   14.16 +  more details.
   14.17 +
   14.18 +  You should have received a copy of the GNU General Public License along with
   14.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   14.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   14.21 +
   14.22 +  The full GNU General Public License is included in this distribution in
   14.23 +  the file called "COPYING".
   14.24 +
   14.25 +  Contact Information:
   14.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   14.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   14.28 +
   14.29 +*******************************************************************************/
   14.30 +
   14.31 +#ifndef _E1000_NVM_H_
   14.32 +#define _E1000_NVM_H_
   14.33 +
   14.34 +s32  igb_acquire_nvm(struct e1000_hw *hw);
   14.35 +void igb_release_nvm(struct e1000_hw *hw);
   14.36 +s32  igb_read_mac_addr(struct e1000_hw *hw);
   14.37 +s32  igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
   14.38 +s32  igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
   14.39 +s32  igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
   14.40 +s32  igb_validate_nvm_checksum(struct e1000_hw *hw);
   14.41 +s32  igb_update_nvm_checksum(struct e1000_hw *hw);
   14.42 +
   14.43 +#endif
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/drivers/net/igb/e1000_phy.c	Tue Feb 17 11:25:51 2009 +0000
    15.3 @@ -0,0 +1,1805 @@
    15.4 +/*******************************************************************************
    15.5 +
    15.6 +  Intel(R) Gigabit Ethernet Linux driver
    15.7 +  Copyright(c) 2007 Intel Corporation.
    15.8 +
    15.9 +  This program is free software; you can redistribute it and/or modify it
   15.10 +  under the terms and conditions of the GNU General Public License,
   15.11 +  version 2, as published by the Free Software Foundation.
   15.12 +
   15.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   15.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   15.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   15.16 +  more details.
   15.17 +
   15.18 +  You should have received a copy of the GNU General Public License along with
   15.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   15.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   15.21 +
   15.22 +  The full GNU General Public License is included in this distribution in
   15.23 +  the file called "COPYING".
   15.24 +
   15.25 +  Contact Information:
   15.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   15.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   15.28 +
   15.29 +*******************************************************************************/
   15.30 +
   15.31 +#include <linux/if_ether.h>
   15.32 +#include <linux/delay.h>
   15.33 +
   15.34 +#include "e1000_mac.h"
   15.35 +#include "e1000_phy.h"
   15.36 +
   15.37 +static s32  igb_get_phy_cfg_done(struct e1000_hw *hw);
   15.38 +static void igb_release_phy(struct e1000_hw *hw);
   15.39 +static s32  igb_acquire_phy(struct e1000_hw *hw);
   15.40 +static s32  igb_phy_reset_dsp(struct e1000_hw *hw);
   15.41 +static s32  igb_phy_setup_autoneg(struct e1000_hw *hw);
   15.42 +static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
   15.43 +					       u16 *phy_ctrl);
   15.44 +static s32  igb_wait_autoneg(struct e1000_hw *hw);
   15.45 +
   15.46 +/* Cable length tables */
   15.47 +static const u16 e1000_m88_cable_length_table[] =
   15.48 +	{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
   15.49 +#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
   15.50 +		(sizeof(e1000_m88_cable_length_table) / \
   15.51 +		 sizeof(e1000_m88_cable_length_table[0]))
   15.52 +
   15.53 +static const u16 e1000_igp_2_cable_length_table[] =
   15.54 +    { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
   15.55 +      0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
   15.56 +      6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
   15.57 +      21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
   15.58 +      40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
   15.59 +      60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
   15.60 +      83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
   15.61 +      104, 109, 114, 118, 121, 124};
   15.62 +#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
   15.63 +		(sizeof(e1000_igp_2_cable_length_table) / \
   15.64 +		 sizeof(e1000_igp_2_cable_length_table[0]))
   15.65 +
   15.66 +/**
   15.67 + *  igb_check_reset_block - Check if PHY reset is blocked
   15.68 + *  @hw: pointer to the HW structure
   15.69 + *
   15.70 + *  Read the PHY management control register and check whether a PHY reset
   15.71 + *  is blocked.  If a reset is not blocked return 0, otherwise
   15.72 + *  return E1000_BLK_PHY_RESET (12).
   15.73 + **/
   15.74 +s32 igb_check_reset_block(struct e1000_hw *hw)
   15.75 +{
   15.76 +	u32 manc;
   15.77 +
   15.78 +	manc = rd32(E1000_MANC);
   15.79 +
   15.80 +	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
   15.81 +	       E1000_BLK_PHY_RESET : 0;
   15.82 +}
   15.83 +
   15.84 +/**
   15.85 + *  igb_get_phy_id - Retrieve the PHY ID and revision
   15.86 + *  @hw: pointer to the HW structure
   15.87 + *
   15.88 + *  Reads the PHY registers and stores the PHY ID and possibly the PHY
   15.89 + *  revision in the hardware structure.
   15.90 + **/
   15.91 +s32 igb_get_phy_id(struct e1000_hw *hw)
   15.92 +{
   15.93 +	struct e1000_phy_info *phy = &hw->phy;
   15.94 +	s32 ret_val = 0;
   15.95 +	u16 phy_id;
   15.96 +
   15.97 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID1, &phy_id);
   15.98 +	if (ret_val)
   15.99 +		goto out;
  15.100 +
  15.101 +	phy->id = (u32)(phy_id << 16);
  15.102 +	udelay(20);
  15.103 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID2, &phy_id);
  15.104 +	if (ret_val)
  15.105 +		goto out;
  15.106 +
  15.107 +	phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
  15.108 +	phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
  15.109 +
  15.110 +out:
  15.111 +	return ret_val;
  15.112 +}
  15.113 +
  15.114 +/**
  15.115 + *  igb_phy_reset_dsp - Reset PHY DSP
  15.116 + *  @hw: pointer to the HW structure
  15.117 + *
  15.118 + *  Reset the digital signal processor.
  15.119 + **/
  15.120 +static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
  15.121 +{
  15.122 +	s32 ret_val;
  15.123 +
  15.124 +	ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
  15.125 +	if (ret_val)
  15.126 +		goto out;
  15.127 +
  15.128 +	ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
  15.129 +
  15.130 +out:
  15.131 +	return ret_val;
  15.132 +}
  15.133 +
  15.134 +/**
  15.135 + *  igb_read_phy_reg_mdic - Read MDI control register
  15.136 + *  @hw: pointer to the HW structure
  15.137 + *  @offset: register offset to be read
  15.138 + *  @data: pointer to the read data
  15.139 + *
  15.140 + *  Reads the MDI control regsiter in the PHY at offset and stores the
  15.141 + *  information read to data.
  15.142 + **/
  15.143 +static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
  15.144 +{
  15.145 +	struct e1000_phy_info *phy = &hw->phy;
  15.146 +	u32 i, mdic = 0;
  15.147 +	s32 ret_val = 0;
  15.148 +
  15.149 +	if (offset > MAX_PHY_REG_ADDRESS) {
  15.150 +		hw_dbg("PHY Address %d is out of range\n", offset);
  15.151 +		ret_val = -E1000_ERR_PARAM;
  15.152 +		goto out;
  15.153 +	}
  15.154 +
  15.155 +	/*
  15.156 +	 * Set up Op-code, Phy Address, and register offset in the MDI
  15.157 +	 * Control register.  The MAC will take care of interfacing with the
  15.158 +	 * PHY to retrieve the desired data.
  15.159 +	 */
  15.160 +	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  15.161 +		(phy->addr << E1000_MDIC_PHY_SHIFT) |
  15.162 +		(E1000_MDIC_OP_READ));
  15.163 +
  15.164 +	wr32(E1000_MDIC, mdic);
  15.165 +
  15.166 +	/*
  15.167 +	 * Poll the ready bit to see if the MDI read completed
  15.168 +	 * Increasing the time out as testing showed failures with
  15.169 +	 * the lower time out
  15.170 +	 */
  15.171 +	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
  15.172 +		udelay(50);
  15.173 +		mdic = rd32(E1000_MDIC);
  15.174 +		if (mdic & E1000_MDIC_READY)
  15.175 +			break;
  15.176 +	}
  15.177 +	if (!(mdic & E1000_MDIC_READY)) {
  15.178 +		hw_dbg("MDI Read did not complete\n");
  15.179 +		ret_val = -E1000_ERR_PHY;
  15.180 +		goto out;
  15.181 +	}
  15.182 +	if (mdic & E1000_MDIC_ERROR) {
  15.183 +		hw_dbg("MDI Error\n");
  15.184 +		ret_val = -E1000_ERR_PHY;
  15.185 +		goto out;
  15.186 +	}
  15.187 +	*data = (u16) mdic;
  15.188 +
  15.189 +out:
  15.190 +	return ret_val;
  15.191 +}
  15.192 +
  15.193 +/**
  15.194 + *  igb_write_phy_reg_mdic - Write MDI control register
  15.195 + *  @hw: pointer to the HW structure
  15.196 + *  @offset: register offset to write to
  15.197 + *  @data: data to write to register at offset
  15.198 + *
  15.199 + *  Writes data to MDI control register in the PHY at offset.
  15.200 + **/
  15.201 +static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
  15.202 +{
  15.203 +	struct e1000_phy_info *phy = &hw->phy;
  15.204 +	u32 i, mdic = 0;
  15.205 +	s32 ret_val = 0;
  15.206 +
  15.207 +	if (offset > MAX_PHY_REG_ADDRESS) {
  15.208 +		hw_dbg("PHY Address %d is out of range\n", offset);
  15.209 +		ret_val = -E1000_ERR_PARAM;
  15.210 +		goto out;
  15.211 +	}
  15.212 +
  15.213 +	/*
  15.214 +	 * Set up Op-code, Phy Address, and register offset in the MDI
  15.215 +	 * Control register.  The MAC will take care of interfacing with the
  15.216 +	 * PHY to retrieve the desired data.
  15.217 +	 */
  15.218 +	mdic = (((u32)data) |
  15.219 +		(offset << E1000_MDIC_REG_SHIFT) |
  15.220 +		(phy->addr << E1000_MDIC_PHY_SHIFT) |
  15.221 +		(E1000_MDIC_OP_WRITE));
  15.222 +
  15.223 +	wr32(E1000_MDIC, mdic);
  15.224 +
  15.225 +	/*
  15.226 +	 * Poll the ready bit to see if the MDI read completed
  15.227 +	 * Increasing the time out as testing showed failures with
  15.228 +	 * the lower time out
  15.229 +	 */
  15.230 +	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
  15.231 +		udelay(50);
  15.232 +		mdic = rd32(E1000_MDIC);
  15.233 +		if (mdic & E1000_MDIC_READY)
  15.234 +			break;
  15.235 +	}
  15.236 +	if (!(mdic & E1000_MDIC_READY)) {
  15.237 +		hw_dbg("MDI Write did not complete\n");
  15.238 +		ret_val = -E1000_ERR_PHY;
  15.239 +		goto out;
  15.240 +	}
  15.241 +	if (mdic & E1000_MDIC_ERROR) {
  15.242 +		hw_dbg("MDI Error\n");
  15.243 +		ret_val = -E1000_ERR_PHY;
  15.244 +		goto out;
  15.245 +	}
  15.246 +
  15.247 +out:
  15.248 +	return ret_val;
  15.249 +}
  15.250 +
  15.251 +/**
  15.252 + *  igb_read_phy_reg_igp - Read igp PHY register
  15.253 + *  @hw: pointer to the HW structure
  15.254 + *  @offset: register offset to be read
  15.255 + *  @data: pointer to the read data
  15.256 + *
  15.257 + *  Acquires semaphore, if necessary, then reads the PHY register at offset
  15.258 + *  and storing the retrieved information in data.  Release any acquired
  15.259 + *  semaphores before exiting.
  15.260 + **/
  15.261 +s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
  15.262 +{
  15.263 +	s32 ret_val;
  15.264 +
  15.265 +	ret_val = igb_acquire_phy(hw);
  15.266 +	if (ret_val)
  15.267 +		goto out;
  15.268 +
  15.269 +	if (offset > MAX_PHY_MULTI_PAGE_REG) {
  15.270 +		ret_val = igb_write_phy_reg_mdic(hw,
  15.271 +						   IGP01E1000_PHY_PAGE_SELECT,
  15.272 +						   (u16)offset);
  15.273 +		if (ret_val) {
  15.274 +			igb_release_phy(hw);
  15.275 +			goto out;
  15.276 +		}
  15.277 +	}
  15.278 +
  15.279 +	ret_val = igb_read_phy_reg_mdic(hw,
  15.280 +					  MAX_PHY_REG_ADDRESS & offset,
  15.281 +					  data);
  15.282 +
  15.283 +	igb_release_phy(hw);
  15.284 +
  15.285 +out:
  15.286 +	return ret_val;
  15.287 +}
  15.288 +
  15.289 +/**
  15.290 + *  igb_write_phy_reg_igp - Write igp PHY register
  15.291 + *  @hw: pointer to the HW structure
  15.292 + *  @offset: register offset to write to
  15.293 + *  @data: data to write at register offset
  15.294 + *
  15.295 + *  Acquires semaphore, if necessary, then writes the data to PHY register
  15.296 + *  at the offset.  Release any acquired semaphores before exiting.
  15.297 + **/
  15.298 +s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
  15.299 +{
  15.300 +	s32 ret_val;
  15.301 +
  15.302 +	ret_val = igb_acquire_phy(hw);
  15.303 +	if (ret_val)
  15.304 +		goto out;
  15.305 +
  15.306 +	if (offset > MAX_PHY_MULTI_PAGE_REG) {
  15.307 +		ret_val = igb_write_phy_reg_mdic(hw,
  15.308 +						   IGP01E1000_PHY_PAGE_SELECT,
  15.309 +						   (u16)offset);
  15.310 +		if (ret_val) {
  15.311 +			igb_release_phy(hw);
  15.312 +			goto out;
  15.313 +		}
  15.314 +	}
  15.315 +
  15.316 +	ret_val = igb_write_phy_reg_mdic(hw,
  15.317 +					   MAX_PHY_REG_ADDRESS & offset,
  15.318 +					   data);
  15.319 +
  15.320 +	igb_release_phy(hw);
  15.321 +
  15.322 +out:
  15.323 +	return ret_val;
  15.324 +}
  15.325 +
  15.326 +/**
  15.327 + *  igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
  15.328 + *  @hw: pointer to the HW structure
  15.329 + *
  15.330 + *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
  15.331 + *  and downshift values are set also.
  15.332 + **/
  15.333 +s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
  15.334 +{
  15.335 +	struct e1000_phy_info *phy = &hw->phy;
  15.336 +	s32 ret_val;
  15.337 +	u16 phy_data;
  15.338 +
  15.339 +	if (phy->reset_disable) {
  15.340 +		ret_val = 0;
  15.341 +		goto out;
  15.342 +	}
  15.343 +
  15.344 +	/* Enable CRS on TX. This must be set for half-duplex operation. */
  15.345 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  15.346 +					   &phy_data);
  15.347 +	if (ret_val)
  15.348 +		goto out;
  15.349 +
  15.350 +	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  15.351 +
  15.352 +	/*
  15.353 +	 * Options:
  15.354 +	 *   MDI/MDI-X = 0 (default)
  15.355 +	 *   0 - Auto for all speeds
  15.356 +	 *   1 - MDI mode
  15.357 +	 *   2 - MDI-X mode
  15.358 +	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  15.359 +	 */
  15.360 +	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  15.361 +
  15.362 +	switch (phy->mdix) {
  15.363 +	case 1:
  15.364 +		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  15.365 +		break;
  15.366 +	case 2:
  15.367 +		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  15.368 +		break;
  15.369 +	case 3:
  15.370 +		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  15.371 +		break;
  15.372 +	case 0:
  15.373 +	default:
  15.374 +		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  15.375 +		break;
  15.376 +	}
  15.377 +
  15.378 +	/*
  15.379 +	 * Options:
  15.380 +	 *   disable_polarity_correction = 0 (default)
  15.381 +	 *       Automatic Correction for Reversed Cable Polarity
  15.382 +	 *   0 - Disabled
  15.383 +	 *   1 - Enabled
  15.384 +	 */
  15.385 +	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  15.386 +	if (phy->disable_polarity_correction == 1)
  15.387 +		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
  15.388 +
  15.389 +	ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  15.390 +					    phy_data);
  15.391 +	if (ret_val)
  15.392 +		goto out;
  15.393 +
  15.394 +	if (phy->revision < E1000_REVISION_4) {
  15.395 +		/*
  15.396 +		 * Force TX_CLK in the Extended PHY Specific Control Register
  15.397 +		 * to 25MHz clock.
  15.398 +		 */
  15.399 +		ret_val = hw->phy.ops.read_phy_reg(hw,
  15.400 +					     M88E1000_EXT_PHY_SPEC_CTRL,
  15.401 +					     &phy_data);
  15.402 +		if (ret_val)
  15.403 +			goto out;
  15.404 +
  15.405 +		phy_data |= M88E1000_EPSCR_TX_CLK_25;
  15.406 +
  15.407 +		if ((phy->revision == E1000_REVISION_2) &&
  15.408 +		    (phy->id == M88E1111_I_PHY_ID)) {
  15.409 +			/* 82573L PHY - set the downshift counter to 5x. */
  15.410 +			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
  15.411 +			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  15.412 +		} else {
  15.413 +			/* Configure Master and Slave downshift values */
  15.414 +			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
  15.415 +				      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  15.416 +			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
  15.417 +				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  15.418 +		}
  15.419 +		ret_val = hw->phy.ops.write_phy_reg(hw,
  15.420 +					     M88E1000_EXT_PHY_SPEC_CTRL,
  15.421 +					     phy_data);
  15.422 +		if (ret_val)
  15.423 +			goto out;
  15.424 +	}
  15.425 +
  15.426 +	/* Commit the changes. */
  15.427 +	ret_val = igb_phy_sw_reset(hw);
  15.428 +	if (ret_val) {
  15.429 +		hw_dbg("Error committing the PHY changes\n");
  15.430 +		goto out;
  15.431 +	}
  15.432 +
  15.433 +out:
  15.434 +	return ret_val;
  15.435 +}
  15.436 +
  15.437 +/**
  15.438 + *  igb_copper_link_setup_igp - Setup igp PHY's for copper link
  15.439 + *  @hw: pointer to the HW structure
  15.440 + *
  15.441 + *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
  15.442 + *  igp PHY's.
  15.443 + **/
  15.444 +s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
  15.445 +{
  15.446 +	struct e1000_phy_info *phy = &hw->phy;
  15.447 +	s32 ret_val;
  15.448 +	u16 data;
  15.449 +
  15.450 +	if (phy->reset_disable) {
  15.451 +		ret_val = 0;
  15.452 +		goto out;
  15.453 +	}
  15.454 +
  15.455 +	ret_val = hw->phy.ops.reset_phy(hw);
  15.456 +	if (ret_val) {
  15.457 +		hw_dbg("Error resetting the PHY.\n");
  15.458 +		goto out;
  15.459 +	}
  15.460 +
  15.461 +	/* Wait 15ms for MAC to configure PHY from NVM settings. */
  15.462 +	msleep(15);
  15.463 +
  15.464 +	/*
  15.465 +	 * The NVM settings will configure LPLU in D3 for
  15.466 +	 * non-IGP1 PHYs.
  15.467 +	 */
  15.468 +	if (phy->type == e1000_phy_igp) {
  15.469 +		/* disable lplu d3 during driver init */
  15.470 +		if (hw->phy.ops.set_d3_lplu_state)
  15.471 +			ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
  15.472 +		if (ret_val) {
  15.473 +			hw_dbg("Error Disabling LPLU D3\n");
  15.474 +			goto out;
  15.475 +		}
  15.476 +	}
  15.477 +
  15.478 +	/* disable lplu d0 during driver init */
  15.479 +	ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
  15.480 +	if (ret_val) {
  15.481 +		hw_dbg("Error Disabling LPLU D0\n");
  15.482 +		goto out;
  15.483 +	}
  15.484 +	/* Configure mdi-mdix settings */
  15.485 +	ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
  15.486 +	if (ret_val)
  15.487 +		goto out;
  15.488 +
  15.489 +	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  15.490 +
  15.491 +	switch (phy->mdix) {
  15.492 +	case 1:
  15.493 +		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  15.494 +		break;
  15.495 +	case 2:
  15.496 +		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  15.497 +		break;
  15.498 +	case 0:
  15.499 +	default:
  15.500 +		data |= IGP01E1000_PSCR_AUTO_MDIX;
  15.501 +		break;
  15.502 +	}
  15.503 +	ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
  15.504 +	if (ret_val)
  15.505 +		goto out;
  15.506 +
  15.507 +	/* set auto-master slave resolution settings */
  15.508 +	if (hw->mac.autoneg) {
  15.509 +		/*
  15.510 +		 * when autonegotiation advertisement is only 1000Mbps then we
  15.511 +		 * should disable SmartSpeed and enable Auto MasterSlave
  15.512 +		 * resolution as hardware default.
  15.513 +		 */
  15.514 +		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
  15.515 +			/* Disable SmartSpeed */
  15.516 +			ret_val = hw->phy.ops.read_phy_reg(hw,
  15.517 +						     IGP01E1000_PHY_PORT_CONFIG,
  15.518 +						     &data);
  15.519 +			if (ret_val)
  15.520 +				goto out;
  15.521 +
  15.522 +			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  15.523 +			ret_val = hw->phy.ops.write_phy_reg(hw,
  15.524 +						     IGP01E1000_PHY_PORT_CONFIG,
  15.525 +						     data);
  15.526 +			if (ret_val)
  15.527 +				goto out;
  15.528 +
  15.529 +			/* Set auto Master/Slave resolution process */
  15.530 +			ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL,
  15.531 +							   &data);
  15.532 +			if (ret_val)
  15.533 +				goto out;
  15.534 +
  15.535 +			data &= ~CR_1000T_MS_ENABLE;
  15.536 +			ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL,
  15.537 +							    data);
  15.538 +			if (ret_val)
  15.539 +				goto out;
  15.540 +		}
  15.541 +
  15.542 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL, &data);
  15.543 +		if (ret_val)
  15.544 +			goto out;
  15.545 +
  15.546 +		/* load defaults for future use */
  15.547 +		phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
  15.548 +			((data & CR_1000T_MS_VALUE) ?
  15.549 +			e1000_ms_force_master :
  15.550 +			e1000_ms_force_slave) :
  15.551 +			e1000_ms_auto;
  15.552 +
  15.553 +		switch (phy->ms_type) {
  15.554 +		case e1000_ms_force_master:
  15.555 +			data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  15.556 +			break;
  15.557 +		case e1000_ms_force_slave:
  15.558 +			data |= CR_1000T_MS_ENABLE;
  15.559 +			data &= ~(CR_1000T_MS_VALUE);
  15.560 +			break;
  15.561 +		case e1000_ms_auto:
  15.562 +			data &= ~CR_1000T_MS_ENABLE;
  15.563 +		default:
  15.564 +			break;
  15.565 +		}
  15.566 +		ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL, data);
  15.567 +		if (ret_val)
  15.568 +			goto out;
  15.569 +	}
  15.570 +
  15.571 +out:
  15.572 +	return ret_val;
  15.573 +}
  15.574 +
  15.575 +/**
  15.576 + *  igb_copper_link_autoneg - Setup/Enable autoneg for copper link
  15.577 + *  @hw: pointer to the HW structure
  15.578 + *
  15.579 + *  Performs initial bounds checking on autoneg advertisement parameter, then
  15.580 + *  configure to advertise the full capability.  Setup the PHY to autoneg
  15.581 + *  and restart the negotiation process between the link partner.  If
  15.582 + *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
  15.583 + **/
  15.584 +s32 igb_copper_link_autoneg(struct e1000_hw *hw)
  15.585 +{
  15.586 +	struct e1000_phy_info *phy = &hw->phy;
  15.587 +	s32 ret_val;
  15.588 +	u16 phy_ctrl;
  15.589 +
  15.590 +	/*
  15.591 +	 * Perform some bounds checking on the autoneg advertisement
  15.592 +	 * parameter.
  15.593 +	 */
  15.594 +	phy->autoneg_advertised &= phy->autoneg_mask;
  15.595 +
  15.596 +	/*
  15.597 +	 * If autoneg_advertised is zero, we assume it was not defaulted
  15.598 +	 * by the calling code so we set to advertise full capability.
  15.599 +	 */
  15.600 +	if (phy->autoneg_advertised == 0)
  15.601 +		phy->autoneg_advertised = phy->autoneg_mask;
  15.602 +
  15.603 +	hw_dbg("Reconfiguring auto-neg advertisement params\n");
  15.604 +	ret_val = igb_phy_setup_autoneg(hw);
  15.605 +	if (ret_val) {
  15.606 +		hw_dbg("Error Setting up Auto-Negotiation\n");
  15.607 +		goto out;
  15.608 +	}
  15.609 +	hw_dbg("Restarting Auto-Neg\n");
  15.610 +
  15.611 +	/*
  15.612 +	 * Restart auto-negotiation by setting the Auto Neg Enable bit and
  15.613 +	 * the Auto Neg Restart bit in the PHY control register.
  15.614 +	 */
  15.615 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
  15.616 +	if (ret_val)
  15.617 +		goto out;
  15.618 +
  15.619 +	phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  15.620 +	ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
  15.621 +	if (ret_val)
  15.622 +		goto out;
  15.623 +
  15.624 +	/*
  15.625 +	 * Does the user want to wait for Auto-Neg to complete here, or
  15.626 +	 * check at a later time (for example, callback routine).
  15.627 +	 */
  15.628 +	if (phy->autoneg_wait_to_complete) {
  15.629 +		ret_val = igb_wait_autoneg(hw);
  15.630 +		if (ret_val) {
  15.631 +			hw_dbg("Error while waiting for "
  15.632 +			       "autoneg to complete\n");
  15.633 +			goto out;
  15.634 +		}
  15.635 +	}
  15.636 +
  15.637 +	hw->mac.get_link_status = true;
  15.638 +
  15.639 +out:
  15.640 +	return ret_val;
  15.641 +}
  15.642 +
  15.643 +/**
  15.644 + *  igb_phy_setup_autoneg - Configure PHY for auto-negotiation
  15.645 + *  @hw: pointer to the HW structure
  15.646 + *
  15.647 + *  Reads the MII auto-neg advertisement register and/or the 1000T control
  15.648 + *  register and if the PHY is already setup for auto-negotiation, then
  15.649 + *  return successful.  Otherwise, setup advertisement and flow control to
  15.650 + *  the appropriate values for the wanted auto-negotiation.
  15.651 + **/
  15.652 +static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
  15.653 +{
  15.654 +	struct e1000_phy_info *phy = &hw->phy;
  15.655 +	s32 ret_val;
  15.656 +	u16 mii_autoneg_adv_reg;
  15.657 +	u16 mii_1000t_ctrl_reg = 0;
  15.658 +
  15.659 +	phy->autoneg_advertised &= phy->autoneg_mask;
  15.660 +
  15.661 +	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
  15.662 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV,
  15.663 +					   &mii_autoneg_adv_reg);
  15.664 +	if (ret_val)
  15.665 +		goto out;
  15.666 +
  15.667 +	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
  15.668 +		/* Read the MII 1000Base-T Control Register (Address 9). */
  15.669 +		ret_val = hw->phy.ops.read_phy_reg(hw,
  15.670 +					    PHY_1000T_CTRL,
  15.671 +					    &mii_1000t_ctrl_reg);
  15.672 +		if (ret_val)
  15.673 +			goto out;
  15.674 +	}
  15.675 +
  15.676 +	/*
  15.677 +	 * Need to parse both autoneg_advertised and fc and set up
  15.678 +	 * the appropriate PHY registers.  First we will parse for
  15.679 +	 * autoneg_advertised software override.  Since we can advertise
  15.680 +	 * a plethora of combinations, we need to check each bit
  15.681 +	 * individually.
  15.682 +	 */
  15.683 +
  15.684 +	/*
  15.685 +	 * First we clear all the 10/100 mb speed bits in the Auto-Neg
  15.686 +	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
  15.687 +	 * the  1000Base-T Control Register (Address 9).
  15.688 +	 */
  15.689 +	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
  15.690 +				 NWAY_AR_100TX_HD_CAPS |
  15.691 +				 NWAY_AR_10T_FD_CAPS   |
  15.692 +				 NWAY_AR_10T_HD_CAPS);
  15.693 +	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
  15.694 +
  15.695 +	hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
  15.696 +
  15.697 +	/* Do we want to advertise 10 Mb Half Duplex? */
  15.698 +	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
  15.699 +		hw_dbg("Advertise 10mb Half duplex\n");
  15.700 +		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  15.701 +	}
  15.702 +
  15.703 +	/* Do we want to advertise 10 Mb Full Duplex? */
  15.704 +	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
  15.705 +		hw_dbg("Advertise 10mb Full duplex\n");
  15.706 +		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  15.707 +	}
  15.708 +
  15.709 +	/* Do we want to advertise 100 Mb Half Duplex? */
  15.710 +	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
  15.711 +		hw_dbg("Advertise 100mb Half duplex\n");
  15.712 +		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  15.713 +	}
  15.714 +
  15.715 +	/* Do we want to advertise 100 Mb Full Duplex? */
  15.716 +	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
  15.717 +		hw_dbg("Advertise 100mb Full duplex\n");
  15.718 +		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  15.719 +	}
  15.720 +
  15.721 +	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  15.722 +	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
  15.723 +		hw_dbg("Advertise 1000mb Half duplex request denied!\n");
  15.724 +
  15.725 +	/* Do we want to advertise 1000 Mb Full Duplex? */
  15.726 +	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
  15.727 +		hw_dbg("Advertise 1000mb Full duplex\n");
  15.728 +		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  15.729 +	}
  15.730 +
  15.731 +	/*
  15.732 +	 * Check for a software override of the flow control settings, and
  15.733 +	 * setup the PHY advertisement registers accordingly.  If
  15.734 +	 * auto-negotiation is enabled, then software will have to set the
  15.735 +	 * "PAUSE" bits to the correct value in the Auto-Negotiation
  15.736 +	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
  15.737 +	 * negotiation.
  15.738 +	 *
  15.739 +	 * The possible values of the "fc" parameter are:
  15.740 +	 *      0:  Flow control is completely disabled
  15.741 +	 *      1:  Rx flow control is enabled (we can receive pause frames
  15.742 +	 *          but not send pause frames).
  15.743 +	 *      2:  Tx flow control is enabled (we can send pause frames
  15.744 +	 *          but we do not support receiving pause frames).
  15.745 +	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
  15.746 +	 *  other:  No software override.  The flow control configuration
  15.747 +	 *          in the EEPROM is used.
  15.748 +	 */
  15.749 +	switch (hw->fc.type) {
  15.750 +	case e1000_fc_none:
  15.751 +		/*
  15.752 +		 * Flow control (RX & TX) is completely disabled by a
  15.753 +		 * software over-ride.
  15.754 +		 */
  15.755 +		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  15.756 +		break;
  15.757 +	case e1000_fc_rx_pause:
  15.758 +		/*
  15.759 +		 * RX Flow control is enabled, and TX Flow control is
  15.760 +		 * disabled, by a software over-ride.
  15.761 +		 *
  15.762 +		 * Since there really isn't a way to advertise that we are
  15.763 +		 * capable of RX Pause ONLY, we will advertise that we
  15.764 +		 * support both symmetric and asymmetric RX PAUSE.  Later
  15.765 +		 * (in e1000_config_fc_after_link_up) we will disable the
  15.766 +		 * hw's ability to send PAUSE frames.
  15.767 +		 */
  15.768 +		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  15.769 +		break;
  15.770 +	case e1000_fc_tx_pause:
  15.771 +		/*
  15.772 +		 * TX Flow control is enabled, and RX Flow control is
  15.773 +		 * disabled, by a software over-ride.
  15.774 +		 */
  15.775 +		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  15.776 +		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  15.777 +		break;
  15.778 +	case e1000_fc_full:
  15.779 +		/*
  15.780 +		 * Flow control (both RX and TX) is enabled by a software
  15.781 +		 * over-ride.
  15.782 +		 */
  15.783 +		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  15.784 +		break;
  15.785 +	default:
  15.786 +		hw_dbg("Flow control param set incorrectly\n");
  15.787 +		ret_val = -E1000_ERR_CONFIG;
  15.788 +		goto out;
  15.789 +	}
  15.790 +
  15.791 +	ret_val = hw->phy.ops.write_phy_reg(hw, PHY_AUTONEG_ADV,
  15.792 +					    mii_autoneg_adv_reg);
  15.793 +	if (ret_val)
  15.794 +		goto out;
  15.795 +
  15.796 +	hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  15.797 +
  15.798 +	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
  15.799 +		ret_val = hw->phy.ops.write_phy_reg(hw,
  15.800 +					      PHY_1000T_CTRL,
  15.801 +					      mii_1000t_ctrl_reg);
  15.802 +		if (ret_val)
  15.803 +			goto out;
  15.804 +	}
  15.805 +
  15.806 +out:
  15.807 +	return ret_val;
  15.808 +}
  15.809 +
  15.810 +/**
  15.811 + *  igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
  15.812 + *  @hw: pointer to the HW structure
  15.813 + *
  15.814 + *  Calls the PHY setup function to force speed and duplex.  Clears the
  15.815 + *  auto-crossover to force MDI manually.  Waits for link and returns
  15.816 + *  successful if link up is successful, else -E1000_ERR_PHY (-2).
  15.817 + **/
  15.818 +s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
  15.819 +{
  15.820 +	struct e1000_phy_info *phy = &hw->phy;
  15.821 +	s32 ret_val;
  15.822 +	u16 phy_data;
  15.823 +	bool link;
  15.824 +
  15.825 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
  15.826 +	if (ret_val)
  15.827 +		goto out;
  15.828 +
  15.829 +	igb_phy_force_speed_duplex_setup(hw, &phy_data);
  15.830 +
  15.831 +	ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
  15.832 +	if (ret_val)
  15.833 +		goto out;
  15.834 +
  15.835 +	/*
  15.836 +	 * Clear Auto-Crossover to force MDI manually.  IGP requires MDI
  15.837 +	 * forced whenever speed and duplex are forced.
  15.838 +	 */
  15.839 +	ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
  15.840 +					   &phy_data);
  15.841 +	if (ret_val)
  15.842 +		goto out;
  15.843 +
  15.844 +	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  15.845 +	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  15.846 +
  15.847 +	ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
  15.848 +					    phy_data);
  15.849 +	if (ret_val)
  15.850 +		goto out;
  15.851 +
  15.852 +	hw_dbg("IGP PSCR: %X\n", phy_data);
  15.853 +
  15.854 +	udelay(1);
  15.855 +
  15.856 +	if (phy->autoneg_wait_to_complete) {
  15.857 +		hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
  15.858 +
  15.859 +		ret_val = igb_phy_has_link(hw,
  15.860 +						     PHY_FORCE_LIMIT,
  15.861 +						     100000,
  15.862 +						     &link);
  15.863 +		if (ret_val)
  15.864 +			goto out;
  15.865 +
  15.866 +		if (!link)
  15.867 +			hw_dbg("Link taking longer than expected.\n");
  15.868 +
  15.869 +		/* Try once more */
  15.870 +		ret_val = igb_phy_has_link(hw,
  15.871 +						     PHY_FORCE_LIMIT,
  15.872 +						     100000,
  15.873 +						     &link);
  15.874 +		if (ret_val)
  15.875 +			goto out;
  15.876 +	}
  15.877 +
  15.878 +out:
  15.879 +	return ret_val;
  15.880 +}
  15.881 +
  15.882 +/**
  15.883 + *  igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
  15.884 + *  @hw: pointer to the HW structure
  15.885 + *
  15.886 + *  Calls the PHY setup function to force speed and duplex.  Clears the
  15.887 + *  auto-crossover to force MDI manually.  Resets the PHY to commit the
  15.888 + *  changes.  If time expires while waiting for link up, we reset the DSP.
  15.889 + *  After reset, TX_CLK and CRS on TX must be set.  Return successful upon
  15.890 + *  successful completion, else return corresponding error code.
  15.891 + **/
  15.892 +s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
  15.893 +{
  15.894 +	struct e1000_phy_info *phy = &hw->phy;
  15.895 +	s32 ret_val;
  15.896 +	u16 phy_data;
  15.897 +	bool link;
  15.898 +
  15.899 +	/*
  15.900 +	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
  15.901 +	 * forced whenever speed and duplex are forced.
  15.902 +	 */
  15.903 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  15.904 +					   &phy_data);
  15.905 +	if (ret_val)
  15.906 +		goto out;
  15.907 +
  15.908 +	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  15.909 +	ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  15.910 +					    phy_data);
  15.911 +	if (ret_val)
  15.912 +		goto out;
  15.913 +
  15.914 +	hw_dbg("M88E1000 PSCR: %X\n", phy_data);
  15.915 +
  15.916 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
  15.917 +	if (ret_val)
  15.918 +		goto out;
  15.919 +
  15.920 +	igb_phy_force_speed_duplex_setup(hw, &phy_data);
  15.921 +
  15.922 +	/* Reset the phy to commit changes. */
  15.923 +	phy_data |= MII_CR_RESET;
  15.924 +
  15.925 +	ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
  15.926 +	if (ret_val)
  15.927 +		goto out;
  15.928 +
  15.929 +	udelay(1);
  15.930 +
  15.931 +	if (phy->autoneg_wait_to_complete) {
  15.932 +		hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
  15.933 +
  15.934 +		ret_val = igb_phy_has_link(hw,
  15.935 +						     PHY_FORCE_LIMIT,
  15.936 +						     100000,
  15.937 +						     &link);
  15.938 +		if (ret_val)
  15.939 +			goto out;
  15.940 +
  15.941 +		if (!link) {
  15.942 +			/*
  15.943 +			 * We didn't get link.
  15.944 +			 * Reset the DSP and cross our fingers.
  15.945 +			 */
  15.946 +			ret_val = hw->phy.ops.write_phy_reg(hw,
  15.947 +						      M88E1000_PHY_PAGE_SELECT,
  15.948 +						      0x001d);
  15.949 +			if (ret_val)
  15.950 +				goto out;
  15.951 +			ret_val = igb_phy_reset_dsp(hw);
  15.952 +			if (ret_val)
  15.953 +				goto out;
  15.954 +		}
  15.955 +
  15.956 +		/* Try once more */
  15.957 +		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
  15.958 +					     100000, &link);
  15.959 +		if (ret_val)
  15.960 +			goto out;
  15.961 +	}
  15.962 +
  15.963 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  15.964 +					   &phy_data);
  15.965 +	if (ret_val)
  15.966 +		goto out;
  15.967 +
  15.968 +	/*
  15.969 +	 * Resetting the phy means we need to re-force TX_CLK in the
  15.970 +	 * Extended PHY Specific Control Register to 25MHz clock from
  15.971 +	 * the reset value of 2.5MHz.
  15.972 +	 */
  15.973 +	phy_data |= M88E1000_EPSCR_TX_CLK_25;
  15.974 +	ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  15.975 +					    phy_data);
  15.976 +	if (ret_val)
  15.977 +		goto out;
  15.978 +
  15.979 +	/*
  15.980 +	 * In addition, we must re-enable CRS on Tx for both half and full
  15.981 +	 * duplex.
  15.982 +	 */
  15.983 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  15.984 +					   &phy_data);
  15.985 +	if (ret_val)
  15.986 +		goto out;
  15.987 +
  15.988 +	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  15.989 +	ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  15.990 +					    phy_data);
  15.991 +
  15.992 +out:
  15.993 +	return ret_val;
  15.994 +}
  15.995 +
  15.996 +/**
  15.997 + *  igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
  15.998 + *  @hw: pointer to the HW structure
  15.999 + *  @phy_ctrl: pointer to current value of PHY_CONTROL
 15.1000 + *
 15.1001 + *  Forces speed and duplex on the PHY by doing the following: disable flow
 15.1002 + *  control, force speed/duplex on the MAC, disable auto speed detection,
 15.1003 + *  disable auto-negotiation, configure duplex, configure speed, configure
 15.1004 + *  the collision distance, write configuration to CTRL register.  The
 15.1005 + *  caller must write to the PHY_CONTROL register for these settings to
 15.1006 + *  take affect.
 15.1007 + **/
 15.1008 +static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
 15.1009 +					       u16 *phy_ctrl)
 15.1010 +{
 15.1011 +	struct e1000_mac_info *mac = &hw->mac;
 15.1012 +	u32 ctrl;
 15.1013 +
 15.1014 +	/* Turn off flow control when forcing speed/duplex */
 15.1015 +	hw->fc.type = e1000_fc_none;
 15.1016 +
 15.1017 +	/* Force speed/duplex on the mac */
 15.1018 +	ctrl = rd32(E1000_CTRL);
 15.1019 +	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 15.1020 +	ctrl &= ~E1000_CTRL_SPD_SEL;
 15.1021 +
 15.1022 +	/* Disable Auto Speed Detection */
 15.1023 +	ctrl &= ~E1000_CTRL_ASDE;
 15.1024 +
 15.1025 +	/* Disable autoneg on the phy */
 15.1026 +	*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
 15.1027 +
 15.1028 +	/* Forcing Full or Half Duplex? */
 15.1029 +	if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
 15.1030 +		ctrl &= ~E1000_CTRL_FD;
 15.1031 +		*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
 15.1032 +		hw_dbg("Half Duplex\n");
 15.1033 +	} else {
 15.1034 +		ctrl |= E1000_CTRL_FD;
 15.1035 +		*phy_ctrl |= MII_CR_FULL_DUPLEX;
 15.1036 +		hw_dbg("Full Duplex\n");
 15.1037 +	}
 15.1038 +
 15.1039 +	/* Forcing 10mb or 100mb? */
 15.1040 +	if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
 15.1041 +		ctrl |= E1000_CTRL_SPD_100;
 15.1042 +		*phy_ctrl |= MII_CR_SPEED_100;
 15.1043 +		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
 15.1044 +		hw_dbg("Forcing 100mb\n");
 15.1045 +	} else {
 15.1046 +		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
 15.1047 +		*phy_ctrl |= MII_CR_SPEED_10;
 15.1048 +		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
 15.1049 +		hw_dbg("Forcing 10mb\n");
 15.1050 +	}
 15.1051 +
 15.1052 +	igb_config_collision_dist(hw);
 15.1053 +
 15.1054 +	wr32(E1000_CTRL, ctrl);
 15.1055 +}
 15.1056 +
 15.1057 +/**
 15.1058 + *  igb_set_d3_lplu_state - Sets low power link up state for D3
 15.1059 + *  @hw: pointer to the HW structure
 15.1060 + *  @active: boolean used to enable/disable lplu
 15.1061 + *
 15.1062 + *  Success returns 0, Failure returns 1
 15.1063 + *
 15.1064 + *  The low power link up (lplu) state is set to the power management level D3
 15.1065 + *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 15.1066 + *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 15.1067 + *  is used during Dx states where the power conservation is most important.
 15.1068 + *  During driver activity, SmartSpeed should be enabled so performance is
 15.1069 + *  maintained.
 15.1070 + **/
 15.1071 +s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
 15.1072 +{
 15.1073 +	struct e1000_phy_info *phy = &hw->phy;
 15.1074 +	s32 ret_val;
 15.1075 +	u16 data;
 15.1076 +
 15.1077 +	ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 15.1078 +					   &data);
 15.1079 +	if (ret_val)
 15.1080 +		goto out;
 15.1081 +
 15.1082 +	if (!active) {
 15.1083 +		data &= ~IGP02E1000_PM_D3_LPLU;
 15.1084 +		ret_val = hw->phy.ops.write_phy_reg(hw,
 15.1085 +					     IGP02E1000_PHY_POWER_MGMT,
 15.1086 +					     data);
 15.1087 +		if (ret_val)
 15.1088 +			goto out;
 15.1089 +		/*
 15.1090 +		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 15.1091 +		 * during Dx states where the power conservation is most
 15.1092 +		 * important.  During driver activity we should enable
 15.1093 +		 * SmartSpeed, so performance is maintained.
 15.1094 +		 */
 15.1095 +		if (phy->smart_speed == e1000_smart_speed_on) {
 15.1096 +			ret_val = hw->phy.ops.read_phy_reg(hw,
 15.1097 +						    IGP01E1000_PHY_PORT_CONFIG,
 15.1098 +						    &data);
 15.1099 +			if (ret_val)
 15.1100 +				goto out;
 15.1101 +
 15.1102 +			data |= IGP01E1000_PSCFR_SMART_SPEED;
 15.1103 +			ret_val = hw->phy.ops.write_phy_reg(hw,
 15.1104 +						     IGP01E1000_PHY_PORT_CONFIG,
 15.1105 +						     data);
 15.1106 +			if (ret_val)
 15.1107 +				goto out;
 15.1108 +		} else if (phy->smart_speed == e1000_smart_speed_off) {
 15.1109 +			ret_val = hw->phy.ops.read_phy_reg(hw,
 15.1110 +						     IGP01E1000_PHY_PORT_CONFIG,
 15.1111 +						     &data);
 15.1112 +			if (ret_val)
 15.1113 +				goto out;
 15.1114 +
 15.1115 +			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 15.1116 +			ret_val = hw->phy.ops.write_phy_reg(hw,
 15.1117 +						     IGP01E1000_PHY_PORT_CONFIG,
 15.1118 +						     data);
 15.1119 +			if (ret_val)
 15.1120 +				goto out;
 15.1121 +		}
 15.1122 +	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 15.1123 +		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 15.1124 +		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 15.1125 +		data |= IGP02E1000_PM_D3_LPLU;
 15.1126 +		ret_val = hw->phy.ops.write_phy_reg(hw,
 15.1127 +					      IGP02E1000_PHY_POWER_MGMT,
 15.1128 +					      data);
 15.1129 +		if (ret_val)
 15.1130 +			goto out;
 15.1131 +
 15.1132 +		/* When LPLU is enabled, we should disable SmartSpeed */
 15.1133 +		ret_val = hw->phy.ops.read_phy_reg(hw,
 15.1134 +					     IGP01E1000_PHY_PORT_CONFIG,
 15.1135 +					     &data);
 15.1136 +		if (ret_val)
 15.1137 +			goto out;
 15.1138 +
 15.1139 +		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 15.1140 +		ret_val = hw->phy.ops.write_phy_reg(hw,
 15.1141 +					      IGP01E1000_PHY_PORT_CONFIG,
 15.1142 +					      data);
 15.1143 +	}
 15.1144 +
 15.1145 +out:
 15.1146 +	return ret_val;
 15.1147 +}
 15.1148 +
 15.1149 +/**
 15.1150 + *  igb_check_downshift - Checks whether a downshift in speed occured
 15.1151 + *  @hw: pointer to the HW structure
 15.1152 + *
 15.1153 + *  Success returns 0, Failure returns 1
 15.1154 + *
 15.1155 + *  A downshift is detected by querying the PHY link health.
 15.1156 + **/
 15.1157 +s32 igb_check_downshift(struct e1000_hw *hw)
 15.1158 +{
 15.1159 +	struct e1000_phy_info *phy = &hw->phy;
 15.1160 +	s32 ret_val;
 15.1161 +	u16 phy_data, offset, mask;
 15.1162 +
 15.1163 +	switch (phy->type) {
 15.1164 +	case e1000_phy_m88:
 15.1165 +	case e1000_phy_gg82563:
 15.1166 +		offset	= M88E1000_PHY_SPEC_STATUS;
 15.1167 +		mask	= M88E1000_PSSR_DOWNSHIFT;
 15.1168 +		break;
 15.1169 +	case e1000_phy_igp_2:
 15.1170 +	case e1000_phy_igp:
 15.1171 +	case e1000_phy_igp_3:
 15.1172 +		offset	= IGP01E1000_PHY_LINK_HEALTH;
 15.1173 +		mask	= IGP01E1000_PLHR_SS_DOWNGRADE;
 15.1174 +		break;
 15.1175 +	default:
 15.1176 +		/* speed downshift not supported */
 15.1177 +		phy->speed_downgraded = false;
 15.1178 +		ret_val = 0;
 15.1179 +		goto out;
 15.1180 +	}
 15.1181 +
 15.1182 +	ret_val = hw->phy.ops.read_phy_reg(hw, offset, &phy_data);
 15.1183 +
 15.1184 +	if (!ret_val)
 15.1185 +		phy->speed_downgraded = (phy_data & mask) ? true : false;
 15.1186 +
 15.1187 +out:
 15.1188 +	return ret_val;
 15.1189 +}
 15.1190 +
 15.1191 +/**
 15.1192 + *  igb_check_polarity_m88 - Checks the polarity.
 15.1193 + *  @hw: pointer to the HW structure
 15.1194 + *
 15.1195 + *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
 15.1196 + *
 15.1197 + *  Polarity is determined based on the PHY specific status register.
 15.1198 + **/
 15.1199 +static s32 igb_check_polarity_m88(struct e1000_hw *hw)
 15.1200 +{
 15.1201 +	struct e1000_phy_info *phy = &hw->phy;
 15.1202 +	s32 ret_val;
 15.1203 +	u16 data;
 15.1204 +
 15.1205 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
 15.1206 +
 15.1207 +	if (!ret_val)
 15.1208 +		phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
 15.1209 +				      ? e1000_rev_polarity_reversed
 15.1210 +				      : e1000_rev_polarity_normal;
 15.1211 +
 15.1212 +	return ret_val;
 15.1213 +}
 15.1214 +
 15.1215 +/**
 15.1216 + *  igb_check_polarity_igp - Checks the polarity.
 15.1217 + *  @hw: pointer to the HW structure
 15.1218 + *
 15.1219 + *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
 15.1220 + *
 15.1221 + *  Polarity is determined based on the PHY port status register, and the
 15.1222 + *  current speed (since there is no polarity at 100Mbps).
 15.1223 + **/
 15.1224 +static s32 igb_check_polarity_igp(struct e1000_hw *hw)
 15.1225 +{
 15.1226 +	struct e1000_phy_info *phy = &hw->phy;
 15.1227 +	s32 ret_val;
 15.1228 +	u16 data, offset, mask;
 15.1229 +
 15.1230 +	/*
 15.1231 +	 * Polarity is determined based on the speed of
 15.1232 +	 * our connection.
 15.1233 +	 */
 15.1234 +	ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
 15.1235 +					   &data);
 15.1236 +	if (ret_val)
 15.1237 +		goto out;
 15.1238 +
 15.1239 +	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
 15.1240 +	    IGP01E1000_PSSR_SPEED_1000MBPS) {
 15.1241 +		offset	= IGP01E1000_PHY_PCS_INIT_REG;
 15.1242 +		mask	= IGP01E1000_PHY_POLARITY_MASK;
 15.1243 +	} else {
 15.1244 +		/*
 15.1245 +		 * This really only applies to 10Mbps since
 15.1246 +		 * there is no polarity for 100Mbps (always 0).
 15.1247 +		 */
 15.1248 +		offset	= IGP01E1000_PHY_PORT_STATUS;
 15.1249 +		mask	= IGP01E1000_PSSR_POLARITY_REVERSED;
 15.1250 +	}
 15.1251 +
 15.1252 +	ret_val = hw->phy.ops.read_phy_reg(hw, offset, &data);
 15.1253 +
 15.1254 +	if (!ret_val)
 15.1255 +		phy->cable_polarity = (data & mask)
 15.1256 +				      ? e1000_rev_polarity_reversed
 15.1257 +				      : e1000_rev_polarity_normal;
 15.1258 +
 15.1259 +out:
 15.1260 +	return ret_val;
 15.1261 +}
 15.1262 +
 15.1263 +/**
 15.1264 + *  igb_wait_autoneg - Wait for auto-neg compeletion
 15.1265 + *  @hw: pointer to the HW structure
 15.1266 + *
 15.1267 + *  Waits for auto-negotiation to complete or for the auto-negotiation time
 15.1268 + *  limit to expire, which ever happens first.
 15.1269 + **/
 15.1270 +static s32 igb_wait_autoneg(struct e1000_hw *hw)
 15.1271 +{
 15.1272 +	s32 ret_val = 0;
 15.1273 +	u16 i, phy_status;
 15.1274 +
 15.1275 +	/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
 15.1276 +	for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
 15.1277 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
 15.1278 +		if (ret_val)
 15.1279 +			break;
 15.1280 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
 15.1281 +		if (ret_val)
 15.1282 +			break;
 15.1283 +		if (phy_status & MII_SR_AUTONEG_COMPLETE)
 15.1284 +			break;
 15.1285 +		msleep(100);
 15.1286 +	}
 15.1287 +
 15.1288 +	/*
 15.1289 +	 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
 15.1290 +	 * has completed.
 15.1291 +	 */
 15.1292 +	return ret_val;
 15.1293 +}
 15.1294 +
 15.1295 +/**
 15.1296 + *  igb_phy_has_link - Polls PHY for link
 15.1297 + *  @hw: pointer to the HW structure
 15.1298 + *  @iterations: number of times to poll for link
 15.1299 + *  @usec_interval: delay between polling attempts
 15.1300 + *  @success: pointer to whether polling was successful or not
 15.1301 + *
 15.1302 + *  Polls the PHY status register for link, 'iterations' number of times.
 15.1303 + **/
 15.1304 +s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
 15.1305 +			       u32 usec_interval, bool *success)
 15.1306 +{
 15.1307 +	s32 ret_val = 0;
 15.1308 +	u16 i, phy_status;
 15.1309 +
 15.1310 +	for (i = 0; i < iterations; i++) {
 15.1311 +		/*
 15.1312 +		 * Some PHYs require the PHY_STATUS register to be read
 15.1313 +		 * twice due to the link bit being sticky.  No harm doing
 15.1314 +		 * it across the board.
 15.1315 +		 */
 15.1316 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
 15.1317 +		if (ret_val)
 15.1318 +			break;
 15.1319 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
 15.1320 +		if (ret_val)
 15.1321 +			break;
 15.1322 +		if (phy_status & MII_SR_LINK_STATUS)
 15.1323 +			break;
 15.1324 +		if (usec_interval >= 1000)
 15.1325 +			mdelay(usec_interval/1000);
 15.1326 +		else
 15.1327 +			udelay(usec_interval);
 15.1328 +	}
 15.1329 +
 15.1330 +	*success = (i < iterations) ? true : false;
 15.1331 +
 15.1332 +	return ret_val;
 15.1333 +}
 15.1334 +
 15.1335 +/**
 15.1336 + *  igb_get_cable_length_m88 - Determine cable length for m88 PHY
 15.1337 + *  @hw: pointer to the HW structure
 15.1338 + *
 15.1339 + *  Reads the PHY specific status register to retrieve the cable length
 15.1340 + *  information.  The cable length is determined by averaging the minimum and
 15.1341 + *  maximum values to get the "average" cable length.  The m88 PHY has four
 15.1342 + *  possible cable length values, which are:
 15.1343 + *	Register Value		Cable Length
 15.1344 + *	0			< 50 meters
 15.1345 + *	1			50 - 80 meters
 15.1346 + *	2			80 - 110 meters
 15.1347 + *	3			110 - 140 meters
 15.1348 + *	4			> 140 meters
 15.1349 + **/
 15.1350 +s32 igb_get_cable_length_m88(struct e1000_hw *hw)
 15.1351 +{
 15.1352 +	struct e1000_phy_info *phy = &hw->phy;
 15.1353 +	s32 ret_val;
 15.1354 +	u16 phy_data, index;
 15.1355 +
 15.1356 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
 15.1357 +					   &phy_data);
 15.1358 +	if (ret_val)
 15.1359 +		goto out;
 15.1360 +
 15.1361 +	index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
 15.1362 +		M88E1000_PSSR_CABLE_LENGTH_SHIFT;
 15.1363 +	phy->min_cable_length = e1000_m88_cable_length_table[index];
 15.1364 +	phy->max_cable_length = e1000_m88_cable_length_table[index+1];
 15.1365 +
 15.1366 +	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 15.1367 +
 15.1368 +out:
 15.1369 +	return ret_val;
 15.1370 +}
 15.1371 +
 15.1372 +/**
 15.1373 + *  igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
 15.1374 + *  @hw: pointer to the HW structure
 15.1375 + *
 15.1376 + *  The automatic gain control (agc) normalizes the amplitude of the
 15.1377 + *  received signal, adjusting for the attenuation produced by the
 15.1378 + *  cable.  By reading the AGC registers, which reperesent the
 15.1379 + *  cobination of course and fine gain value, the value can be put
 15.1380 + *  into a lookup table to obtain the approximate cable length
 15.1381 + *  for each channel.
 15.1382 + **/
 15.1383 +s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
 15.1384 +{
 15.1385 +	struct e1000_phy_info *phy = &hw->phy;
 15.1386 +	s32 ret_val = 0;
 15.1387 +	u16 phy_data, i, agc_value = 0;
 15.1388 +	u16 cur_agc_index, max_agc_index = 0;
 15.1389 +	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
 15.1390 +	u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
 15.1391 +							 {IGP02E1000_PHY_AGC_A,
 15.1392 +							  IGP02E1000_PHY_AGC_B,
 15.1393 +							  IGP02E1000_PHY_AGC_C,
 15.1394 +							  IGP02E1000_PHY_AGC_D};
 15.1395 +
 15.1396 +	/* Read the AGC registers for all channels */
 15.1397 +	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
 15.1398 +		ret_val = hw->phy.ops.read_phy_reg(hw, agc_reg_array[i],
 15.1399 +						   &phy_data);
 15.1400 +		if (ret_val)
 15.1401 +			goto out;
 15.1402 +
 15.1403 +		/*
 15.1404 +		 * Getting bits 15:9, which represent the combination of
 15.1405 +		 * course and fine gain values.  The result is a number
 15.1406 +		 * that can be put into the lookup table to obtain the
 15.1407 +		 * approximate cable length.
 15.1408 +		 */
 15.1409 +		cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
 15.1410 +				IGP02E1000_AGC_LENGTH_MASK;
 15.1411 +
 15.1412 +		/* Array index bound check. */
 15.1413 +		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
 15.1414 +		    (cur_agc_index == 0)) {
 15.1415 +			ret_val = -E1000_ERR_PHY;
 15.1416 +			goto out;
 15.1417 +		}
 15.1418 +
 15.1419 +		/* Remove min & max AGC values from calculation. */
 15.1420 +		if (e1000_igp_2_cable_length_table[min_agc_index] >
 15.1421 +		    e1000_igp_2_cable_length_table[cur_agc_index])
 15.1422 +			min_agc_index = cur_agc_index;
 15.1423 +		if (e1000_igp_2_cable_length_table[max_agc_index] <
 15.1424 +		    e1000_igp_2_cable_length_table[cur_agc_index])
 15.1425 +			max_agc_index = cur_agc_index;
 15.1426 +
 15.1427 +		agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
 15.1428 +	}
 15.1429 +
 15.1430 +	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
 15.1431 +		      e1000_igp_2_cable_length_table[max_agc_index]);
 15.1432 +	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
 15.1433 +
 15.1434 +	/* Calculate cable length with the error range of +/- 10 meters. */
 15.1435 +	phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
 15.1436 +				 (agc_value - IGP02E1000_AGC_RANGE) : 0;
 15.1437 +	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
 15.1438 +
 15.1439 +	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 15.1440 +
 15.1441 +out:
 15.1442 +	return ret_val;
 15.1443 +}
 15.1444 +
 15.1445 +/**
 15.1446 + *  igb_get_phy_info_m88 - Retrieve PHY information
 15.1447 + *  @hw: pointer to the HW structure
 15.1448 + *
 15.1449 + *  Valid for only copper links.  Read the PHY status register (sticky read)
 15.1450 + *  to verify that link is up.  Read the PHY special control register to
 15.1451 + *  determine the polarity and 10base-T extended distance.  Read the PHY
 15.1452 + *  special status register to determine MDI/MDIx and current speed.  If
 15.1453 + *  speed is 1000, then determine cable length, local and remote receiver.
 15.1454 + **/
 15.1455 +s32 igb_get_phy_info_m88(struct e1000_hw *hw)
 15.1456 +{
 15.1457 +	struct e1000_phy_info *phy = &hw->phy;
 15.1458 +	s32  ret_val;
 15.1459 +	u16 phy_data;
 15.1460 +	bool link;
 15.1461 +
 15.1462 +	if (hw->phy.media_type != e1000_media_type_copper) {
 15.1463 +		hw_dbg("Phy info is only valid for copper media\n");
 15.1464 +		ret_val = -E1000_ERR_CONFIG;
 15.1465 +		goto out;
 15.1466 +	}
 15.1467 +
 15.1468 +	ret_val = igb_phy_has_link(hw, 1, 0, &link);
 15.1469 +	if (ret_val)
 15.1470 +		goto out;
 15.1471 +
 15.1472 +	if (!link) {
 15.1473 +		hw_dbg("Phy info is only valid if link is up\n");
 15.1474 +		ret_val = -E1000_ERR_CONFIG;
 15.1475 +		goto out;
 15.1476 +	}
 15.1477 +
 15.1478 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
 15.1479 +					   &phy_data);
 15.1480 +	if (ret_val)
 15.1481 +		goto out;
 15.1482 +
 15.1483 +	phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
 15.1484 +				   ? true
 15.1485 +				   : false;
 15.1486 +
 15.1487 +	ret_val = igb_check_polarity_m88(hw);
 15.1488 +	if (ret_val)
 15.1489 +		goto out;
 15.1490 +
 15.1491 +	ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
 15.1492 +					   &phy_data);
 15.1493 +	if (ret_val)
 15.1494 +		goto out;
 15.1495 +
 15.1496 +	phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
 15.1497 +
 15.1498 +	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
 15.1499 +		ret_val = hw->phy.ops.get_cable_length(hw);
 15.1500 +		if (ret_val)
 15.1501 +			goto out;
 15.1502 +
 15.1503 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
 15.1504 +						   &phy_data);
 15.1505 +		if (ret_val)
 15.1506 +			goto out;
 15.1507 +
 15.1508 +		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
 15.1509 +				? e1000_1000t_rx_status_ok
 15.1510 +				: e1000_1000t_rx_status_not_ok;
 15.1511 +
 15.1512 +		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
 15.1513 +				 ? e1000_1000t_rx_status_ok
 15.1514 +				 : e1000_1000t_rx_status_not_ok;
 15.1515 +	} else {
 15.1516 +		/* Set values to "undefined" */
 15.1517 +		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 15.1518 +		phy->local_rx = e1000_1000t_rx_status_undefined;
 15.1519 +		phy->remote_rx = e1000_1000t_rx_status_undefined;
 15.1520 +	}
 15.1521 +
 15.1522 +out:
 15.1523 +	return ret_val;
 15.1524 +}
 15.1525 +
 15.1526 +/**
 15.1527 + *  igb_get_phy_info_igp - Retrieve igp PHY information
 15.1528 + *  @hw: pointer to the HW structure
 15.1529 + *
 15.1530 + *  Read PHY status to determine if link is up.  If link is up, then
 15.1531 + *  set/determine 10base-T extended distance and polarity correction.  Read
 15.1532 + *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
 15.1533 + *  determine on the cable length, local and remote receiver.
 15.1534 + **/
 15.1535 +s32 igb_get_phy_info_igp(struct e1000_hw *hw)
 15.1536 +{
 15.1537 +	struct e1000_phy_info *phy = &hw->phy;
 15.1538 +	s32 ret_val;
 15.1539 +	u16 data;
 15.1540 +	bool link;
 15.1541 +
 15.1542 +	ret_val = igb_phy_has_link(hw, 1, 0, &link);
 15.1543 +	if (ret_val)
 15.1544 +		goto out;
 15.1545 +
 15.1546 +	if (!link) {
 15.1547 +		hw_dbg("Phy info is only valid if link is up\n");
 15.1548 +		ret_val = -E1000_ERR_CONFIG;
 15.1549 +		goto out;
 15.1550 +	}
 15.1551 +
 15.1552 +	phy->polarity_correction = true;
 15.1553 +
 15.1554 +	ret_val = igb_check_polarity_igp(hw);
 15.1555 +	if (ret_val)
 15.1556 +		goto out;
 15.1557 +
 15.1558 +	ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
 15.1559 +					   &data);
 15.1560 +	if (ret_val)
 15.1561 +		goto out;
 15.1562 +
 15.1563 +	phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
 15.1564 +
 15.1565 +	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
 15.1566 +	    IGP01E1000_PSSR_SPEED_1000MBPS) {
 15.1567 +		ret_val = hw->phy.ops.get_cable_length(hw);
 15.1568 +		if (ret_val)
 15.1569 +			goto out;
 15.1570 +
 15.1571 +		ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
 15.1572 +						   &data);
 15.1573 +		if (ret_val)
 15.1574 +			goto out;
 15.1575 +
 15.1576 +		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
 15.1577 +				? e1000_1000t_rx_status_ok
 15.1578 +				: e1000_1000t_rx_status_not_ok;
 15.1579 +
 15.1580 +		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
 15.1581 +				 ? e1000_1000t_rx_status_ok
 15.1582 +				 : e1000_1000t_rx_status_not_ok;
 15.1583 +	} else {
 15.1584 +		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 15.1585 +		phy->local_rx = e1000_1000t_rx_status_undefined;
 15.1586 +		phy->remote_rx = e1000_1000t_rx_status_undefined;
 15.1587 +	}
 15.1588 +
 15.1589 +out:
 15.1590 +	return ret_val;
 15.1591 +}
 15.1592 +
 15.1593 +/**
 15.1594 + *  igb_phy_sw_reset - PHY software reset
 15.1595 + *  @hw: pointer to the HW structure
 15.1596 + *
 15.1597 + *  Does a software reset of the PHY by reading the PHY control register and
 15.1598 + *  setting/write the control register reset bit to the PHY.
 15.1599 + **/
 15.1600 +s32 igb_phy_sw_reset(struct e1000_hw *hw)
 15.1601 +{
 15.1602 +	s32 ret_val;
 15.1603 +	u16 phy_ctrl;
 15.1604 +
 15.1605 +	ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
 15.1606 +	if (ret_val)
 15.1607 +		goto out;
 15.1608 +
 15.1609 +	phy_ctrl |= MII_CR_RESET;
 15.1610 +	ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
 15.1611 +	if (ret_val)
 15.1612 +		goto out;
 15.1613 +
 15.1614 +	udelay(1);
 15.1615 +
 15.1616 +out:
 15.1617 +	return ret_val;
 15.1618 +}
 15.1619 +
 15.1620 +/**
 15.1621 + *  igb_phy_hw_reset - PHY hardware reset
 15.1622 + *  @hw: pointer to the HW structure
 15.1623 + *
 15.1624 + *  Verify the reset block is not blocking us from resetting.  Acquire
 15.1625 + *  semaphore (if necessary) and read/set/write the device control reset
 15.1626 + *  bit in the PHY.  Wait the appropriate delay time for the device to
 15.1627 + *  reset and relase the semaphore (if necessary).
 15.1628 + **/
 15.1629 +s32 igb_phy_hw_reset(struct e1000_hw *hw)
 15.1630 +{
 15.1631 +	struct e1000_phy_info *phy = &hw->phy;
 15.1632 +	s32  ret_val;
 15.1633 +	u32 ctrl;
 15.1634 +
 15.1635 +	ret_val = igb_check_reset_block(hw);
 15.1636 +	if (ret_val) {
 15.1637 +		ret_val = 0;
 15.1638 +		goto out;
 15.1639 +	}
 15.1640 +
 15.1641 +	ret_val = igb_acquire_phy(hw);
 15.1642 +	if (ret_val)
 15.1643 +		goto out;
 15.1644 +
 15.1645 +	ctrl = rd32(E1000_CTRL);
 15.1646 +	wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
 15.1647 +	wrfl();
 15.1648 +
 15.1649 +	udelay(phy->reset_delay_us);
 15.1650 +
 15.1651 +	wr32(E1000_CTRL, ctrl);
 15.1652 +	wrfl();
 15.1653 +
 15.1654 +	udelay(150);
 15.1655 +
 15.1656 +	igb_release_phy(hw);
 15.1657 +
 15.1658 +	ret_val = igb_get_phy_cfg_done(hw);
 15.1659 +
 15.1660 +out:
 15.1661 +	return ret_val;
 15.1662 +}
 15.1663 +
 15.1664 +/* Internal function pointers */
 15.1665 +
 15.1666 +/**
 15.1667 + *  igb_get_phy_cfg_done - Generic PHY configuration done
 15.1668 + *  @hw: pointer to the HW structure
 15.1669 + *
 15.1670 + *  Return success if silicon family did not implement a family specific
 15.1671 + *  get_cfg_done function.
 15.1672 + **/
 15.1673 +static s32 igb_get_phy_cfg_done(struct e1000_hw *hw)
 15.1674 +{
 15.1675 +	if (hw->phy.ops.get_cfg_done)
 15.1676 +		return hw->phy.ops.get_cfg_done(hw);
 15.1677 +
 15.1678 +	return 0;
 15.1679 +}
 15.1680 +
 15.1681 +/**
 15.1682 + *  igb_release_phy - Generic release PHY
 15.1683 + *  @hw: pointer to the HW structure
 15.1684 + *
 15.1685 + *  Return if silicon family does not require a semaphore when accessing the
 15.1686 + *  PHY.
 15.1687 + **/
 15.1688 +static void igb_release_phy(struct e1000_hw *hw)
 15.1689 +{
 15.1690 +	if (hw->phy.ops.release_phy)
 15.1691 +		hw->phy.ops.release_phy(hw);
 15.1692 +}
 15.1693 +
 15.1694 +/**
 15.1695 + *  igb_acquire_phy - Generic acquire PHY
 15.1696 + *  @hw: pointer to the HW structure
 15.1697 + *
 15.1698 + *  Return success if silicon family does not require a semaphore when
 15.1699 + *  accessing the PHY.
 15.1700 + **/
 15.1701 +static s32 igb_acquire_phy(struct e1000_hw *hw)
 15.1702 +{
 15.1703 +	if (hw->phy.ops.acquire_phy)
 15.1704 +		return hw->phy.ops.acquire_phy(hw);
 15.1705 +
 15.1706 +	return 0;
 15.1707 +}
 15.1708 +
 15.1709 +/**
 15.1710 + *  igb_phy_force_speed_duplex - Generic force PHY speed/duplex
 15.1711 + *  @hw: pointer to the HW structure
 15.1712 + *
 15.1713 + *  When the silicon family has not implemented a forced speed/duplex
 15.1714 + *  function for the PHY, simply return 0.
 15.1715 + **/
 15.1716 +s32 igb_phy_force_speed_duplex(struct e1000_hw *hw)
 15.1717 +{
 15.1718 +	if (hw->phy.ops.force_speed_duplex)
 15.1719 +		return hw->phy.ops.force_speed_duplex(hw);
 15.1720 +
 15.1721 +	return 0;
 15.1722 +}
 15.1723 +
 15.1724 +/**
 15.1725 + *  igb_phy_init_script_igp3 - Inits the IGP3 PHY
 15.1726 + *  @hw: pointer to the HW structure
 15.1727 + *
 15.1728 + *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
 15.1729 + **/
 15.1730 +s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
 15.1731 +{
 15.1732 +	hw_dbg("Running IGP 3 PHY init script\n");
 15.1733 +
 15.1734 +	/* PHY init IGP 3 */
 15.1735 +	/* Enable rise/fall, 10-mode work in class-A */
 15.1736 +	hw->phy.ops.write_phy_reg(hw, 0x2F5B, 0x9018);
 15.1737 +	/* Remove all caps from Replica path filter */
 15.1738 +	hw->phy.ops.write_phy_reg(hw, 0x2F52, 0x0000);
 15.1739 +	/* Bias trimming for ADC, AFE and Driver (Default) */
 15.1740 +	hw->phy.ops.write_phy_reg(hw, 0x2FB1, 0x8B24);
 15.1741 +	/* Increase Hybrid poly bias */
 15.1742 +	hw->phy.ops.write_phy_reg(hw, 0x2FB2, 0xF8F0);
 15.1743 +	/* Add 4% to TX amplitude in Giga mode */
 15.1744 +	hw->phy.ops.write_phy_reg(hw, 0x2010, 0x10B0);
 15.1745 +	/* Disable trimming (TTT) */
 15.1746 +	hw->phy.ops.write_phy_reg(hw, 0x2011, 0x0000);
 15.1747 +	/* Poly DC correction to 94.6% + 2% for all channels */
 15.1748 +	hw->phy.ops.write_phy_reg(hw, 0x20DD, 0x249A);
 15.1749 +	/* ABS DC correction to 95.9% */
 15.1750 +	hw->phy.ops.write_phy_reg(hw, 0x20DE, 0x00D3);
 15.1751 +	/* BG temp curve trim */
 15.1752 +	hw->phy.ops.write_phy_reg(hw, 0x28B4, 0x04CE);
 15.1753 +	/* Increasing ADC OPAMP stage 1 currents to max */
 15.1754 +	hw->phy.ops.write_phy_reg(hw, 0x2F70, 0x29E4);
 15.1755 +	/* Force 1000 ( required for enabling PHY regs configuration) */
 15.1756 +	hw->phy.ops.write_phy_reg(hw, 0x0000, 0x0140);
 15.1757 +	/* Set upd_freq to 6 */
 15.1758 +	hw->phy.ops.write_phy_reg(hw, 0x1F30, 0x1606);
 15.1759 +	/* Disable NPDFE */
 15.1760 +	hw->phy.ops.write_phy_reg(hw, 0x1F31, 0xB814);
 15.1761 +	/* Disable adaptive fixed FFE (Default) */
 15.1762 +	hw->phy.ops.write_phy_reg(hw, 0x1F35, 0x002A);
 15.1763 +	/* Enable FFE hysteresis */
 15.1764 +	hw->phy.ops.write_phy_reg(hw, 0x1F3E, 0x0067);
 15.1765 +	/* Fixed FFE for short cable lengths */
 15.1766 +	hw->phy.ops.write_phy_reg(hw, 0x1F54, 0x0065);
 15.1767 +	/* Fixed FFE for medium cable lengths */
 15.1768 +	hw->phy.ops.write_phy_reg(hw, 0x1F55, 0x002A);
 15.1769 +	/* Fixed FFE for long cable lengths */
 15.1770 +	hw->phy.ops.write_phy_reg(hw, 0x1F56, 0x002A);
 15.1771 +	/* Enable Adaptive Clip Threshold */
 15.1772 +	hw->phy.ops.write_phy_reg(hw, 0x1F72, 0x3FB0);
 15.1773 +	/* AHT reset limit to 1 */
 15.1774 +	hw->phy.ops.write_phy_reg(hw, 0x1F76, 0xC0FF);
 15.1775 +	/* Set AHT master delay to 127 msec */
 15.1776 +	hw->phy.ops.write_phy_reg(hw, 0x1F77, 0x1DEC);
 15.1777 +	/* Set scan bits for AHT */
 15.1778 +	hw->phy.ops.write_phy_reg(hw, 0x1F78, 0xF9EF);
 15.1779 +	/* Set AHT Preset bits */
 15.1780 +	hw->phy.ops.write_phy_reg(hw, 0x1F79, 0x0210);
 15.1781 +	/* Change integ_factor of channel A to 3 */
 15.1782 +	hw->phy.ops.write_phy_reg(hw, 0x1895, 0x0003);
 15.1783 +	/* Change prop_factor of channels BCD to 8 */
 15.1784 +	hw->phy.ops.write_phy_reg(hw, 0x1796, 0x0008);
 15.1785 +	/* Change cg_icount + enable integbp for channels BCD */
 15.1786 +	hw->phy.ops.write_phy_reg(hw, 0x1798, 0xD008);
 15.1787 +	/*
 15.1788 +	 * Change cg_icount + enable integbp + change prop_factor_master
 15.1789 +	 * to 8 for channel A
 15.1790 +	 */
 15.1791 +	hw->phy.ops.write_phy_reg(hw, 0x1898, 0xD918);
 15.1792 +	/* Disable AHT in Slave mode on channel A */
 15.1793 +	hw->phy.ops.write_phy_reg(hw, 0x187A, 0x0800);
 15.1794 +	/*
 15.1795 +	 * Enable LPLU and disable AN to 1000 in non-D0a states,
 15.1796 +	 * Enable SPD+B2B
 15.1797 +	 */
 15.1798 +	hw->phy.ops.write_phy_reg(hw, 0x0019, 0x008D);
 15.1799 +	/* Enable restart AN on an1000_dis change */
 15.1800 +	hw->phy.ops.write_phy_reg(hw, 0x001B, 0x2080);
 15.1801 +	/* Enable wh_fifo read clock in 10/100 modes */
 15.1802 +	hw->phy.ops.write_phy_reg(hw, 0x0014, 0x0045);
 15.1803 +	/* Restart AN, Speed selection is 1000 */
 15.1804 +	hw->phy.ops.write_phy_reg(hw, 0x0000, 0x1340);
 15.1805 +
 15.1806 +	return 0;
 15.1807 +}
 15.1808 +
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/drivers/net/igb/e1000_phy.h	Tue Feb 17 11:25:51 2009 +0000
    16.3 @@ -0,0 +1,100 @@
    16.4 +/*******************************************************************************
    16.5 +
    16.6 +  Intel(R) Gigabit Ethernet Linux driver
    16.7 +  Copyright(c) 2007 Intel Corporation.
    16.8 +
    16.9 +  This program is free software; you can redistribute it and/or modify it
   16.10 +  under the terms and conditions of the GNU General Public License,
   16.11 +  version 2, as published by the Free Software Foundation.
   16.12 +
   16.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   16.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   16.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   16.16 +  more details.
   16.17 +
   16.18 +  You should have received a copy of the GNU General Public License along with
   16.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   16.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   16.21 +
   16.22 +  The full GNU General Public License is included in this distribution in
   16.23 +  the file called "COPYING".
   16.24 +
   16.25 +  Contact Information:
   16.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   16.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   16.28 +
   16.29 +*******************************************************************************/
   16.30 +
   16.31 +#ifndef _E1000_PHY_H_
   16.32 +#define _E1000_PHY_H_
   16.33 +
   16.34 +#include "igb_compat.h"
   16.35 +
   16.36 +enum e1000_ms_type {
   16.37 +	e1000_ms_hw_default = 0,
   16.38 +	e1000_ms_force_master,
   16.39 +	e1000_ms_force_slave,
   16.40 +	e1000_ms_auto
   16.41 +};
   16.42 +
   16.43 +enum e1000_smart_speed {
   16.44 +	e1000_smart_speed_default = 0,
   16.45 +	e1000_smart_speed_on,
   16.46 +	e1000_smart_speed_off
   16.47 +};
   16.48 +
   16.49 +s32  igb_check_downshift(struct e1000_hw *hw);
   16.50 +s32  igb_check_reset_block(struct e1000_hw *hw);
   16.51 +s32  igb_copper_link_autoneg(struct e1000_hw *hw);
   16.52 +s32  igb_phy_force_speed_duplex(struct e1000_hw *hw);
   16.53 +s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
   16.54 +s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
   16.55 +s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
   16.56 +s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
   16.57 +s32  igb_get_cable_length_m88(struct e1000_hw *hw);
   16.58 +s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
   16.59 +s32  igb_get_phy_id(struct e1000_hw *hw);
   16.60 +s32  igb_get_phy_info_igp(struct e1000_hw *hw);
   16.61 +s32  igb_get_phy_info_m88(struct e1000_hw *hw);
   16.62 +s32  igb_phy_sw_reset(struct e1000_hw *hw);
   16.63 +s32  igb_phy_hw_reset(struct e1000_hw *hw);
   16.64 +s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
   16.65 +s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
   16.66 +s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
   16.67 +s32  igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
   16.68 +				u32 usec_interval, bool *success);
   16.69 +s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
   16.70 +
   16.71 +/* IGP01E1000 Specific Registers */
   16.72 +#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
   16.73 +#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
   16.74 +#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
   16.75 +#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
   16.76 +#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
   16.77 +#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
   16.78 +#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
   16.79 +#define IGP01E1000_PHY_POLARITY_MASK      0x0078
   16.80 +#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
   16.81 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
   16.82 +#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
   16.83 +
   16.84 +/* Enable flexible speed on link-up */
   16.85 +#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
   16.86 +#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
   16.87 +#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
   16.88 +#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
   16.89 +#define IGP01E1000_PSSR_MDIX              0x0008
   16.90 +#define IGP01E1000_PSSR_SPEED_MASK        0xC000
   16.91 +#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
   16.92 +#define IGP02E1000_PHY_CHANNEL_NUM        4
   16.93 +#define IGP02E1000_PHY_AGC_A              0x11B1
   16.94 +#define IGP02E1000_PHY_AGC_B              0x12B1
   16.95 +#define IGP02E1000_PHY_AGC_C              0x14B1
   16.96 +#define IGP02E1000_PHY_AGC_D              0x18B1
   16.97 +#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
   16.98 +#define IGP02E1000_AGC_LENGTH_MASK        0x7F
   16.99 +#define IGP02E1000_AGC_RANGE              15
  16.100 +
  16.101 +#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
  16.102 +
  16.103 +#endif
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/drivers/net/igb/e1000_regs.h	Tue Feb 17 11:25:51 2009 +0000
    17.3 @@ -0,0 +1,272 @@
    17.4 +/*******************************************************************************
    17.5 +
    17.6 +  Intel(R) Gigabit Ethernet Linux driver
    17.7 +  Copyright(c) 2007 Intel Corporation.
    17.8 +
    17.9 +  This program is free software; you can redistribute it and/or modify it
   17.10 +  under the terms and conditions of the GNU General Public License,
   17.11 +  version 2, as published by the Free Software Foundation.
   17.12 +
   17.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   17.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   17.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   17.16 +  more details.
   17.17 +
   17.18 +  You should have received a copy of the GNU General Public License along with
   17.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   17.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   17.21 +
   17.22 +  The full GNU General Public License is included in this distribution in
   17.23 +  the file called "COPYING".
   17.24 +
   17.25 +  Contact Information:
   17.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   17.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   17.28 +
   17.29 +*******************************************************************************/
   17.30 +
   17.31 +#ifndef _E1000_REGS_H_
   17.32 +#define _E1000_REGS_H_
   17.33 +
   17.34 +#define E1000_CTRL     0x00000  /* Device Control - RW */
   17.35 +#define E1000_STATUS   0x00008  /* Device Status - RO */
   17.36 +#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
   17.37 +#define E1000_EERD     0x00014  /* EEPROM Read - RW */
   17.38 +#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
   17.39 +#define E1000_MDIC     0x00020  /* MDI Control - RW */
   17.40 +#define E1000_SCTL     0x00024  /* SerDes Control - RW */
   17.41 +#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
   17.42 +#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
   17.43 +#define E1000_FCT      0x00030  /* Flow Control Type - RW */
   17.44 +#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
   17.45 +#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
   17.46 +#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
   17.47 +#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
   17.48 +#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
   17.49 +#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
   17.50 +#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
   17.51 +#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
   17.52 +#define E1000_RCTL     0x00100  /* RX Control - RW */
   17.53 +#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
   17.54 +#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
   17.55 +#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
   17.56 +#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
   17.57 +#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
   17.58 +#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
   17.59 +#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
   17.60 +#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
   17.61 +#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
   17.62 +#define E1000_GPIE     0x01514  /* General Purpose Interrupt Enable - RW */
   17.63 +#define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
   17.64 +#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
   17.65 +#define E1000_TCTL     0x00400  /* TX Control - RW */
   17.66 +#define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
   17.67 +#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
   17.68 +#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
   17.69 +#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
   17.70 +#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
   17.71 +#define E1000_PBS      0x01008  /* Packet Buffer Size */
   17.72 +#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
   17.73 +#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
   17.74 +#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
   17.75 +#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
   17.76 +#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */
   17.77 +#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
   17.78 +#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
   17.79 +#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
   17.80 +#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
   17.81 +/* Split and Replication RX Control - RW */
   17.82 +/*
   17.83 + * Convenience macros
   17.84 + *
   17.85 + * Note: "_n" is the queue number of the register to be written to.
   17.86 + *
   17.87 + * Example usage:
   17.88 + * E1000_RDBAL_REG(current_rx_queue)
   17.89 + */
   17.90 +#define E1000_RDBAL(_n)   ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \
   17.91 +				    : (0x0C000 + ((_n) * 0x40)))
   17.92 +#define E1000_RDBAH(_n)   ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \
   17.93 +				    : (0x0C004 + ((_n) * 0x40)))
   17.94 +#define E1000_RDLEN(_n)   ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \
   17.95 +				    : (0x0C008 + ((_n) * 0x40)))
   17.96 +#define E1000_SRRCTL(_n)  ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \
   17.97 +				    : (0x0C00C + ((_n) * 0x40)))
   17.98 +#define E1000_RDH(_n)     ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \
   17.99 +				    : (0x0C010 + ((_n) * 0x40)))
  17.100 +#define E1000_RDT(_n)     ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \
  17.101 +				    : (0x0C018 + ((_n) * 0x40)))
  17.102 +#define E1000_RXDCTL(_n)  ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \
  17.103 +				    : (0x0C028 + ((_n) * 0x40)))
  17.104 +#define E1000_TDBAL(_n)   ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \
  17.105 +				    : (0x0E000 + ((_n) * 0x40)))
  17.106 +#define E1000_TDBAH(_n)   ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \
  17.107 +				    : (0x0E004 + ((_n) * 0x40)))
  17.108 +#define E1000_TDLEN(_n)   ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \
  17.109 +				    : (0x0E008 + ((_n) * 0x40)))
  17.110 +#define E1000_TDH(_n)     ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \
  17.111 +				    : (0x0E010 + ((_n) * 0x40)))
  17.112 +#define E1000_TDT(_n)     ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \
  17.113 +				    : (0x0E018 + ((_n) * 0x40)))
  17.114 +#define E1000_TXDCTL(_n)  ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
  17.115 +				    : (0x0E028 + ((_n) * 0x40)))
  17.116 +#define E1000_TARC(_n)    (0x03840 + (_n << 8))
  17.117 +#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
  17.118 +#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
  17.119 +#define E1000_TDWBAL(_n)  ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
  17.120 +				    : (0x0E038 + ((_n) * 0x40)))
  17.121 +#define E1000_TDWBAH(_n)  ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \
  17.122 +				    : (0x0E03C + ((_n) * 0x40)))
  17.123 +#define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
  17.124 +#define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
  17.125 +#define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
  17.126 +#define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
  17.127 +#define E1000_DTXCTL   0x03590  /* DMA TX Control - RW */
  17.128 +#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
  17.129 +#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
  17.130 +#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
  17.131 +#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
  17.132 +#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
  17.133 +#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
  17.134 +#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
  17.135 +#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
  17.136 +#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
  17.137 +#define E1000_COLC     0x04028  /* Collision Count - R/clr */
  17.138 +#define E1000_DC       0x04030  /* Defer Count - R/clr */
  17.139 +#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
  17.140 +#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
  17.141 +#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
  17.142 +#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
  17.143 +#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
  17.144 +#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
  17.145 +#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
  17.146 +#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
  17.147 +#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
  17.148 +#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
  17.149 +#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
  17.150 +#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
  17.151 +#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
  17.152 +#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
  17.153 +#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
  17.154 +#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
  17.155 +#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
  17.156 +#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
  17.157 +#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
  17.158 +#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
  17.159 +#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
  17.160 +#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
  17.161 +#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
  17.162 +#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
  17.163 +#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
  17.164 +#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
  17.165 +#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
  17.166 +#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
  17.167 +#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
  17.168 +#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
  17.169 +#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
  17.170 +#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
  17.171 +#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
  17.172 +#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
  17.173 +#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
  17.174 +#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
  17.175 +#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
  17.176 +#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
  17.177 +#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
  17.178 +#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
  17.179 +#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
  17.180 +#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
  17.181 +#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
  17.182 +#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
  17.183 +#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
  17.184 +#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
  17.185 +#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
  17.186 +#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
  17.187 +/* Interrupt Cause Rx Packet Timer Expire Count */
  17.188 +#define E1000_ICRXPTC  0x04104
  17.189 +/* Interrupt Cause Rx Absolute Timer Expire Count */
  17.190 +#define E1000_ICRXATC  0x04108
  17.191 +/* Interrupt Cause Tx Packet Timer Expire Count */
  17.192 +#define E1000_ICTXPTC  0x0410C
  17.193 +/* Interrupt Cause Tx Absolute Timer Expire Count */
  17.194 +#define E1000_ICTXATC  0x04110
  17.195 +/* Interrupt Cause Tx Queue Empty Count */
  17.196 +#define E1000_ICTXQEC  0x04118
  17.197 +/* Interrupt Cause Tx Queue Minimum Threshold Count */
  17.198 +#define E1000_ICTXQMTC 0x0411C
  17.199 +/* Interrupt Cause Rx Descriptor Minimum Threshold Count */
  17.200 +#define E1000_ICRXDMTC 0x04120
  17.201 +#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
  17.202 +#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
  17.203 +#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
  17.204 +#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
  17.205 +#define E1000_CBTMPC      0x0402C  /* Circuit Breaker TX Packet Count */
  17.206 +#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
  17.207 +#define E1000_CBRMPC      0x040FC  /* Circuit Breaker RX Packet Count */
  17.208 +#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
  17.209 +#define E1000_HGPTC       0x04118  /* Host Good Packets TX Count */
  17.210 +#define E1000_HTCBDPC     0x04124  /* Host TX Circuit Breaker Dropped Count */
  17.211 +#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
  17.212 +#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
  17.213 +#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
  17.214 +#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
  17.215 +#define E1000_LENERRS     0x04138  /* Length Errors Count */
  17.216 +#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
  17.217 +#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
  17.218 +#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
  17.219 +#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
  17.220 +#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
  17.221 +#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
  17.222 +#define E1000_RLPML    0x05004  /* RX Long Packet Max Length */
  17.223 +#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
  17.224 +#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
  17.225 +#define E1000_RA       0x05400  /* Receive Address - RW Array */
  17.226 +#define E1000_RA2      0x054E0  /* 2nd half of receive address array - RW Array */
  17.227 +#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
  17.228 +#define E1000_VMD_CTL  0x0581C  /* VMDq Control - RW */
  17.229 +#define E1000_WUC      0x05800  /* Wakeup Control - RW */
  17.230 +#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
  17.231 +#define E1000_WUS      0x05810  /* Wakeup Status - RO */
  17.232 +#define E1000_MANC     0x05820  /* Management Control - RW */
  17.233 +#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
  17.234 +#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
  17.235 +#define E1000_HOST_IF  0x08800  /* Host Interface */
  17.236 +
  17.237 +#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
  17.238 +#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
  17.239 +#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
  17.240 +#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
  17.241 +#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
  17.242 +#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
  17.243 +#define E1000_SWSM      0x05B50 /* SW Semaphore */
  17.244 +#define E1000_FWSM      0x05B54 /* FW Semaphore */
  17.245 +#define E1000_HICR      0x08F00 /* Host Inteface Control */
  17.246 +
  17.247 +/* RSS registers */
  17.248 +#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
  17.249 +#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
  17.250 +#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
  17.251 +#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
  17.252 +/* MSI-X Allocation Register (_i) - RW */
  17.253 +#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4))
  17.254 +/* MSI-X Table entry addr low reg 0 - RW */
  17.255 +#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10))
  17.256 +/* MSI-X Table entry addr upper reg 0 - RW */
  17.257 +#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
  17.258 +/* MSI-X Table entry message reg 0 - RW */
  17.259 +#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10))
  17.260 +/* MSI-X Table entry vector ctrl reg 0 - RW */
  17.261 +#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
  17.262 +/* Redirection Table - RW Array */
  17.263 +#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4))
  17.264 +#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
  17.265 +
  17.266 +#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
  17.267 +#define rd32(reg) (readl(hw->hw_addr + reg))
  17.268 +#define wrfl() ((void)rd32(E1000_STATUS))
  17.269 +
  17.270 +#define array_wr32(reg, offset, value) \
  17.271 +	(writel(value, hw->hw_addr + reg + ((offset) << 2)))
  17.272 +#define array_rd32(reg, offset) \
  17.273 +	(readl(hw->hw_addr + reg + ((offset) << 2)))
  17.274 +
  17.275 +#endif
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/drivers/net/igb/igb.h	Tue Feb 17 11:25:51 2009 +0000
    18.3 @@ -0,0 +1,324 @@
    18.4 +/*******************************************************************************
    18.5 +
    18.6 +  Intel(R) Gigabit Ethernet Linux driver
    18.7 +  Copyright(c) 2007 Intel Corporation.
    18.8 +
    18.9 +  This program is free software; you can redistribute it and/or modify it
   18.10 +  under the terms and conditions of the GNU General Public License,
   18.11 +  version 2, as published by the Free Software Foundation.
   18.12 +
   18.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   18.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   18.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   18.16 +  more details.
   18.17 +
   18.18 +  You should have received a copy of the GNU General Public License along with
   18.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   18.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   18.21 +
   18.22 +  The full GNU General Public License is included in this distribution in
   18.23 +  the file called "COPYING".
   18.24 +
   18.25 +  Contact Information:
   18.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   18.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   18.28 +
   18.29 +*******************************************************************************/
   18.30 +
   18.31 +
   18.32 +/* Linux PRO/1000 Ethernet Driver main header file */
   18.33 +
   18.34 +#ifndef _IGB_H_
   18.35 +#define _IGB_H_
   18.36 +
   18.37 +#include "e1000_mac.h"
   18.38 +#include "e1000_82575.h"
   18.39 +
   18.40 +struct igb_adapter;
   18.41 +
   18.42 +#ifdef CONFIG_IGB_LRO
   18.43 +#include <linux/inet_lro.h>
   18.44 +#define MAX_LRO_AGGR                      32
   18.45 +#define MAX_LRO_DESCRIPTORS                8
   18.46 +#endif
   18.47 +
   18.48 +/* Interrupt defines */
   18.49 +#define IGB_MAX_TX_CLEAN 72
   18.50 +
   18.51 +#define IGB_MIN_DYN_ITR 3000
   18.52 +#define IGB_MAX_DYN_ITR 96000
   18.53 +
   18.54 +/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
   18.55 +#define IGB_START_ITR 648
   18.56 +
   18.57 +#define IGB_DYN_ITR_PACKET_THRESHOLD 2
   18.58 +#define IGB_DYN_ITR_LENGTH_LOW 200
   18.59 +#define IGB_DYN_ITR_LENGTH_HIGH 1000
   18.60 +
   18.61 +/* TX/RX descriptor defines */
   18.62 +#define IGB_DEFAULT_TXD                  256
   18.63 +#define IGB_MIN_TXD                       80
   18.64 +#define IGB_MAX_TXD                     4096
   18.65 +
   18.66 +#define IGB_DEFAULT_RXD                  256
   18.67 +#define IGB_MIN_RXD                       80
   18.68 +#define IGB_MAX_RXD                     4096
   18.69 +
   18.70 +#define IGB_DEFAULT_ITR                    3 /* dynamic */
   18.71 +#define IGB_MAX_ITR_USECS              10000
   18.72 +#define IGB_MIN_ITR_USECS                 10
   18.73 +
   18.74 +/* Transmit and receive queues */
   18.75 +#define IGB_MAX_RX_QUEUES                  4
   18.76 +
   18.77 +/* RX descriptor control thresholds.
   18.78 + * PTHRESH - MAC will consider prefetch if it has fewer than this number of
   18.79 + *           descriptors available in its onboard memory.
   18.80 + *           Setting this to 0 disables RX descriptor prefetch.
   18.81 + * HTHRESH - MAC will only prefetch if there are at least this many descriptors
   18.82 + *           available in host memory.
   18.83 + *           If PTHRESH is 0, this should also be 0.
   18.84 + * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
   18.85 + *           descriptors until either it has this many to write back, or the
   18.86 + *           ITR timer expires.
   18.87 + */
   18.88 +#define IGB_RX_PTHRESH                    16
   18.89 +#define IGB_RX_HTHRESH                     8
   18.90 +#define IGB_RX_WTHRESH                     1
   18.91 +
   18.92 +/* this is the size past which hardware will drop packets when setting LPE=0 */
   18.93 +#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
   18.94 +
   18.95 +/* Supported Rx Buffer Sizes */
   18.96 +#define IGB_RXBUFFER_128   128    /* Used for packet split */
   18.97 +#define IGB_RXBUFFER_256   256    /* Used for packet split */
   18.98 +#define IGB_RXBUFFER_512   512
   18.99 +#define IGB_RXBUFFER_1024  1024
  18.100 +#define IGB_RXBUFFER_2048  2048
  18.101 +#define IGB_RXBUFFER_4096  4096
  18.102 +#define IGB_RXBUFFER_8192  8192
  18.103 +#define IGB_RXBUFFER_16384 16384
  18.104 +
  18.105 +/* Packet Buffer allocations */
  18.106 +
  18.107 +
  18.108 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
  18.109 +#define IGB_TX_QUEUE_WAKE	16
  18.110 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
  18.111 +#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */
  18.112 +
  18.113 +#define AUTO_ALL_MODES            0
  18.114 +#define IGB_EEPROM_APME         0x0400
  18.115 +
  18.116 +#ifndef IGB_MASTER_SLAVE
  18.117 +/* Switch to override PHY master/slave setting */
  18.118 +#define IGB_MASTER_SLAVE	e1000_ms_hw_default
  18.119 +#endif
  18.120 +
  18.121 +#define IGB_MNG_VLAN_NONE -1
  18.122 +
  18.123 +/* wrapper around a pointer to a socket buffer,
  18.124 + * so a DMA handle can be stored along with the buffer */
  18.125 +struct igb_buffer {
  18.126 +	struct sk_buff *skb;
  18.127 +	dma_addr_t dma;
  18.128 +	union {
  18.129 +		/* TX */
  18.130 +		struct {
  18.131 +			unsigned long time_stamp;
  18.132 +			u32 length;
  18.133 +		};
  18.134 +		/* RX */
  18.135 +		struct {
  18.136 +			struct page *page;
  18.137 +			u64 page_dma;
  18.138 +			unsigned int page_offset;
  18.139 +		};
  18.140 +	};
  18.141 +};
  18.142 +
  18.143 +struct igb_queue_stats {
  18.144 +	u64 packets;
  18.145 +	u64 bytes;
  18.146 +};
  18.147 +
  18.148 +struct igb_ring {
  18.149 +	struct igb_adapter *adapter; /* backlink */
  18.150 +	void *desc;                  /* descriptor ring memory */
  18.151 +	dma_addr_t dma;              /* phys address of the ring */
  18.152 +	unsigned int size;           /* length of desc. ring in bytes */
  18.153 +	unsigned int count;          /* number of desc. in the ring */
  18.154 +	u16 next_to_use;
  18.155 +	u16 next_to_clean;
  18.156 +	u16 head;
  18.157 +	u16 tail;
  18.158 +	struct igb_buffer *buffer_info; /* array of buffer info structs */
  18.159 +
  18.160 +	u32 eims_value;
  18.161 +	u32 itr_val;
  18.162 +	u16 itr_register;
  18.163 +	u16 cpu;
  18.164 +
  18.165 +	int queue_index;
  18.166 +	unsigned int total_bytes;
  18.167 +	unsigned int total_packets;
  18.168 +
  18.169 +	union {
  18.170 +		/* TX */
  18.171 +		struct {
  18.172 +			spinlock_t tx_clean_lock;
  18.173 +			spinlock_t tx_lock;
  18.174 +			bool detect_tx_hung;
  18.175 +		};
  18.176 +		/* RX */
  18.177 +		struct {
  18.178 +			struct igb_queue_stats rx_stats;
  18.179 +			struct net_device *netdev;
  18.180 +			struct igb_ring *buddy;
  18.181 +			int set_itr;
  18.182 +#ifdef CONFIG_IGB_LRO
  18.183 +			struct net_lro_mgr lro_mgr;
  18.184 +			bool lro_used;
  18.185 +#endif
  18.186 +		};
  18.187 +	};
  18.188 +
  18.189 +	char name[IFNAMSIZ + 5];
  18.190 +};
  18.191 +
  18.192 +#define IGB_DESC_UNUSED(R) \
  18.193 +	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  18.194 +	(R)->next_to_clean - (R)->next_to_use - 1)
  18.195 +
  18.196 +#define E1000_RX_DESC_ADV(R, i)	    \
  18.197 +	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
  18.198 +#define E1000_TX_DESC_ADV(R, i)	    \
  18.199 +	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
  18.200 +#define E1000_TX_CTXTDESC_ADV(R, i)	    \
  18.201 +	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
  18.202 +#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
  18.203 +#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
  18.204 +#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
  18.205 +
  18.206 +/* board specific private data structure */
  18.207 +
  18.208 +struct igb_adapter {
  18.209 +	struct timer_list watchdog_timer;
  18.210 +	struct timer_list phy_info_timer;
  18.211 +	struct vlan_group *vlgrp;
  18.212 +	u16 mng_vlan_id;
  18.213 +	u32 bd_number;
  18.214 +	u32 rx_buffer_len;
  18.215 +	u32 wol;
  18.216 +	u32 en_mng_pt;
  18.217 +	u16 link_speed;
  18.218 +	u16 link_duplex;
  18.219 +	unsigned int total_tx_bytes;
  18.220 +	unsigned int total_tx_packets;
  18.221 +	unsigned int total_rx_bytes;
  18.222 +	unsigned int total_rx_packets;
  18.223 +	/* Interrupt Throttle Rate */
  18.224 +	u32 itr;
  18.225 +	u32 itr_setting;
  18.226 +	u16 tx_itr;
  18.227 +	u16 rx_itr;
  18.228 +
  18.229 +	struct work_struct reset_task;
  18.230 +	struct work_struct watchdog_task;
  18.231 +	bool fc_autoneg;
  18.232 +	u8  tx_timeout_factor;
  18.233 +	struct timer_list blink_timer;
  18.234 +	unsigned long led_status;
  18.235 +
  18.236 +	/* TX */
  18.237 +	struct igb_ring *tx_ring;      /* One per active queue */
  18.238 +	unsigned int restart_queue;
  18.239 +	unsigned long tx_queue_len;
  18.240 +	u32 txd_cmd;
  18.241 +	u32 gotc;
  18.242 +	u64 gotc_old;
  18.243 +	u64 tpt_old;
  18.244 +	u64 colc_old;
  18.245 +	u32 tx_timeout_count;
  18.246 +
  18.247 +	/* RX */
  18.248 +	struct igb_ring *rx_ring;      /* One per active queue */
  18.249 +	int num_tx_queues;
  18.250 +	int num_rx_queues;
  18.251 +
  18.252 +	u64 hw_csum_err;
  18.253 +	u64 hw_csum_good;
  18.254 +	u64 rx_hdr_split;
  18.255 +	u32 alloc_rx_buff_failed;
  18.256 +	bool rx_csum;
  18.257 +	u32 gorc;
  18.258 +	u64 gorc_old;
  18.259 +	u16 rx_ps_hdr_size;
  18.260 +	u32 max_frame_size;
  18.261 +	u32 min_frame_size;
  18.262 +
  18.263 +	/* OS defined structs */
  18.264 +	struct net_device *netdev;
  18.265 +	struct pci_dev *pdev;
  18.266 +	struct net_device_stats net_stats;
  18.267 +
  18.268 +	/* structs defined in e1000_hw.h */
  18.269 +	struct e1000_hw hw;
  18.270 +	struct e1000_hw_stats stats;
  18.271 +	struct e1000_phy_info phy_info;
  18.272 +	struct e1000_phy_stats phy_stats;
  18.273 +
  18.274 +	u32 test_icr;
  18.275 +	struct igb_ring test_tx_ring;
  18.276 +	struct igb_ring test_rx_ring;
  18.277 +
  18.278 +	int msg_enable;
  18.279 +	struct msix_entry *msix_entries;
  18.280 +	u32 eims_enable_mask;
  18.281 +	u32 eims_other;
  18.282 +
  18.283 +	/* to not mess up cache alignment, always add to the bottom */
  18.284 +	unsigned long state;
  18.285 +	unsigned int flags;
  18.286 +	u32 eeprom_wol;
  18.287 +#ifdef CONFIG_IGB_LRO
  18.288 +	unsigned int lro_max_aggr;
  18.289 +	unsigned int lro_aggregated;
  18.290 +	unsigned int lro_flushed;
  18.291 +	unsigned int lro_no_desc;
  18.292 +#endif
  18.293 +};
  18.294 +
  18.295 +#define IGB_FLAG_HAS_MSI           (1 << 0)
  18.296 +#define IGB_FLAG_MSI_ENABLE        (1 << 1)
  18.297 +#define IGB_FLAG_HAS_DCA           (1 << 2)
  18.298 +#define IGB_FLAG_DCA_ENABLED       (1 << 3)
  18.299 +#define IGB_FLAG_IN_NETPOLL        (1 << 5)
  18.300 +#define IGB_FLAG_QUAD_PORT_A       (1 << 6)
  18.301 +#define IGB_FLAG_NEED_CTX_IDX      (1 << 7)
  18.302 +
  18.303 +enum e1000_state_t {
  18.304 +	__IGB_TESTING,
  18.305 +	__IGB_RESETTING,
  18.306 +	__IGB_DOWN
  18.307 +};
  18.308 +
  18.309 +enum igb_boards {
  18.310 +	board_82575,
  18.311 +};
  18.312 +
  18.313 +extern char igb_driver_name[];
  18.314 +extern char igb_driver_version[];
  18.315 +
  18.316 +extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
  18.317 +extern int igb_up(struct igb_adapter *);
  18.318 +extern void igb_down(struct igb_adapter *);
  18.319 +extern void igb_reinit_locked(struct igb_adapter *);
  18.320 +extern void igb_reset(struct igb_adapter *);
  18.321 +extern int igb_set_spd_dplx(struct igb_adapter *, u16);
  18.322 +extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
  18.323 +extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
  18.324 +extern void igb_update_stats(struct igb_adapter *);
  18.325 +extern void igb_set_ethtool_ops(struct net_device *);
  18.326 +
  18.327 +#endif /* _IGB_H_ */
    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/drivers/net/igb/igb_compat.h	Tue Feb 17 11:25:51 2009 +0000
    19.3 @@ -0,0 +1,55 @@
    19.4 +#ifndef __IGB_COMPAT_H__
    19.5 +#define __IGB_COMPAT_H__
    19.6 +
    19.7 +#include <linux/if_vlan.h>
    19.8 +#include <linux/pci.h>
    19.9 +
   19.10 +typedef unsigned int bool;
   19.11 +
   19.12 +#define ETH_FCS_LEN               4
   19.13 +
   19.14 +static inline struct net_device *vlan_group_get_device(struct vlan_group *vg,
   19.15 +						       int vlan_id)
   19.16 +{
   19.17 +	return vg->vlan_devices[vlan_id];
   19.18 +}
   19.19 +
   19.20 +static inline void vlan_group_set_device(struct vlan_group *vg, int vlan_id,
   19.21 +					 struct net_device *dev)
   19.22 +{
   19.23 +	vg->vlan_devices[vlan_id] = NULL;
   19.24 +}
   19.25 +
   19.26 +/* generic boolean compatibility */
   19.27 +#define true 1
   19.28 +#define false 0
   19.29 +
   19.30 +#ifndef PCI_VDEVICE
   19.31 +#define PCI_VDEVICE(ven, dev)        \
   19.32 +        PCI_VENDOR_ID_##ven, (dev),  \
   19.33 +    PCI_ANY_ID, PCI_ANY_ID, 0, 0
   19.34 +#endif
   19.35 +
   19.36 +static inline int pci_channel_offline(struct pci_dev *pdev)
   19.37 +{
   19.38 +    return (pdev->error_state != pci_channel_io_normal);
   19.39 +}
   19.40 +
   19.41 +#ifndef round_jiffies
   19.42 +#define round_jiffies(x) x
   19.43 +#endif
   19.44 +
   19.45 +#define tcp_hdr(skb) (skb->h.th)
   19.46 +#define tcp_hdrlen(skb) (skb->h.th->doff << 2)
   19.47 +#define ip_hdr(skb) (skb->nh.iph)
   19.48 +#define ipv6_hdr(skb) (skb->nh.ipv6h)
   19.49 +#define skb_network_header(skb) (skb->nh.raw)
   19.50 +#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw)
   19.51 +#define skb_network_offset(skb) (skb->nh.raw - skb->data)
   19.52 +
   19.53 +#ifndef CHECKSUM_PARTIAL
   19.54 +#define CHECKSUM_PARTIAL CHECKSUM_HW
   19.55 +#define CHECKSUM_COMPLETE CHECKSUM_HW
   19.56 +#endif
   19.57 +
   19.58 +#endif
    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/drivers/net/igb/igb_ethtool.c	Tue Feb 17 11:25:51 2009 +0000
    20.3 @@ -0,0 +1,2026 @@
    20.4 +/*******************************************************************************
    20.5 +
    20.6 +  Intel(R) Gigabit Ethernet Linux driver
    20.7 +  Copyright(c) 2007 Intel Corporation.
    20.8 +
    20.9 +  This program is free software; you can redistribute it and/or modify it
   20.10 +  under the terms and conditions of the GNU General Public License,
   20.11 +  version 2, as published by the Free Software Foundation.
   20.12 +
   20.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   20.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   20.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   20.16 +  more details.
   20.17 +
   20.18 +  You should have received a copy of the GNU General Public License along with
   20.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   20.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   20.21 +
   20.22 +  The full GNU General Public License is included in this distribution in
   20.23 +  the file called "COPYING".
   20.24 +
   20.25 +  Contact Information:
   20.26 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   20.27 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   20.28 +
   20.29 +*******************************************************************************/
   20.30 +
   20.31 +/* ethtool support for igb */
   20.32 +
   20.33 +#include <linux/vmalloc.h>
   20.34 +#include <linux/netdevice.h>
   20.35 +#include <linux/pci.h>
   20.36 +#include <linux/delay.h>
   20.37 +#include <linux/interrupt.h>
   20.38 +#include <linux/if_ether.h>
   20.39 +#include <linux/ethtool.h>
   20.40 +
   20.41 +#include "igb.h"
   20.42 +
   20.43 +struct igb_stats {
   20.44 +	char stat_string[ETH_GSTRING_LEN];
   20.45 +	int sizeof_stat;
   20.46 +	int stat_offset;
   20.47 +};
   20.48 +
   20.49 +#define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
   20.50 +		      offsetof(struct igb_adapter, m)
   20.51 +static const struct igb_stats igb_gstrings_stats[] = {
   20.52 +	{ "rx_packets", IGB_STAT(stats.gprc) },
   20.53 +	{ "tx_packets", IGB_STAT(stats.gptc) },
   20.54 +	{ "rx_bytes", IGB_STAT(stats.gorc) },
   20.55 +	{ "tx_bytes", IGB_STAT(stats.gotc) },
   20.56 +	{ "rx_broadcast", IGB_STAT(stats.bprc) },
   20.57 +	{ "tx_broadcast", IGB_STAT(stats.bptc) },
   20.58 +	{ "rx_multicast", IGB_STAT(stats.mprc) },
   20.59 +	{ "tx_multicast", IGB_STAT(stats.mptc) },
   20.60 +	{ "rx_errors", IGB_STAT(net_stats.rx_errors) },
   20.61 +	{ "tx_errors", IGB_STAT(net_stats.tx_errors) },
   20.62 +	{ "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
   20.63 +	{ "multicast", IGB_STAT(stats.mprc) },
   20.64 +	{ "collisions", IGB_STAT(stats.colc) },
   20.65 +	{ "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
   20.66 +	{ "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
   20.67 +	{ "rx_crc_errors", IGB_STAT(stats.crcerrs) },
   20.68 +	{ "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
   20.69 +	{ "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
   20.70 +	{ "rx_missed_errors", IGB_STAT(stats.mpc) },
   20.71 +	{ "tx_aborted_errors", IGB_STAT(stats.ecol) },
   20.72 +	{ "tx_carrier_errors", IGB_STAT(stats.tncrs) },
   20.73 +	{ "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
   20.74 +	{ "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
   20.75 +	{ "tx_window_errors", IGB_STAT(stats.latecol) },
   20.76 +	{ "tx_abort_late_coll", IGB_STAT(stats.latecol) },
   20.77 +	{ "tx_deferred_ok", IGB_STAT(stats.dc) },
   20.78 +	{ "tx_single_coll_ok", IGB_STAT(stats.scc) },
   20.79 +	{ "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
   20.80 +	{ "tx_timeout_count", IGB_STAT(tx_timeout_count) },
   20.81 +	{ "tx_restart_queue", IGB_STAT(restart_queue) },
   20.82 +	{ "rx_long_length_errors", IGB_STAT(stats.roc) },
   20.83 +	{ "rx_short_length_errors", IGB_STAT(stats.ruc) },
   20.84 +	{ "rx_align_errors", IGB_STAT(stats.algnerrc) },
   20.85 +	{ "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
   20.86 +	{ "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
   20.87 +	{ "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
   20.88 +	{ "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
   20.89 +	{ "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
   20.90 +	{ "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
   20.91 +	{ "rx_long_byte_count", IGB_STAT(stats.gorc) },
   20.92 +	{ "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
   20.93 +	{ "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
   20.94 +	{ "rx_header_split", IGB_STAT(rx_hdr_split) },
   20.95 +	{ "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
   20.96 +	{ "tx_smbus", IGB_STAT(stats.mgptc) },
   20.97 +	{ "rx_smbus", IGB_STAT(stats.mgprc) },
   20.98 +	{ "dropped_smbus", IGB_STAT(stats.mgpdc) },
   20.99 +#ifdef CONFIG_IGB_LRO
  20.100 +	{ "lro_aggregated", IGB_STAT(lro_aggregated) },
  20.101 +	{ "lro_flushed", IGB_STAT(lro_flushed) },
  20.102 +	{ "lro_no_desc", IGB_STAT(lro_no_desc) },
  20.103 +#endif
  20.104 +};
  20.105 +
  20.106 +#define IGB_QUEUE_STATS_LEN \
  20.107 +	((((((struct igb_adapter *)netdev->priv)->num_rx_queues > 1) ? \
  20.108 +	  ((struct igb_adapter *)netdev->priv)->num_rx_queues : 0) + \
  20.109 +	 (((((struct igb_adapter *)netdev->priv)->num_tx_queues > 1) ? \
  20.110 +	  ((struct igb_adapter *)netdev->priv)->num_tx_queues : 0))) * \
  20.111 +	(sizeof(struct igb_queue_stats) / sizeof(u64)))
  20.112 +#define IGB_GLOBAL_STATS_LEN	\
  20.113 +	sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
  20.114 +#define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
  20.115 +static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
  20.116 +	"Register test  (offline)", "Eeprom test    (offline)",
  20.117 +	"Interrupt test (offline)", "Loopback test  (offline)",
  20.118 +	"Link test   (on/offline)"
  20.119 +};
  20.120 +#define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
  20.121 +
  20.122 +static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
  20.123 +{
  20.124 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.125 +	struct e1000_hw *hw = &adapter->hw;
  20.126 +
  20.127 +	if (hw->phy.media_type == e1000_media_type_copper) {
  20.128 +
  20.129 +		ecmd->supported = (SUPPORTED_10baseT_Half |
  20.130 +				   SUPPORTED_10baseT_Full |
  20.131 +				   SUPPORTED_100baseT_Half |
  20.132 +				   SUPPORTED_100baseT_Full |
  20.133 +				   SUPPORTED_1000baseT_Full|
  20.134 +				   SUPPORTED_Autoneg |
  20.135 +				   SUPPORTED_TP);
  20.136 +		ecmd->advertising = ADVERTISED_TP;
  20.137 +
  20.138 +		if (hw->mac.autoneg == 1) {
  20.139 +			ecmd->advertising |= ADVERTISED_Autoneg;
  20.140 +			/* the e1000 autoneg seems to match ethtool nicely */
  20.141 +			ecmd->advertising |= hw->phy.autoneg_advertised;
  20.142 +		}
  20.143 +
  20.144 +		ecmd->port = PORT_TP;
  20.145 +		ecmd->phy_address = hw->phy.addr;
  20.146 +	} else {
  20.147 +		ecmd->supported   = (SUPPORTED_1000baseT_Full |
  20.148 +				     SUPPORTED_FIBRE |
  20.149 +				     SUPPORTED_Autoneg);
  20.150 +
  20.151 +		ecmd->advertising = (ADVERTISED_1000baseT_Full |
  20.152 +				     ADVERTISED_FIBRE |
  20.153 +				     ADVERTISED_Autoneg);
  20.154 +
  20.155 +		ecmd->port = PORT_FIBRE;
  20.156 +	}
  20.157 +
  20.158 +	ecmd->transceiver = XCVR_INTERNAL;
  20.159 +
  20.160 +	if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
  20.161 +
  20.162 +		adapter->hw.mac.ops.get_speed_and_duplex(hw,
  20.163 +					&adapter->link_speed,
  20.164 +					&adapter->link_duplex);
  20.165 +		ecmd->speed = adapter->link_speed;
  20.166 +
  20.167 +		/* unfortunately FULL_DUPLEX != DUPLEX_FULL
  20.168 +		 *          and HALF_DUPLEX != DUPLEX_HALF */
  20.169 +
  20.170 +		if (adapter->link_duplex == FULL_DUPLEX)
  20.171 +			ecmd->duplex = DUPLEX_FULL;
  20.172 +		else
  20.173 +			ecmd->duplex = DUPLEX_HALF;
  20.174 +	} else {
  20.175 +		ecmd->speed = -1;
  20.176 +		ecmd->duplex = -1;
  20.177 +	}
  20.178 +
  20.179 +	ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
  20.180 +			 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  20.181 +	return 0;
  20.182 +}
  20.183 +
  20.184 +static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
  20.185 +{
  20.186 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.187 +	struct e1000_hw *hw = &adapter->hw;
  20.188 +
  20.189 +	/* When SoL/IDER sessions are active, autoneg/speed/duplex
  20.190 +	 * cannot be changed */
  20.191 +	if (igb_check_reset_block(hw)) {
  20.192 +		dev_err(&adapter->pdev->dev, "Cannot change link "
  20.193 +			"characteristics when SoL/IDER is active.\n");
  20.194 +		return -EINVAL;
  20.195 +	}
  20.196 +
  20.197 +	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
  20.198 +		msleep(1);
  20.199 +
  20.200 +	if (ecmd->autoneg == AUTONEG_ENABLE) {
  20.201 +		hw->mac.autoneg = 1;
  20.202 +		if (hw->phy.media_type == e1000_media_type_fiber)
  20.203 +			hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
  20.204 +						     ADVERTISED_FIBRE |
  20.205 +						     ADVERTISED_Autoneg;
  20.206 +		else
  20.207 +			hw->phy.autoneg_advertised = ecmd->advertising |
  20.208 +						     ADVERTISED_TP |
  20.209 +						     ADVERTISED_Autoneg;
  20.210 +		ecmd->advertising = hw->phy.autoneg_advertised;
  20.211 +	} else
  20.212 +		if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
  20.213 +			clear_bit(__IGB_RESETTING, &adapter->state);
  20.214 +			return -EINVAL;
  20.215 +		}
  20.216 +
  20.217 +	/* reset the link */
  20.218 +
  20.219 +	if (netif_running(adapter->netdev)) {
  20.220 +		igb_down(adapter);
  20.221 +		igb_up(adapter);
  20.222 +	} else
  20.223 +		igb_reset(adapter);
  20.224 +
  20.225 +	clear_bit(__IGB_RESETTING, &adapter->state);
  20.226 +	return 0;
  20.227 +}
  20.228 +
  20.229 +static void igb_get_pauseparam(struct net_device *netdev,
  20.230 +			       struct ethtool_pauseparam *pause)
  20.231 +{
  20.232 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.233 +	struct e1000_hw *hw = &adapter->hw;
  20.234 +
  20.235 +	pause->autoneg =
  20.236 +		(adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
  20.237 +
  20.238 +	if (hw->fc.type == e1000_fc_rx_pause)
  20.239 +		pause->rx_pause = 1;
  20.240 +	else if (hw->fc.type == e1000_fc_tx_pause)
  20.241 +		pause->tx_pause = 1;
  20.242 +	else if (hw->fc.type == e1000_fc_full) {
  20.243 +		pause->rx_pause = 1;
  20.244 +		pause->tx_pause = 1;
  20.245 +	}
  20.246 +}
  20.247 +
  20.248 +static int igb_set_pauseparam(struct net_device *netdev,
  20.249 +			      struct ethtool_pauseparam *pause)
  20.250 +{
  20.251 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.252 +	struct e1000_hw *hw = &adapter->hw;
  20.253 +	int retval = 0;
  20.254 +
  20.255 +	adapter->fc_autoneg = pause->autoneg;
  20.256 +
  20.257 +	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
  20.258 +		msleep(1);
  20.259 +
  20.260 +	if (pause->rx_pause && pause->tx_pause)
  20.261 +		hw->fc.type = e1000_fc_full;
  20.262 +	else if (pause->rx_pause && !pause->tx_pause)
  20.263 +		hw->fc.type = e1000_fc_rx_pause;
  20.264 +	else if (!pause->rx_pause && pause->tx_pause)
  20.265 +		hw->fc.type = e1000_fc_tx_pause;
  20.266 +	else if (!pause->rx_pause && !pause->tx_pause)
  20.267 +		hw->fc.type = e1000_fc_none;
  20.268 +
  20.269 +	hw->fc.original_type = hw->fc.type;
  20.270 +
  20.271 +	if (adapter->fc_autoneg == AUTONEG_ENABLE) {
  20.272 +		if (netif_running(adapter->netdev)) {
  20.273 +			igb_down(adapter);
  20.274 +			igb_up(adapter);
  20.275 +		} else
  20.276 +			igb_reset(adapter);
  20.277 +	} else
  20.278 +		retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
  20.279 +			  igb_setup_link(hw) : igb_force_mac_fc(hw));
  20.280 +
  20.281 +	clear_bit(__IGB_RESETTING, &adapter->state);
  20.282 +	return retval;
  20.283 +}
  20.284 +
  20.285 +static u32 igb_get_rx_csum(struct net_device *netdev)
  20.286 +{
  20.287 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.288 +	return adapter->rx_csum;
  20.289 +}
  20.290 +
  20.291 +static int igb_set_rx_csum(struct net_device *netdev, u32 data)
  20.292 +{
  20.293 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.294 +	adapter->rx_csum = data;
  20.295 +
  20.296 +	return 0;
  20.297 +}
  20.298 +
  20.299 +static u32 igb_get_tx_csum(struct net_device *netdev)
  20.300 +{
  20.301 +	return (netdev->features & NETIF_F_HW_CSUM) != 0;
  20.302 +}
  20.303 +
  20.304 +static int igb_set_tx_csum(struct net_device *netdev, u32 data)
  20.305 +{
  20.306 +	if (data)
  20.307 +		netdev->features |= NETIF_F_HW_CSUM;
  20.308 +	else
  20.309 +		netdev->features &= ~NETIF_F_HW_CSUM;
  20.310 +
  20.311 +	return 0;
  20.312 +}
  20.313 +
  20.314 +static int igb_set_tso(struct net_device *netdev, u32 data)
  20.315 +{
  20.316 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.317 +
  20.318 +	if (data)
  20.319 +		netdev->features |= NETIF_F_TSO;
  20.320 +	else
  20.321 +		netdev->features &= ~NETIF_F_TSO;
  20.322 +
  20.323 +	if (data)
  20.324 +		netdev->features |= NETIF_F_TSO6;
  20.325 +	else
  20.326 +		netdev->features &= ~NETIF_F_TSO6;
  20.327 +
  20.328 +	dev_info(&adapter->pdev->dev, "TSO is %s\n",
  20.329 +		 data ? "Enabled" : "Disabled");
  20.330 +	return 0;
  20.331 +}
  20.332 +
  20.333 +static u32 igb_get_msglevel(struct net_device *netdev)
  20.334 +{
  20.335 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.336 +	return adapter->msg_enable;
  20.337 +}
  20.338 +
  20.339 +static void igb_set_msglevel(struct net_device *netdev, u32 data)
  20.340 +{
  20.341 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.342 +	adapter->msg_enable = data;
  20.343 +}
  20.344 +
  20.345 +static int igb_get_regs_len(struct net_device *netdev)
  20.346 +{
  20.347 +#define IGB_REGS_LEN 551
  20.348 +	return IGB_REGS_LEN * sizeof(u32);
  20.349 +}
  20.350 +
  20.351 +static void igb_get_regs(struct net_device *netdev,
  20.352 +			 struct ethtool_regs *regs, void *p)
  20.353 +{
  20.354 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.355 +	struct e1000_hw *hw = &adapter->hw;
  20.356 +	u32 *regs_buff = p;
  20.357 +	u8 i;
  20.358 +
  20.359 +	memset(p, 0, IGB_REGS_LEN * sizeof(u32));
  20.360 +
  20.361 +	regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
  20.362 +
  20.363 +	/* General Registers */
  20.364 +	regs_buff[0] = rd32(E1000_CTRL);
  20.365 +	regs_buff[1] = rd32(E1000_STATUS);
  20.366 +	regs_buff[2] = rd32(E1000_CTRL_EXT);
  20.367 +	regs_buff[3] = rd32(E1000_MDIC);
  20.368 +	regs_buff[4] = rd32(E1000_SCTL);
  20.369 +	regs_buff[5] = rd32(E1000_CONNSW);
  20.370 +	regs_buff[6] = rd32(E1000_VET);
  20.371 +	regs_buff[7] = rd32(E1000_LEDCTL);
  20.372 +	regs_buff[8] = rd32(E1000_PBA);
  20.373 +	regs_buff[9] = rd32(E1000_PBS);
  20.374 +	regs_buff[10] = rd32(E1000_FRTIMER);
  20.375 +	regs_buff[11] = rd32(E1000_TCPTIMER);
  20.376 +
  20.377 +	/* NVM Register */
  20.378 +	regs_buff[12] = rd32(E1000_EECD);
  20.379 +
  20.380 +	/* Interrupt */
  20.381 +	regs_buff[13] = rd32(E1000_EICR);
  20.382 +	regs_buff[14] = rd32(E1000_EICS);
  20.383 +	regs_buff[15] = rd32(E1000_EIMS);
  20.384 +	regs_buff[16] = rd32(E1000_EIMC);
  20.385 +	regs_buff[17] = rd32(E1000_EIAC);
  20.386 +	regs_buff[18] = rd32(E1000_EIAM);
  20.387 +	regs_buff[19] = rd32(E1000_ICR);
  20.388 +	regs_buff[20] = rd32(E1000_ICS);
  20.389 +	regs_buff[21] = rd32(E1000_IMS);
  20.390 +	regs_buff[22] = rd32(E1000_IMC);
  20.391 +	regs_buff[23] = rd32(E1000_IAC);
  20.392 +	regs_buff[24] = rd32(E1000_IAM);
  20.393 +	regs_buff[25] = rd32(E1000_IMIRVP);
  20.394 +
  20.395 +	/* Flow Control */
  20.396 +	regs_buff[26] = rd32(E1000_FCAL);
  20.397 +	regs_buff[27] = rd32(E1000_FCAH);
  20.398 +	regs_buff[28] = rd32(E1000_FCTTV);
  20.399 +	regs_buff[29] = rd32(E1000_FCRTL);
  20.400 +	regs_buff[30] = rd32(E1000_FCRTH);
  20.401 +	regs_buff[31] = rd32(E1000_FCRTV);
  20.402 +
  20.403 +	/* Receive */
  20.404 +	regs_buff[32] = rd32(E1000_RCTL);
  20.405 +	regs_buff[33] = rd32(E1000_RXCSUM);
  20.406 +	regs_buff[34] = rd32(E1000_RLPML);
  20.407 +	regs_buff[35] = rd32(E1000_RFCTL);
  20.408 +	regs_buff[36] = rd32(E1000_MRQC);
  20.409 +	regs_buff[37] = rd32(E1000_VMD_CTL);
  20.410 +
  20.411 +	/* Transmit */
  20.412 +	regs_buff[38] = rd32(E1000_TCTL);
  20.413 +	regs_buff[39] = rd32(E1000_TCTL_EXT);
  20.414 +	regs_buff[40] = rd32(E1000_TIPG);
  20.415 +	regs_buff[41] = rd32(E1000_DTXCTL);
  20.416 +
  20.417 +	/* Wake Up */
  20.418 +	regs_buff[42] = rd32(E1000_WUC);
  20.419 +	regs_buff[43] = rd32(E1000_WUFC);
  20.420 +	regs_buff[44] = rd32(E1000_WUS);
  20.421 +	regs_buff[45] = rd32(E1000_IPAV);
  20.422 +	regs_buff[46] = rd32(E1000_WUPL);
  20.423 +
  20.424 +	/* MAC */
  20.425 +	regs_buff[47] = rd32(E1000_PCS_CFG0);
  20.426 +	regs_buff[48] = rd32(E1000_PCS_LCTL);
  20.427 +	regs_buff[49] = rd32(E1000_PCS_LSTAT);
  20.428 +	regs_buff[50] = rd32(E1000_PCS_ANADV);
  20.429 +	regs_buff[51] = rd32(E1000_PCS_LPAB);
  20.430 +	regs_buff[52] = rd32(E1000_PCS_NPTX);
  20.431 +	regs_buff[53] = rd32(E1000_PCS_LPABNP);
  20.432 +
  20.433 +	/* Statistics */
  20.434 +	regs_buff[54] = adapter->stats.crcerrs;
  20.435 +	regs_buff[55] = adapter->stats.algnerrc;
  20.436 +	regs_buff[56] = adapter->stats.symerrs;
  20.437 +	regs_buff[57] = adapter->stats.rxerrc;
  20.438 +	regs_buff[58] = adapter->stats.mpc;
  20.439 +	regs_buff[59] = adapter->stats.scc;
  20.440 +	regs_buff[60] = adapter->stats.ecol;
  20.441 +	regs_buff[61] = adapter->stats.mcc;
  20.442 +	regs_buff[62] = adapter->stats.latecol;
  20.443 +	regs_buff[63] = adapter->stats.colc;
  20.444 +	regs_buff[64] = adapter->stats.dc;
  20.445 +	regs_buff[65] = adapter->stats.tncrs;
  20.446 +	regs_buff[66] = adapter->stats.sec;
  20.447 +	regs_buff[67] = adapter->stats.htdpmc;
  20.448 +	regs_buff[68] = adapter->stats.rlec;
  20.449 +	regs_buff[69] = adapter->stats.xonrxc;
  20.450 +	regs_buff[70] = adapter->stats.xontxc;
  20.451 +	regs_buff[71] = adapter->stats.xoffrxc;
  20.452 +	regs_buff[72] = adapter->stats.xofftxc;
  20.453 +	regs_buff[73] = adapter->stats.fcruc;
  20.454 +	regs_buff[74] = adapter->stats.prc64;
  20.455 +	regs_buff[75] = adapter->stats.prc127;
  20.456 +	regs_buff[76] = adapter->stats.prc255;
  20.457 +	regs_buff[77] = adapter->stats.prc511;
  20.458 +	regs_buff[78] = adapter->stats.prc1023;
  20.459 +	regs_buff[79] = adapter->stats.prc1522;
  20.460 +	regs_buff[80] = adapter->stats.gprc;
  20.461 +	regs_buff[81] = adapter->stats.bprc;
  20.462 +	regs_buff[82] = adapter->stats.mprc;
  20.463 +	regs_buff[83] = adapter->stats.gptc;
  20.464 +	regs_buff[84] = adapter->stats.gorc;
  20.465 +	regs_buff[86] = adapter->stats.gotc;
  20.466 +	regs_buff[88] = adapter->stats.rnbc;
  20.467 +	regs_buff[89] = adapter->stats.ruc;
  20.468 +	regs_buff[90] = adapter->stats.rfc;
  20.469 +	regs_buff[91] = adapter->stats.roc;
  20.470 +	regs_buff[92] = adapter->stats.rjc;
  20.471 +	regs_buff[93] = adapter->stats.mgprc;
  20.472 +	regs_buff[94] = adapter->stats.mgpdc;
  20.473 +	regs_buff[95] = adapter->stats.mgptc;
  20.474 +	regs_buff[96] = adapter->stats.tor;
  20.475 +	regs_buff[98] = adapter->stats.tot;
  20.476 +	regs_buff[100] = adapter->stats.tpr;
  20.477 +	regs_buff[101] = adapter->stats.tpt;
  20.478 +	regs_buff[102] = adapter->stats.ptc64;
  20.479 +	regs_buff[103] = adapter->stats.ptc127;
  20.480 +	regs_buff[104] = adapter->stats.ptc255;
  20.481 +	regs_buff[105] = adapter->stats.ptc511;
  20.482 +	regs_buff[106] = adapter->stats.ptc1023;
  20.483 +	regs_buff[107] = adapter->stats.ptc1522;
  20.484 +	regs_buff[108] = adapter->stats.mptc;
  20.485 +	regs_buff[109] = adapter->stats.bptc;
  20.486 +	regs_buff[110] = adapter->stats.tsctc;
  20.487 +	regs_buff[111] = adapter->stats.iac;
  20.488 +	regs_buff[112] = adapter->stats.rpthc;
  20.489 +	regs_buff[113] = adapter->stats.hgptc;
  20.490 +	regs_buff[114] = adapter->stats.hgorc;
  20.491 +	regs_buff[116] = adapter->stats.hgotc;
  20.492 +	regs_buff[118] = adapter->stats.lenerrs;
  20.493 +	regs_buff[119] = adapter->stats.scvpc;
  20.494 +	regs_buff[120] = adapter->stats.hrmpc;
  20.495 +
  20.496 +	/* These should probably be added to e1000_regs.h instead */
  20.497 +	#define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
  20.498 +	#define E1000_RAL(_i)         (0x05400 + ((_i) * 8))
  20.499 +	#define E1000_RAH(_i)         (0x05404 + ((_i) * 8))
  20.500 +	#define E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
  20.501 +	#define E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
  20.502 +	#define E1000_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
  20.503 +	#define E1000_FFMT_REG(_i)    (0x09000 + ((_i) * 8))
  20.504 +	#define E1000_FFVT_REG(_i)    (0x09800 + ((_i) * 8))
  20.505 +	#define E1000_FFLT_REG(_i)    (0x05F00 + ((_i) * 8))
  20.506 +
  20.507 +	for (i = 0; i < 4; i++)
  20.508 +		regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
  20.509 +	for (i = 0; i < 4; i++)
  20.510 +		regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
  20.511 +	for (i = 0; i < 4; i++)
  20.512 +		regs_buff[129 + i] = rd32(E1000_RDBAL(i));
  20.513 +	for (i = 0; i < 4; i++)
  20.514 +		regs_buff[133 + i] = rd32(E1000_RDBAH(i));
  20.515 +	for (i = 0; i < 4; i++)
  20.516 +		regs_buff[137 + i] = rd32(E1000_RDLEN(i));
  20.517 +	for (i = 0; i < 4; i++)
  20.518 +		regs_buff[141 + i] = rd32(E1000_RDH(i));
  20.519 +	for (i = 0; i < 4; i++)
  20.520 +		regs_buff[145 + i] = rd32(E1000_RDT(i));
  20.521 +	for (i = 0; i < 4; i++)
  20.522 +		regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
  20.523 +
  20.524 +	for (i = 0; i < 10; i++)
  20.525 +		regs_buff[153 + i] = rd32(E1000_EITR(i));
  20.526 +	for (i = 0; i < 8; i++)
  20.527 +		regs_buff[163 + i] = rd32(E1000_IMIR(i));
  20.528 +	for (i = 0; i < 8; i++)
  20.529 +		regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
  20.530 +	for (i = 0; i < 16; i++)
  20.531 +		regs_buff[179 + i] = rd32(E1000_RAL(i));
  20.532 +	for (i = 0; i < 16; i++)
  20.533 +		regs_buff[195 + i] = rd32(E1000_RAH(i));
  20.534 +
  20.535 +	for (i = 0; i < 4; i++)
  20.536 +		regs_buff[211 + i] = rd32(E1000_TDBAL(i));
  20.537 +	for (i = 0; i < 4; i++)
  20.538 +		regs_buff[215 + i] = rd32(E1000_TDBAH(i));
  20.539 +	for (i = 0; i < 4; i++)
  20.540 +		regs_buff[219 + i] = rd32(E1000_TDLEN(i));
  20.541 +	for (i = 0; i < 4; i++)
  20.542 +		regs_buff[223 + i] = rd32(E1000_TDH(i));
  20.543 +	for (i = 0; i < 4; i++)
  20.544 +		regs_buff[227 + i] = rd32(E1000_TDT(i));
  20.545 +	for (i = 0; i < 4; i++)
  20.546 +		regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
  20.547 +	for (i = 0; i < 4; i++)
  20.548 +		regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
  20.549 +	for (i = 0; i < 4; i++)
  20.550 +		regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
  20.551 +	for (i = 0; i < 4; i++)
  20.552 +		regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
  20.553 +
  20.554 +	for (i = 0; i < 4; i++)
  20.555 +		regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
  20.556 +	for (i = 0; i < 4; i++)
  20.557 +		regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
  20.558 +	for (i = 0; i < 32; i++)
  20.559 +		regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
  20.560 +	for (i = 0; i < 128; i++)
  20.561 +		regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
  20.562 +	for (i = 0; i < 128; i++)
  20.563 +		regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
  20.564 +	for (i = 0; i < 4; i++)
  20.565 +		regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
  20.566 +
  20.567 +	regs_buff[547] = rd32(E1000_TDFH);
  20.568 +	regs_buff[548] = rd32(E1000_TDFT);
  20.569 +	regs_buff[549] = rd32(E1000_TDFHS);
  20.570 +	regs_buff[550] = rd32(E1000_TDFPC);
  20.571 +
  20.572 +}
  20.573 +
  20.574 +static int igb_get_eeprom_len(struct net_device *netdev)
  20.575 +{
  20.576 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.577 +	return adapter->hw.nvm.word_size * 2;
  20.578 +}
  20.579 +
  20.580 +static int igb_get_eeprom(struct net_device *netdev,
  20.581 +			  struct ethtool_eeprom *eeprom, u8 *bytes)
  20.582 +{
  20.583 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.584 +	struct e1000_hw *hw = &adapter->hw;
  20.585 +	u16 *eeprom_buff;
  20.586 +	int first_word, last_word;
  20.587 +	int ret_val = 0;
  20.588 +	u16 i;
  20.589 +
  20.590 +	if (eeprom->len == 0)
  20.591 +		return -EINVAL;
  20.592 +
  20.593 +	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
  20.594 +
  20.595 +	first_word = eeprom->offset >> 1;
  20.596 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  20.597 +
  20.598 +	eeprom_buff = kmalloc(sizeof(u16) *
  20.599 +			(last_word - first_word + 1), GFP_KERNEL);
  20.600 +	if (!eeprom_buff)
  20.601 +		return -ENOMEM;
  20.602 +
  20.603 +	if (hw->nvm.type == e1000_nvm_eeprom_spi)
  20.604 +		ret_val = hw->nvm.ops.read_nvm(hw, first_word,
  20.605 +					    last_word - first_word + 1,
  20.606 +					    eeprom_buff);
  20.607 +	else {
  20.608 +		for (i = 0; i < last_word - first_word + 1; i++) {
  20.609 +			ret_val = hw->nvm.ops.read_nvm(hw, first_word + i, 1,
  20.610 +						    &eeprom_buff[i]);
  20.611 +			if (ret_val)
  20.612 +				break;
  20.613 +		}
  20.614 +	}
  20.615 +
  20.616 +	/* Device's eeprom is always little-endian, word addressable */
  20.617 +	for (i = 0; i < last_word - first_word + 1; i++)
  20.618 +		le16_to_cpus(&eeprom_buff[i]);
  20.619 +
  20.620 +	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
  20.621 +			eeprom->len);
  20.622 +	kfree(eeprom_buff);
  20.623 +
  20.624 +	return ret_val;
  20.625 +}
  20.626 +
  20.627 +static int igb_set_eeprom(struct net_device *netdev,
  20.628 +			  struct ethtool_eeprom *eeprom, u8 *bytes)
  20.629 +{
  20.630 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.631 +	struct e1000_hw *hw = &adapter->hw;
  20.632 +	u16 *eeprom_buff;
  20.633 +	void *ptr;
  20.634 +	int max_len, first_word, last_word, ret_val = 0;
  20.635 +	u16 i;
  20.636 +
  20.637 +	if (eeprom->len == 0)
  20.638 +		return -EOPNOTSUPP;
  20.639 +
  20.640 +	if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
  20.641 +		return -EFAULT;
  20.642 +
  20.643 +	max_len = hw->nvm.word_size * 2;
  20.644 +
  20.645 +	first_word = eeprom->offset >> 1;
  20.646 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  20.647 +	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
  20.648 +	if (!eeprom_buff)
  20.649 +		return -ENOMEM;
  20.650 +
  20.651 +	ptr = (void *)eeprom_buff;
  20.652 +
  20.653 +	if (eeprom->offset & 1) {
  20.654 +		/* need read/modify/write of first changed EEPROM word */
  20.655 +		/* only the second byte of the word is being modified */
  20.656 +		ret_val = hw->nvm.ops.read_nvm(hw, first_word, 1,
  20.657 +					    &eeprom_buff[0]);
  20.658 +		ptr++;
  20.659 +	}
  20.660 +	if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
  20.661 +		/* need read/modify/write of last changed EEPROM word */
  20.662 +		/* only the first byte of the word is being modified */
  20.663 +		ret_val = hw->nvm.ops.read_nvm(hw, last_word, 1,
  20.664 +				   &eeprom_buff[last_word - first_word]);
  20.665 +	}
  20.666 +
  20.667 +	/* Device's eeprom is always little-endian, word addressable */
  20.668 +	for (i = 0; i < last_word - first_word + 1; i++)
  20.669 +		le16_to_cpus(&eeprom_buff[i]);
  20.670 +
  20.671 +	memcpy(ptr, bytes, eeprom->len);
  20.672 +
  20.673 +	for (i = 0; i < last_word - first_word + 1; i++)
  20.674 +		eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
  20.675 +
  20.676 +	ret_val = hw->nvm.ops.write_nvm(hw, first_word,
  20.677 +				     last_word - first_word + 1, eeprom_buff);
  20.678 +
  20.679 +	/* Update the checksum over the first part of the EEPROM if needed
  20.680 +	 * and flush shadow RAM for 82573 controllers */
  20.681 +	if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
  20.682 +		igb_update_nvm_checksum(hw);
  20.683 +
  20.684 +	kfree(eeprom_buff);
  20.685 +	return ret_val;
  20.686 +}
  20.687 +
  20.688 +static void igb_get_drvinfo(struct net_device *netdev,
  20.689 +			    struct ethtool_drvinfo *drvinfo)
  20.690 +{
  20.691 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.692 +	char firmware_version[32];
  20.693 +	u16 eeprom_data;
  20.694 +
  20.695 +	strncpy(drvinfo->driver,  igb_driver_name, 32);
  20.696 +	strncpy(drvinfo->version, igb_driver_version, 32);
  20.697 +
  20.698 +	/* EEPROM image version # is reported as firmware version # for
  20.699 +	 * 82575 controllers */
  20.700 +	adapter->hw.nvm.ops.read_nvm(&adapter->hw, 5, 1, &eeprom_data);
  20.701 +	sprintf(firmware_version, "%d.%d-%d",
  20.702 +		(eeprom_data & 0xF000) >> 12,
  20.703 +		(eeprom_data & 0x0FF0) >> 4,
  20.704 +		eeprom_data & 0x000F);
  20.705 +
  20.706 +	strncpy(drvinfo->fw_version, firmware_version, 32);
  20.707 +	strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
  20.708 +	drvinfo->n_stats = IGB_STATS_LEN;
  20.709 +	drvinfo->testinfo_len = IGB_TEST_LEN;
  20.710 +	drvinfo->regdump_len = igb_get_regs_len(netdev);
  20.711 +	drvinfo->eedump_len = igb_get_eeprom_len(netdev);
  20.712 +}
  20.713 +
  20.714 +static void igb_get_ringparam(struct net_device *netdev,
  20.715 +			      struct ethtool_ringparam *ring)
  20.716 +{
  20.717 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.718 +	struct igb_ring *tx_ring = adapter->tx_ring;
  20.719 +	struct igb_ring *rx_ring = adapter->rx_ring;
  20.720 +
  20.721 +	ring->rx_max_pending = IGB_MAX_RXD;
  20.722 +	ring->tx_max_pending = IGB_MAX_TXD;
  20.723 +	ring->rx_mini_max_pending = 0;
  20.724 +	ring->rx_jumbo_max_pending = 0;
  20.725 +	ring->rx_pending = rx_ring->count;
  20.726 +	ring->tx_pending = tx_ring->count;
  20.727 +	ring->rx_mini_pending = 0;
  20.728 +	ring->rx_jumbo_pending = 0;
  20.729 +}
  20.730 +
  20.731 +static int igb_set_ringparam(struct net_device *netdev,
  20.732 +			     struct ethtool_ringparam *ring)
  20.733 +{
  20.734 +	struct igb_adapter *adapter = netdev_priv(netdev);
  20.735 +	struct igb_buffer *old_buf;
  20.736 +	struct igb_buffer *old_rx_buf;
  20.737 +	void *old_desc;
  20.738 +	int i, err;
  20.739 +	u32 new_rx_count, new_tx_count, old_size;
  20.740 +	dma_addr_t old_dma;
  20.741 +
  20.742 +	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
  20.743 +		return -EINVAL;
  20.744 +
  20.745 +	new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
  20.746 +	new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
  20.747 +	new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
  20.748 +
  20.749 +	new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
  20.750 +	new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
  20.751 +	new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
  20.752 +
  20.753 +	if ((new_tx_count == adapter->tx_ring->count) &&
  20.754 +	    (new_rx_count == adapter->rx_ring->count)) {
  20.755 +		/* nothing to do */
  20.756 +		return 0;
  20.757 +	}
  20.758 +
  20.759 +	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
  20.760 +		msleep(1);
  20.761 +
  20.762 +	if (netif_running(adapter->netdev))
  20.763 +		igb_down(adapter);
  20.764 +
  20.765 +	/*
  20.766 +	 * We can't just free everything and then setup again,
  20.767 +	 * because the ISRs in MSI-X mode get passed pointers
  20.768 +	 * to the tx and rx ring structs.
  20.769 +	 */
  20.770 +	if (new_tx_count != adapter->tx_ring->count) {
  20.771 +		for (i = 0; i < adapter->num_tx_queues; i++) {
  20.772 +			/* Save existing descriptor ring */
  20.773 +			old_buf = adapter->tx_ring[i].buffer_info;
  20.774 +			old_desc = adapter->tx_ring[i].desc;
  20.775 +			old_size = adapter->tx_ring[i].size;
  20.776 +			old_dma = adapter->tx_ring[i].dma;
  20.777 +			/* Try to allocate a new one */
  20.778 +			adapter->tx_ring[i].buffer_info = NULL;
  20.779 +			adapter->tx_ring[i].desc = NULL;
  20.780 +			adapter->tx_ring[i].count = new_tx_count;
  20.781 +			err = igb_setup_tx_resources(adapter,
  20.782 +						&adapter->tx_ring[i]);
  20.783 +			if (err) {
  20.784 +				/* Restore the old one so at least
  20.785 +				   the adapter still works, even if
  20.786 +				   we failed the request */
  20.787 +				adapter->tx_ring[i].buffer_info = old_buf;
  20.788 +				adapter->tx_ring[i].desc = old_desc;
  20.789 +				adapter->tx_ring[i].size = old_size;
  20.790 +				adapter->tx_ring[i].dma = old_dma;
  20.791 +				goto err_setup;
  20.792 +			}
  20.793 +			/* Free the old buffer manually */
  20.794 +			vfree(old_buf);
  20.795 +			pci_free_consistent(adapter->pdev, old_size,
  20.796 +					    old_desc, old_dma);
  20.797 +		}
  20.798 +	}
  20.799 +
  20.800 +	if (new_rx_count != adapter->rx_ring->count) {
  20.801 +		for (i = 0; i < adapter->num_rx_queues; i++) {
  20.802 +
  20.803 +			old_rx_buf = adapter->rx_ring[i].buffer_info;
  20.804 +			old_desc = adapter->rx_ring[i].desc;
  20.805 +			old_size = adapter->rx_ring[i].size;
  20.806 +			old_dma = adapter->rx_ring[i].dma;
  20.807 +
  20.808 +			adapter->rx_ring[i].buffer_info = NULL;
  20.809 +			adapter->rx_ring[i].desc = NULL;
  20.810 +			adapter->rx_ring[i].dma = 0;
  20.811 +			adapter->rx_ring[i].count = new_rx_count;
  20.812 +			err = igb_setup_rx_resources(adapter,
  20.813 +						     &adapter->rx_ring[i]);
  20.814 +			if (err) {
  20.815 +				adapter->rx_ring[i].buffer_info = old_rx_buf;
  20.816 +				adapter->rx_ring[i].desc = old_desc;
  20.817 +				adapter->rx_ring[i].size = old_size;
  20.818 +				adapter->rx_ring[i].dma = old_dma;
  20.819 +				goto err_setup;
  20.820 +			}
  20.821 +
  20.822 +			vfree(old_rx_buf);
  20.823 +			pci_free_consistent(adapter->pdev, old_size, old_desc,
  20.824 +					    old_dma);
  20.825 +		}
  20.826 +	}
  20.827 +
  20.828 +	err = 0;
  20.829 +err_setup:
  20.830 +	if (netif_running(adapter->netdev))
  20.831 +		igb_up(adapter);
  20.832 +
  20.833 +	clear_bit(__IGB_RESETTING, &adapter->state);
  20.834 +	return err;
  20.835 +}
  20.836 +
  20.837 +/* ethtool register test data */
  20.838 +struct igb_reg_test {
  20.839 +	u16 reg;
  20.840 +	u16 reg_offset;
  20.841 +	u16 array_len;
  20.842 +	u16 test_type;
  20.843 +	u32 mask;
  20.844 +	u32 write;
  20.845 +};
  20.846 +
  20.847 +/* In the hardware, registers are laid out either singly, in arrays
  20.848 + * spaced 0x100 bytes apart, or in contiguous tables.  We assume
  20.849 + * most tests take place on arrays or single registers (handled
  20.850 + * as a single-element array) and special-case the tables.
  20.851 + * Table tests are always pattern tests.
  20.852 + *
  20.853 + * We also make provision for some required setup steps by specifying
  20.854 + * registers to be written without any read-back testing.
  20.855 + */
  20.856 +
  20.857 +#define PATTERN_TEST	1
  20.858 +#define SET_READ_TEST	2
  20.859 +#define WRITE_NO_TEST	3
  20.860 +#define TABLE32_TEST	4
  20.861 +#define TABLE64_TEST_LO	5
  20.862 +#define TABLE64_TEST_HI	6
  20.863 +
  20.864 +/* 82576 reg test */
  20.865 +static struct igb_reg_test reg_test_82576[] = {
  20.866 +	{ E1000_FCAL,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.867 +	{ E1000_FCAH,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  20.868 +	{ E1000_FCT,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  20.869 +	{ E1000_VET,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.870 +	{ E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  20.871 +	{ E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.872 +	{ E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
  20.873 +	{ E1000_RDBAL(4),  0x40,  8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  20.874 +	{ E1000_RDBAH(4),  0x40,  8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.875 +	{ E1000_RDLEN(4),  0x40,  8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
  20.876 +	/* Enable all four RX queues before testing. */
  20.877 +	{ E1000_RXDCTL(0), 0x100, 1,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
  20.878 +	/* RDH is read-only for 82576, only test RDT. */
  20.879 +	{ E1000_RDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  20.880 +	{ E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
  20.881 +	{ E1000_FCRTH,	   0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
  20.882 +	{ E1000_FCTTV,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  20.883 +	{ E1000_TIPG,	   0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
  20.884 +	{ E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  20.885 +	{ E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.886 +	{ E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
  20.887 +	{ E1000_TDBAL(4),  0x40, 8,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  20.888 +	{ E1000_TDBAH(4),  0x40, 8,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.889 +	{ E1000_TDLEN(4),  0x40, 8,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
  20.890 +	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  20.891 +	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
  20.892 +	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
  20.893 +	{ E1000_TCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  20.894 +	{ E1000_RA,	   0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
  20.895 +	{ E1000_RA,	   0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
  20.896 +	{ E1000_RA2,	   0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
  20.897 +	{ E1000_RA2,	   0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
  20.898 +	{ E1000_MTA,	   0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.899 +	{ 0, 0, 0, 0 }
  20.900 +};
  20.901 +
  20.902 +/* 82575 register test */
  20.903 +static struct igb_reg_test reg_test_82575[] = {
  20.904 +	{ E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.905 +	{ E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  20.906 +	{ E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  20.907 +	{ E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.908 +	{ E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  20.909 +	{ E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.910 +	{ E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  20.911 +	/* Enable all four RX queues before testing. */
  20.912 +	{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
  20.913 +	/* RDH is read-only for 82575, only test RDT. */
  20.914 +	{ E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  20.915 +	{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
  20.916 +	{ E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
  20.917 +	{ E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  20.918 +	{ E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
  20.919 +	{ E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  20.920 +	{ E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.921 +	{ E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  20.922 +	{ E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  20.923 +	{ E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
  20.924 +	{ E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
  20.925 +	{ E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  20.926 +	{ E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
  20.927 +	{ E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
  20.928 +	{ E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
  20.929 +	{ E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  20.930 +	{ 0, 0, 0, 0 }
  20.931 +};
  20.932 +
  20.933 +static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
  20.934 +			     int reg, u32 mask, u32 write)
  20.935 +{
  20.936 +	u32 pat, val;
  20.937 +	u32 _test[] =
  20.938 +		{0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
  20.939 +	for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
  20.940 +		writel((_test[pat] & write), (adapter->hw.hw_addr + reg));
  20.941 +		val = readl(adapter->hw.hw_addr + reg);
  20.942 +		if (val != (_test[pat] & write & mask)) {
  20.943 +			dev_err(&adapter->pdev->dev, "pattern test reg %04X "
  20.944 +				"failed: got 0x%08X expected 0x%08X\n",
  20.945 +				reg, val, (_test[pat] & write & mask));
  20.946 +			*data = reg;
  20.947 +			return 1;
  20.948 +		}
  20.949 +	}
  20.950 +	return 0;
  20.951 +}
  20.952 +
  20.953 +static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
  20.954 +			      int reg, u32 mask, u32 write)
  20.955 +{
  20.956 +	u32 val;
  20.957 +	writel((write & mask), (adapter->hw.hw_addr + reg));
  20.958 +	val = readl(adapter->hw.hw_addr + reg);
  20.959 +	if ((write & mask) != (val & mask)) {
  20.960 +		dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
  20.961 +			" got 0x%08X expected 0x%08X\n", reg,
  20.962 +			(val & mask), (write & mask));
  20.963 +		*data = reg;
  20.964 +		return 1;
  20.965 +	}
  20.966 +	return 0;
  20.967 +}
  20.968 +
  20.969 +#define REG_PATTERN_TEST(reg, mask, write) \
  20.970 +	do { \
  20.971 +		if (reg_pattern_test(adapter, data, reg, mask, write)) \
  20.972 +			return 1; \
  20.973 +	} while (0)
  20.974 +
  20.975 +#define REG_SET_AND_CHECK(reg, mask, write) \
  20.976 +	do { \
  20.977 +		if (reg_set_and_check(adapter, data, reg, mask, write)) \
  20.978 +			return 1; \
  20.979 +	} while (0)
  20.980 +
  20.981 +static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
  20.982 +{
  20.983 +	struct e1000_hw *hw = &adapter->hw;
  20.984 +	struct igb_reg_test *test;
  20.985 +	u32 value, before, after;
  20.986 +	u32 i, toggle;
  20.987 +
  20.988 +	toggle = 0x7FFFF3FF;
  20.989 +
  20.990 +	switch (adapter->hw.mac.type) {
  20.991 +	case e1000_82576:
  20.992 +		test = reg_test_82576;
  20.993 +		break;
  20.994 +	default:
  20.995 +		test = reg_test_82575;
  20.996 +		break;
  20.997 +	}
  20.998 +
  20.999 +	/* Because the status register is such a special case,
 20.1000 +	 * we handle it separately from the rest of the register
 20.1001 +	 * tests.  Some bits are read-only, some toggle, and some
 20.1002 +	 * are writable on newer MACs.
 20.1003 +	 */
 20.1004 +	before = rd32(E1000_STATUS);
 20.1005 +	value = (rd32(E1000_STATUS) & toggle);
 20.1006 +	wr32(E1000_STATUS, toggle);
 20.1007 +	after = rd32(E1000_STATUS) & toggle;
 20.1008 +	if (value != after) {
 20.1009 +		dev_err(&adapter->pdev->dev, "failed STATUS register test "
 20.1010 +			"got: 0x%08X expected: 0x%08X\n", after, value);
 20.1011 +		*data = 1;
 20.1012 +		return 1;
 20.1013 +	}
 20.1014 +	/* restore previous status */
 20.1015 +	wr32(E1000_STATUS, before);
 20.1016 +
 20.1017 +	/* Perform the remainder of the register test, looping through
 20.1018 +	 * the test table until we either fail or reach the null entry.
 20.1019 +	 */
 20.1020 +	while (test->reg) {
 20.1021 +		for (i = 0; i < test->array_len; i++) {
 20.1022 +			switch (test->test_type) {
 20.1023 +			case PATTERN_TEST:
 20.1024 +				REG_PATTERN_TEST(test->reg + (i * test->reg_offset),
 20.1025 +						test->mask,
 20.1026 +						test->write);
 20.1027 +				break;
 20.1028 +			case SET_READ_TEST:
 20.1029 +				REG_SET_AND_CHECK(test->reg + (i * test->reg_offset),
 20.1030 +						test->mask,
 20.1031 +						test->write);
 20.1032 +				break;
 20.1033 +			case WRITE_NO_TEST:
 20.1034 +				writel(test->write,
 20.1035 +				    (adapter->hw.hw_addr + test->reg)
 20.1036 +					+ (i * test->reg_offset));
 20.1037 +				break;
 20.1038 +			case TABLE32_TEST:
 20.1039 +				REG_PATTERN_TEST(test->reg + (i * 4),
 20.1040 +						test->mask,
 20.1041 +						test->write);
 20.1042 +				break;
 20.1043 +			case TABLE64_TEST_LO:
 20.1044 +				REG_PATTERN_TEST(test->reg + (i * 8),
 20.1045 +						test->mask,
 20.1046 +						test->write);
 20.1047 +				break;
 20.1048 +			case TABLE64_TEST_HI:
 20.1049 +				REG_PATTERN_TEST((test->reg + 4) + (i * 8),
 20.1050 +						test->mask,
 20.1051 +						test->write);
 20.1052 +				break;
 20.1053 +			}
 20.1054 +		}
 20.1055 +		test++;
 20.1056 +	}
 20.1057 +
 20.1058 +	*data = 0;
 20.1059 +	return 0;
 20.1060 +}
 20.1061 +
 20.1062 +static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
 20.1063 +{
 20.1064 +	u16 temp;
 20.1065 +	u16 checksum = 0;
 20.1066 +	u16 i;
 20.1067 +
 20.1068 +	*data = 0;
 20.1069 +	/* Read and add up the contents of the EEPROM */
 20.1070 +	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
 20.1071 +		if ((adapter->hw.nvm.ops.read_nvm(&adapter->hw, i, 1, &temp))
 20.1072 +		    < 0) {
 20.1073 +			*data = 1;
 20.1074 +			break;
 20.1075 +		}
 20.1076 +		checksum += temp;
 20.1077 +	}
 20.1078 +
 20.1079 +	/* If Checksum is not Correct return error else test passed */
 20.1080 +	if ((checksum != (u16) NVM_SUM) && !(*data))
 20.1081 +		*data = 2;
 20.1082 +
 20.1083 +	return *data;
 20.1084 +}
 20.1085 +
 20.1086 +static irqreturn_t igb_test_intr(int irq, void *data, struct pt_regs *regs)
 20.1087 +{
 20.1088 +	struct net_device *netdev = (struct net_device *) data;
 20.1089 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1090 +	struct e1000_hw *hw = &adapter->hw;
 20.1091 +
 20.1092 +	adapter->test_icr |= rd32(E1000_ICR);
 20.1093 +
 20.1094 +	return IRQ_HANDLED;
 20.1095 +}
 20.1096 +
 20.1097 +static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
 20.1098 +{
 20.1099 +	struct e1000_hw *hw = &adapter->hw;
 20.1100 +	struct net_device *netdev = adapter->netdev;
 20.1101 +	u32 mask, i = 0, shared_int = true;
 20.1102 +	u32 irq = adapter->pdev->irq;
 20.1103 +
 20.1104 +	*data = 0;
 20.1105 +
 20.1106 +	/* Hook up test interrupt handler just for this test */
 20.1107 +	if (adapter->msix_entries) {
 20.1108 +		/* NOTE: we don't test MSI-X interrupts here, yet */
 20.1109 +		return 0;
 20.1110 +	} else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 20.1111 +		shared_int = false;
 20.1112 +		if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
 20.1113 +			*data = 1;
 20.1114 +			return -1;
 20.1115 +		}
 20.1116 +	} else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
 20.1117 +				netdev->name, netdev)) {
 20.1118 +		shared_int = false;
 20.1119 +	} else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
 20.1120 +		 netdev->name, netdev)) {
 20.1121 +		*data = 1;
 20.1122 +		return -1;
 20.1123 +	}
 20.1124 +	dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
 20.1125 +		(shared_int ? "shared" : "unshared"));
 20.1126 +
 20.1127 +	/* Disable all the interrupts */
 20.1128 +	wr32(E1000_IMC, 0xFFFFFFFF);
 20.1129 +	msleep(10);
 20.1130 +
 20.1131 +	/* Test each interrupt */
 20.1132 +	for (; i < 10; i++) {
 20.1133 +		/* Interrupt to test */
 20.1134 +		mask = 1 << i;
 20.1135 +
 20.1136 +		if (!shared_int) {
 20.1137 +			/* Disable the interrupt to be reported in
 20.1138 +			 * the cause register and then force the same
 20.1139 +			 * interrupt and see if one gets posted.  If
 20.1140 +			 * an interrupt was posted to the bus, the
 20.1141 +			 * test failed.
 20.1142 +			 */
 20.1143 +			adapter->test_icr = 0;
 20.1144 +			wr32(E1000_IMC, ~mask & 0x00007FFF);
 20.1145 +			wr32(E1000_ICS, ~mask & 0x00007FFF);
 20.1146 +			msleep(10);
 20.1147 +
 20.1148 +			if (adapter->test_icr & mask) {
 20.1149 +				*data = 3;
 20.1150 +				break;
 20.1151 +			}
 20.1152 +		}
 20.1153 +
 20.1154 +		/* Enable the interrupt to be reported in
 20.1155 +		 * the cause register and then force the same
 20.1156 +		 * interrupt and see if one gets posted.  If
 20.1157 +		 * an interrupt was not posted to the bus, the
 20.1158 +		 * test failed.
 20.1159 +		 */
 20.1160 +		adapter->test_icr = 0;
 20.1161 +		wr32(E1000_IMS, mask);
 20.1162 +		wr32(E1000_ICS, mask);
 20.1163 +		msleep(10);
 20.1164 +
 20.1165 +		if (!(adapter->test_icr & mask)) {
 20.1166 +			*data = 4;
 20.1167 +			break;
 20.1168 +		}
 20.1169 +
 20.1170 +		if (!shared_int) {
 20.1171 +			/* Disable the other interrupts to be reported in
 20.1172 +			 * the cause register and then force the other
 20.1173 +			 * interrupts and see if any get posted.  If
 20.1174 +			 * an interrupt was posted to the bus, the
 20.1175 +			 * test failed.
 20.1176 +			 */
 20.1177 +			adapter->test_icr = 0;
 20.1178 +			wr32(E1000_IMC, ~mask & 0x00007FFF);
 20.1179 +			wr32(E1000_ICS, ~mask & 0x00007FFF);
 20.1180 +			msleep(10);
 20.1181 +
 20.1182 +			if (adapter->test_icr) {
 20.1183 +				*data = 5;
 20.1184 +				break;
 20.1185 +			}
 20.1186 +		}
 20.1187 +	}
 20.1188 +
 20.1189 +	/* Disable all the interrupts */
 20.1190 +	wr32(E1000_IMC, 0xFFFFFFFF);
 20.1191 +	msleep(10);
 20.1192 +
 20.1193 +	/* Unhook test interrupt handler */
 20.1194 +	free_irq(irq, netdev);
 20.1195 +
 20.1196 +	return *data;
 20.1197 +}
 20.1198 +
 20.1199 +static void igb_free_desc_rings(struct igb_adapter *adapter)
 20.1200 +{
 20.1201 +	struct igb_ring *tx_ring = &adapter->test_tx_ring;
 20.1202 +	struct igb_ring *rx_ring = &adapter->test_rx_ring;
 20.1203 +	struct pci_dev *pdev = adapter->pdev;
 20.1204 +	int i;
 20.1205 +
 20.1206 +	if (tx_ring->desc && tx_ring->buffer_info) {
 20.1207 +		for (i = 0; i < tx_ring->count; i++) {
 20.1208 +			struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
 20.1209 +			if (buf->dma)
 20.1210 +				pci_unmap_single(pdev, buf->dma, buf->length,
 20.1211 +						 PCI_DMA_TODEVICE);
 20.1212 +			if (buf->skb)
 20.1213 +				dev_kfree_skb(buf->skb);
 20.1214 +		}
 20.1215 +	}
 20.1216 +
 20.1217 +	if (rx_ring->desc && rx_ring->buffer_info) {
 20.1218 +		for (i = 0; i < rx_ring->count; i++) {
 20.1219 +			struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
 20.1220 +			if (buf->dma)
 20.1221 +				pci_unmap_single(pdev, buf->dma,
 20.1222 +						 IGB_RXBUFFER_2048,
 20.1223 +						 PCI_DMA_FROMDEVICE);
 20.1224 +			if (buf->skb)
 20.1225 +				dev_kfree_skb(buf->skb);
 20.1226 +		}
 20.1227 +	}
 20.1228 +
 20.1229 +	if (tx_ring->desc) {
 20.1230 +		pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
 20.1231 +				    tx_ring->dma);
 20.1232 +		tx_ring->desc = NULL;
 20.1233 +	}
 20.1234 +	if (rx_ring->desc) {
 20.1235 +		pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
 20.1236 +				    rx_ring->dma);
 20.1237 +		rx_ring->desc = NULL;
 20.1238 +	}
 20.1239 +
 20.1240 +	kfree(tx_ring->buffer_info);
 20.1241 +	tx_ring->buffer_info = NULL;
 20.1242 +	kfree(rx_ring->buffer_info);
 20.1243 +	rx_ring->buffer_info = NULL;
 20.1244 +
 20.1245 +	return;
 20.1246 +}
 20.1247 +
 20.1248 +static int igb_setup_desc_rings(struct igb_adapter *adapter)
 20.1249 +{
 20.1250 +	struct e1000_hw *hw = &adapter->hw;
 20.1251 +	struct igb_ring *tx_ring = &adapter->test_tx_ring;
 20.1252 +	struct igb_ring *rx_ring = &adapter->test_rx_ring;
 20.1253 +	struct pci_dev *pdev = adapter->pdev;
 20.1254 +	u32 rctl;
 20.1255 +	int i, ret_val;
 20.1256 +
 20.1257 +	/* Setup Tx descriptor ring and Tx buffers */
 20.1258 +
 20.1259 +	if (!tx_ring->count)
 20.1260 +		tx_ring->count = IGB_DEFAULT_TXD;
 20.1261 +
 20.1262 +	tx_ring->buffer_info = kcalloc(tx_ring->count,
 20.1263 +				       sizeof(struct igb_buffer),
 20.1264 +				       GFP_KERNEL);
 20.1265 +	if (!tx_ring->buffer_info) {
 20.1266 +		ret_val = 1;
 20.1267 +		goto err_nomem;
 20.1268 +	}
 20.1269 +
 20.1270 +	tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
 20.1271 +	tx_ring->size = ALIGN(tx_ring->size, 4096);
 20.1272 +	tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
 20.1273 +					     &tx_ring->dma);
 20.1274 +	if (!tx_ring->desc) {
 20.1275 +		ret_val = 2;
 20.1276 +		goto err_nomem;
 20.1277 +	}
 20.1278 +	tx_ring->next_to_use = tx_ring->next_to_clean = 0;
 20.1279 +
 20.1280 +	wr32(E1000_TDBAL(0),
 20.1281 +			((u64) tx_ring->dma & 0x00000000FFFFFFFF));
 20.1282 +	wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
 20.1283 +	wr32(E1000_TDLEN(0),
 20.1284 +			tx_ring->count * sizeof(struct e1000_tx_desc));
 20.1285 +	wr32(E1000_TDH(0), 0);
 20.1286 +	wr32(E1000_TDT(0), 0);
 20.1287 +	wr32(E1000_TCTL,
 20.1288 +			E1000_TCTL_PSP | E1000_TCTL_EN |
 20.1289 +			E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
 20.1290 +			E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
 20.1291 +
 20.1292 +	for (i = 0; i < tx_ring->count; i++) {
 20.1293 +		struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
 20.1294 +		struct sk_buff *skb;
 20.1295 +		unsigned int size = 1024;
 20.1296 +
 20.1297 +		skb = alloc_skb(size, GFP_KERNEL);
 20.1298 +		if (!skb) {
 20.1299 +			ret_val = 3;
 20.1300 +			goto err_nomem;
 20.1301 +		}
 20.1302 +		skb_put(skb, size);
 20.1303 +		tx_ring->buffer_info[i].skb = skb;
 20.1304 +		tx_ring->buffer_info[i].length = skb->len;
 20.1305 +		tx_ring->buffer_info[i].dma =
 20.1306 +			pci_map_single(pdev, skb->data, skb->len,
 20.1307 +				       PCI_DMA_TODEVICE);
 20.1308 +		tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
 20.1309 +		tx_desc->lower.data = cpu_to_le32(skb->len);
 20.1310 +		tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
 20.1311 +						   E1000_TXD_CMD_IFCS |
 20.1312 +						   E1000_TXD_CMD_RS);
 20.1313 +		tx_desc->upper.data = 0;
 20.1314 +	}
 20.1315 +
 20.1316 +	/* Setup Rx descriptor ring and Rx buffers */
 20.1317 +
 20.1318 +	if (!rx_ring->count)
 20.1319 +		rx_ring->count = IGB_DEFAULT_RXD;
 20.1320 +
 20.1321 +	rx_ring->buffer_info = kcalloc(rx_ring->count,
 20.1322 +				       sizeof(struct igb_buffer),
 20.1323 +				       GFP_KERNEL);
 20.1324 +	if (!rx_ring->buffer_info) {
 20.1325 +		ret_val = 4;
 20.1326 +		goto err_nomem;
 20.1327 +	}
 20.1328 +
 20.1329 +	rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
 20.1330 +	rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
 20.1331 +					     &rx_ring->dma);
 20.1332 +	if (!rx_ring->desc) {
 20.1333 +		ret_val = 5;
 20.1334 +		goto err_nomem;
 20.1335 +	}
 20.1336 +	rx_ring->next_to_use = rx_ring->next_to_clean = 0;
 20.1337 +
 20.1338 +	rctl = rd32(E1000_RCTL);
 20.1339 +	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 20.1340 +	wr32(E1000_RDBAL(0),
 20.1341 +			((u64) rx_ring->dma & 0xFFFFFFFF));
 20.1342 +	wr32(E1000_RDBAH(0),
 20.1343 +			((u64) rx_ring->dma >> 32));
 20.1344 +	wr32(E1000_RDLEN(0), rx_ring->size);
 20.1345 +	wr32(E1000_RDH(0), 0);
 20.1346 +	wr32(E1000_RDT(0), 0);
 20.1347 +	rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
 20.1348 +		E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
 20.1349 +		(adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
 20.1350 +	wr32(E1000_RCTL, rctl);
 20.1351 +	wr32(E1000_SRRCTL(0), 0);
 20.1352 +
 20.1353 +	for (i = 0; i < rx_ring->count; i++) {
 20.1354 +		struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
 20.1355 +		struct sk_buff *skb;
 20.1356 +
 20.1357 +		skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
 20.1358 +				GFP_KERNEL);
 20.1359 +		if (!skb) {
 20.1360 +			ret_val = 6;
 20.1361 +			goto err_nomem;
 20.1362 +		}
 20.1363 +		skb_reserve(skb, NET_IP_ALIGN);
 20.1364 +		rx_ring->buffer_info[i].skb = skb;
 20.1365 +		rx_ring->buffer_info[i].dma =
 20.1366 +			pci_map_single(pdev, skb->data, IGB_RXBUFFER_2048,
 20.1367 +				       PCI_DMA_FROMDEVICE);
 20.1368 +		rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
 20.1369 +		memset(skb->data, 0x00, skb->len);
 20.1370 +	}
 20.1371 +
 20.1372 +	return 0;
 20.1373 +
 20.1374 +err_nomem:
 20.1375 +	igb_free_desc_rings(adapter);
 20.1376 +	return ret_val;
 20.1377 +}
 20.1378 +
 20.1379 +static void igb_phy_disable_receiver(struct igb_adapter *adapter)
 20.1380 +{
 20.1381 +	struct e1000_hw *hw = &adapter->hw;
 20.1382 +
 20.1383 +	/* Write out to PHY registers 29 and 30 to disable the Receiver. */
 20.1384 +	hw->phy.ops.write_phy_reg(hw, 29, 0x001F);
 20.1385 +	hw->phy.ops.write_phy_reg(hw, 30, 0x8FFC);
 20.1386 +	hw->phy.ops.write_phy_reg(hw, 29, 0x001A);
 20.1387 +	hw->phy.ops.write_phy_reg(hw, 30, 0x8FF0);
 20.1388 +}
 20.1389 +
 20.1390 +static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
 20.1391 +{
 20.1392 +	struct e1000_hw *hw = &adapter->hw;
 20.1393 +	u32 ctrl_reg = 0;
 20.1394 +	u32 stat_reg = 0;
 20.1395 +
 20.1396 +	hw->mac.autoneg = false;
 20.1397 +
 20.1398 +	if (hw->phy.type == e1000_phy_m88) {
 20.1399 +		/* Auto-MDI/MDIX Off */
 20.1400 +		hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
 20.1401 +		/* reset to update Auto-MDI/MDIX */
 20.1402 +		hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x9140);
 20.1403 +		/* autoneg off */
 20.1404 +		hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x8140);
 20.1405 +	}
 20.1406 +
 20.1407 +	ctrl_reg = rd32(E1000_CTRL);
 20.1408 +
 20.1409 +	/* force 1000, set loopback */
 20.1410 +	hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x4140);
 20.1411 +
 20.1412 +	/* Now set up the MAC to the same speed/duplex as the PHY. */
 20.1413 +	ctrl_reg = rd32(E1000_CTRL);
 20.1414 +	ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
 20.1415 +	ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
 20.1416 +		     E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
 20.1417 +		     E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
 20.1418 +		     E1000_CTRL_FD);	 /* Force Duplex to FULL */
 20.1419 +
 20.1420 +	if (hw->phy.media_type == e1000_media_type_copper &&
 20.1421 +	    hw->phy.type == e1000_phy_m88)
 20.1422 +		ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
 20.1423 +	else {
 20.1424 +		/* Set the ILOS bit on the fiber Nic if half duplex link is
 20.1425 +		 * detected. */
 20.1426 +		stat_reg = rd32(E1000_STATUS);
 20.1427 +		if ((stat_reg & E1000_STATUS_FD) == 0)
 20.1428 +			ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
 20.1429 +	}
 20.1430 +
 20.1431 +	wr32(E1000_CTRL, ctrl_reg);
 20.1432 +
 20.1433 +	/* Disable the receiver on the PHY so when a cable is plugged in, the
 20.1434 +	 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
 20.1435 +	 */
 20.1436 +	if (hw->phy.type == e1000_phy_m88)
 20.1437 +		igb_phy_disable_receiver(adapter);
 20.1438 +
 20.1439 +	udelay(500);
 20.1440 +
 20.1441 +	return 0;
 20.1442 +}
 20.1443 +
 20.1444 +static int igb_set_phy_loopback(struct igb_adapter *adapter)
 20.1445 +{
 20.1446 +	return igb_integrated_phy_loopback(adapter);
 20.1447 +}
 20.1448 +
 20.1449 +static int igb_setup_loopback_test(struct igb_adapter *adapter)
 20.1450 +{
 20.1451 +	struct e1000_hw *hw = &adapter->hw;
 20.1452 +	u32 reg;
 20.1453 +
 20.1454 +	if (hw->phy.media_type == e1000_media_type_fiber ||
 20.1455 +	    hw->phy.media_type == e1000_media_type_internal_serdes) {
 20.1456 +		reg = rd32(E1000_RCTL);
 20.1457 +		reg |= E1000_RCTL_LBM_TCVR;
 20.1458 +		wr32(E1000_RCTL, reg);
 20.1459 +
 20.1460 +		wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
 20.1461 +
 20.1462 +		reg = rd32(E1000_CTRL);
 20.1463 +		reg &= ~(E1000_CTRL_RFCE |
 20.1464 +			 E1000_CTRL_TFCE |
 20.1465 +			 E1000_CTRL_LRST);
 20.1466 +		reg |= E1000_CTRL_SLU |
 20.1467 +		       E1000_CTRL_FD; 
 20.1468 +		wr32(E1000_CTRL, reg);
 20.1469 +
 20.1470 +		/* Unset switch control to serdes energy detect */
 20.1471 +		reg = rd32(E1000_CONNSW);
 20.1472 +		reg &= ~E1000_CONNSW_ENRGSRC;
 20.1473 +		wr32(E1000_CONNSW, reg);
 20.1474 +
 20.1475 +		/* Set PCS register for forced speed */
 20.1476 +		reg = rd32(E1000_PCS_LCTL);
 20.1477 +		reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
 20.1478 +		reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
 20.1479 +		       E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
 20.1480 +		       E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
 20.1481 +		       E1000_PCS_LCTL_FSD |           /* Force Speed */
 20.1482 +		       E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
 20.1483 +		wr32(E1000_PCS_LCTL, reg);
 20.1484 +
 20.1485 +		return 0;
 20.1486 +	} else if (hw->phy.media_type == e1000_media_type_copper) {
 20.1487 +		return igb_set_phy_loopback(adapter);
 20.1488 +	}
 20.1489 +
 20.1490 +	return 7;
 20.1491 +}
 20.1492 +
 20.1493 +static void igb_loopback_cleanup(struct igb_adapter *adapter)
 20.1494 +{
 20.1495 +	struct e1000_hw *hw = &adapter->hw;
 20.1496 +	u32 rctl;
 20.1497 +	u16 phy_reg;
 20.1498 +
 20.1499 +	rctl = rd32(E1000_RCTL);
 20.1500 +	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
 20.1501 +	wr32(E1000_RCTL, rctl);
 20.1502 +
 20.1503 +	hw->mac.autoneg = true;
 20.1504 +	hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_reg);
 20.1505 +	if (phy_reg & MII_CR_LOOPBACK) {
 20.1506 +		phy_reg &= ~MII_CR_LOOPBACK;
 20.1507 +		hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_reg);
 20.1508 +		igb_phy_sw_reset(hw);
 20.1509 +	}
 20.1510 +}
 20.1511 +
 20.1512 +static void igb_create_lbtest_frame(struct sk_buff *skb,
 20.1513 +				    unsigned int frame_size)
 20.1514 +{
 20.1515 +	memset(skb->data, 0xFF, frame_size);
 20.1516 +	frame_size &= ~1;
 20.1517 +	memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
 20.1518 +	memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
 20.1519 +	memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
 20.1520 +}
 20.1521 +
 20.1522 +static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
 20.1523 +{
 20.1524 +	frame_size &= ~1;
 20.1525 +	if (*(skb->data + 3) == 0xFF)
 20.1526 +		if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
 20.1527 +		   (*(skb->data + frame_size / 2 + 12) == 0xAF))
 20.1528 +			return 0;
 20.1529 +	return 13;
 20.1530 +}
 20.1531 +
 20.1532 +static int igb_run_loopback_test(struct igb_adapter *adapter)
 20.1533 +{
 20.1534 +	struct e1000_hw *hw = &adapter->hw;
 20.1535 +	struct igb_ring *tx_ring = &adapter->test_tx_ring;
 20.1536 +	struct igb_ring *rx_ring = &adapter->test_rx_ring;
 20.1537 +	struct pci_dev *pdev = adapter->pdev;
 20.1538 +	int i, j, k, l, lc, good_cnt;
 20.1539 +	int ret_val = 0;
 20.1540 +	unsigned long time;
 20.1541 +
 20.1542 +	wr32(E1000_RDT(0), rx_ring->count - 1);
 20.1543 +
 20.1544 +	/* Calculate the loop count based on the largest descriptor ring
 20.1545 +	 * The idea is to wrap the largest ring a number of times using 64
 20.1546 +	 * send/receive pairs during each loop
 20.1547 +	 */
 20.1548 +
 20.1549 +	if (rx_ring->count <= tx_ring->count)
 20.1550 +		lc = ((tx_ring->count / 64) * 2) + 1;
 20.1551 +	else
 20.1552 +		lc = ((rx_ring->count / 64) * 2) + 1;
 20.1553 +
 20.1554 +	k = l = 0;
 20.1555 +	for (j = 0; j <= lc; j++) { /* loop count loop */
 20.1556 +		for (i = 0; i < 64; i++) { /* send the packets */
 20.1557 +			igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
 20.1558 +						1024);
 20.1559 +			pci_dma_sync_single_for_device(pdev,
 20.1560 +				tx_ring->buffer_info[k].dma,
 20.1561 +				tx_ring->buffer_info[k].length,
 20.1562 +				PCI_DMA_TODEVICE);
 20.1563 +			k++;
 20.1564 +			if (k == tx_ring->count)
 20.1565 +				k = 0;
 20.1566 +		}
 20.1567 +		wr32(E1000_TDT(0), k);
 20.1568 +		msleep(200);
 20.1569 +		time = jiffies; /* set the start time for the receive */
 20.1570 +		good_cnt = 0;
 20.1571 +		do { /* receive the sent packets */
 20.1572 +			pci_dma_sync_single_for_cpu(pdev,
 20.1573 +					rx_ring->buffer_info[l].dma,
 20.1574 +					IGB_RXBUFFER_2048,
 20.1575 +					PCI_DMA_FROMDEVICE);
 20.1576 +
 20.1577 +			ret_val = igb_check_lbtest_frame(
 20.1578 +					     rx_ring->buffer_info[l].skb, 1024);
 20.1579 +			if (!ret_val)
 20.1580 +				good_cnt++;
 20.1581 +			l++;
 20.1582 +			if (l == rx_ring->count)
 20.1583 +				l = 0;
 20.1584 +			/* time + 20 msecs (200 msecs on 2.4) is more than
 20.1585 +			 * enough time to complete the receives, if it's
 20.1586 +			 * exceeded, break and error off
 20.1587 +			 */
 20.1588 +		} while (good_cnt < 64 && jiffies < (time + 20));
 20.1589 +		if (good_cnt != 64) {
 20.1590 +			ret_val = 13; /* ret_val is the same as mis-compare */
 20.1591 +			break;
 20.1592 +		}
 20.1593 +		if (jiffies >= (time + 20)) {
 20.1594 +			ret_val = 14; /* error code for time out error */
 20.1595 +			break;
 20.1596 +		}
 20.1597 +	} /* end loop count loop */
 20.1598 +	return ret_val;
 20.1599 +}
 20.1600 +
 20.1601 +static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
 20.1602 +{
 20.1603 +	/* PHY loopback cannot be performed if SoL/IDER
 20.1604 +	 * sessions are active */
 20.1605 +	if (igb_check_reset_block(&adapter->hw)) {
 20.1606 +		dev_err(&adapter->pdev->dev,
 20.1607 +			"Cannot do PHY loopback test "
 20.1608 +			"when SoL/IDER is active.\n");
 20.1609 +		*data = 0;
 20.1610 +		goto out;
 20.1611 +	}
 20.1612 +	*data = igb_setup_desc_rings(adapter);
 20.1613 +	if (*data)
 20.1614 +		goto out;
 20.1615 +	*data = igb_setup_loopback_test(adapter);
 20.1616 +	if (*data)
 20.1617 +		goto err_loopback;
 20.1618 +	*data = igb_run_loopback_test(adapter);
 20.1619 +	igb_loopback_cleanup(adapter);
 20.1620 +
 20.1621 +err_loopback:
 20.1622 +	igb_free_desc_rings(adapter);
 20.1623 +out:
 20.1624 +	return *data;
 20.1625 +}
 20.1626 +
 20.1627 +static int igb_link_test(struct igb_adapter *adapter, u64 *data)
 20.1628 +{
 20.1629 +	struct e1000_hw *hw = &adapter->hw;
 20.1630 +	*data = 0;
 20.1631 +	if (hw->phy.media_type == e1000_media_type_internal_serdes) {
 20.1632 +		int i = 0;
 20.1633 +		hw->mac.serdes_has_link = false;
 20.1634 +
 20.1635 +		/* On some blade server designs, link establishment
 20.1636 +		 * could take as long as 2-3 minutes */
 20.1637 +		do {
 20.1638 +			hw->mac.ops.check_for_link(&adapter->hw);
 20.1639 +			if (hw->mac.serdes_has_link)
 20.1640 +				return *data;
 20.1641 +			msleep(20);
 20.1642 +		} while (i++ < 3750);
 20.1643 +
 20.1644 +		*data = 1;
 20.1645 +	} else {
 20.1646 +		hw->mac.ops.check_for_link(&adapter->hw);
 20.1647 +		if (hw->mac.autoneg)
 20.1648 +			msleep(4000);
 20.1649 +
 20.1650 +		if (!(rd32(E1000_STATUS) &
 20.1651 +		      E1000_STATUS_LU))
 20.1652 +			*data = 1;
 20.1653 +	}
 20.1654 +	return *data;
 20.1655 +}
 20.1656 +
 20.1657 +static void igb_diag_test(struct net_device *netdev,
 20.1658 +			  struct ethtool_test *eth_test, u64 *data)
 20.1659 +{
 20.1660 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1661 +	u16 autoneg_advertised;
 20.1662 +	u8 forced_speed_duplex, autoneg;
 20.1663 +	bool if_running = netif_running(netdev);
 20.1664 +
 20.1665 +	set_bit(__IGB_TESTING, &adapter->state);
 20.1666 +	if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
 20.1667 +		/* Offline tests */
 20.1668 +
 20.1669 +		/* save speed, duplex, autoneg settings */
 20.1670 +		autoneg_advertised = adapter->hw.phy.autoneg_advertised;
 20.1671 +		forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
 20.1672 +		autoneg = adapter->hw.mac.autoneg;
 20.1673 +
 20.1674 +		dev_info(&adapter->pdev->dev, "offline testing starting\n");
 20.1675 +
 20.1676 +		/* Link test performed before hardware reset so autoneg doesn't
 20.1677 +		 * interfere with test result */
 20.1678 +		if (igb_link_test(adapter, &data[4]))
 20.1679 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 20.1680 +
 20.1681 +		if (if_running)
 20.1682 +			/* indicate we're in test mode */
 20.1683 +			dev_close(netdev);
 20.1684 +		else
 20.1685 +			igb_reset(adapter);
 20.1686 +
 20.1687 +		if (igb_reg_test(adapter, &data[0]))
 20.1688 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 20.1689 +
 20.1690 +		igb_reset(adapter);
 20.1691 +		if (igb_eeprom_test(adapter, &data[1]))
 20.1692 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 20.1693 +
 20.1694 +		igb_reset(adapter);
 20.1695 +		if (igb_intr_test(adapter, &data[2]))
 20.1696 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 20.1697 +
 20.1698 +		igb_reset(adapter);
 20.1699 +		if (igb_loopback_test(adapter, &data[3]))
 20.1700 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 20.1701 +
 20.1702 +		/* restore speed, duplex, autoneg settings */
 20.1703 +		adapter->hw.phy.autoneg_advertised = autoneg_advertised;
 20.1704 +		adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
 20.1705 +		adapter->hw.mac.autoneg = autoneg;
 20.1706 +
 20.1707 +		/* force this routine to wait until autoneg complete/timeout */
 20.1708 +		adapter->hw.phy.autoneg_wait_to_complete = true;
 20.1709 +		igb_reset(adapter);
 20.1710 +		adapter->hw.phy.autoneg_wait_to_complete = false;
 20.1711 +
 20.1712 +		clear_bit(__IGB_TESTING, &adapter->state);
 20.1713 +		if (if_running)
 20.1714 +			dev_open(netdev);
 20.1715 +	} else {
 20.1716 +		dev_info(&adapter->pdev->dev, "online testing starting\n");
 20.1717 +		/* Online tests */
 20.1718 +		if (igb_link_test(adapter, &data[4]))
 20.1719 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 20.1720 +
 20.1721 +		/* Online tests aren't run; pass by default */
 20.1722 +		data[0] = 0;
 20.1723 +		data[1] = 0;
 20.1724 +		data[2] = 0;
 20.1725 +		data[3] = 0;
 20.1726 +
 20.1727 +		clear_bit(__IGB_TESTING, &adapter->state);
 20.1728 +	}
 20.1729 +	msleep_interruptible(4 * 1000);
 20.1730 +}
 20.1731 +
 20.1732 +static int igb_wol_exclusion(struct igb_adapter *adapter,
 20.1733 +			     struct ethtool_wolinfo *wol)
 20.1734 +{
 20.1735 +	struct e1000_hw *hw = &adapter->hw;
 20.1736 +	int retval = 1; /* fail by default */
 20.1737 +
 20.1738 +	switch (hw->device_id) {
 20.1739 +	case E1000_DEV_ID_82575GB_QUAD_COPPER:
 20.1740 +		/* WoL not supported */
 20.1741 +		wol->supported = 0;
 20.1742 +		break;
 20.1743 +	case E1000_DEV_ID_82575EB_FIBER_SERDES:
 20.1744 +	case E1000_DEV_ID_82576_FIBER:
 20.1745 +	case E1000_DEV_ID_82576_SERDES:
 20.1746 +		/* Wake events not supported on port B */
 20.1747 +		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
 20.1748 +			wol->supported = 0;
 20.1749 +			break;
 20.1750 +		}
 20.1751 +		/* return success for non excluded adapter ports */
 20.1752 +		retval = 0;
 20.1753 +		break;
 20.1754 +	case E1000_DEV_ID_82576_QUAD_COPPER:
 20.1755 +		/* quad port adapters only support WoL on port A */
 20.1756 +		if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
 20.1757 +			wol->supported = 0;
 20.1758 +			break;
 20.1759 +		}
 20.1760 +		/* return success for non excluded adapter ports */
 20.1761 +		retval = 0;
 20.1762 +		break;
 20.1763 +	default:
 20.1764 +		/* dual port cards only support WoL on port A from now on
 20.1765 +		 * unless it was enabled in the eeprom for port B
 20.1766 +		 * so exclude FUNC_1 ports from having WoL enabled */
 20.1767 +		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
 20.1768 +		    !adapter->eeprom_wol) {
 20.1769 +			wol->supported = 0;
 20.1770 +			break;
 20.1771 +		}
 20.1772 +
 20.1773 +		retval = 0;
 20.1774 +	}
 20.1775 +
 20.1776 +	return retval;
 20.1777 +}
 20.1778 +
 20.1779 +static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
 20.1780 +{
 20.1781 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1782 +
 20.1783 +	wol->supported = WAKE_UCAST | WAKE_MCAST |
 20.1784 +			 WAKE_BCAST | WAKE_MAGIC;
 20.1785 +	wol->wolopts = 0;
 20.1786 +
 20.1787 +	/* this function will set ->supported = 0 and return 1 if wol is not
 20.1788 +	 * supported by this hardware */
 20.1789 +	if (igb_wol_exclusion(adapter, wol))
 20.1790 +		return;
 20.1791 +
 20.1792 +	/* apply any specific unsupported masks here */
 20.1793 +	switch (adapter->hw.device_id) {
 20.1794 +	default:
 20.1795 +		break;
 20.1796 +	}
 20.1797 +
 20.1798 +	if (adapter->wol & E1000_WUFC_EX)
 20.1799 +		wol->wolopts |= WAKE_UCAST;
 20.1800 +	if (adapter->wol & E1000_WUFC_MC)
 20.1801 +		wol->wolopts |= WAKE_MCAST;
 20.1802 +	if (adapter->wol & E1000_WUFC_BC)
 20.1803 +		wol->wolopts |= WAKE_BCAST;
 20.1804 +	if (adapter->wol & E1000_WUFC_MAG)
 20.1805 +		wol->wolopts |= WAKE_MAGIC;
 20.1806 +
 20.1807 +	return;
 20.1808 +}
 20.1809 +
 20.1810 +static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
 20.1811 +{
 20.1812 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1813 +	struct e1000_hw *hw = &adapter->hw;
 20.1814 +
 20.1815 +	if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
 20.1816 +		return -EOPNOTSUPP;
 20.1817 +
 20.1818 +	if (igb_wol_exclusion(adapter, wol))
 20.1819 +		return wol->wolopts ? -EOPNOTSUPP : 0;
 20.1820 +
 20.1821 +	switch (hw->device_id) {
 20.1822 +	default:
 20.1823 +		break;
 20.1824 +	}
 20.1825 +
 20.1826 +	/* these settings will always override what we currently have */
 20.1827 +	adapter->wol = 0;
 20.1828 +
 20.1829 +	if (wol->wolopts & WAKE_UCAST)
 20.1830 +		adapter->wol |= E1000_WUFC_EX;
 20.1831 +	if (wol->wolopts & WAKE_MCAST)
 20.1832 +		adapter->wol |= E1000_WUFC_MC;
 20.1833 +	if (wol->wolopts & WAKE_BCAST)
 20.1834 +		adapter->wol |= E1000_WUFC_BC;
 20.1835 +	if (wol->wolopts & WAKE_MAGIC)
 20.1836 +		adapter->wol |= E1000_WUFC_MAG;
 20.1837 +
 20.1838 +	return 0;
 20.1839 +}
 20.1840 +
 20.1841 +/* toggle LED 4 times per second = 2 "blinks" per second */
 20.1842 +#define IGB_ID_INTERVAL		(HZ/4)
 20.1843 +
 20.1844 +/* bit defines for adapter->led_status */
 20.1845 +#define IGB_LED_ON		0
 20.1846 +
 20.1847 +static int igb_phys_id(struct net_device *netdev, u32 data)
 20.1848 +{
 20.1849 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1850 +	struct e1000_hw *hw = &adapter->hw;
 20.1851 +
 20.1852 +	if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
 20.1853 +		data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
 20.1854 +
 20.1855 +	igb_blink_led(hw);
 20.1856 +	msleep_interruptible(data * 1000);
 20.1857 +
 20.1858 +	igb_led_off(hw);
 20.1859 +	clear_bit(IGB_LED_ON, &adapter->led_status);
 20.1860 +	igb_cleanup_led(hw);
 20.1861 +
 20.1862 +	return 0;
 20.1863 +}
 20.1864 +
 20.1865 +static int igb_set_coalesce(struct net_device *netdev,
 20.1866 +			    struct ethtool_coalesce *ec)
 20.1867 +{
 20.1868 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1869 +	struct e1000_hw *hw = &adapter->hw;
 20.1870 +	int i;
 20.1871 +
 20.1872 +	if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
 20.1873 +	    ((ec->rx_coalesce_usecs > 3) &&
 20.1874 +	     (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
 20.1875 +	    (ec->rx_coalesce_usecs == 2))
 20.1876 +		return -EINVAL;
 20.1877 +
 20.1878 +	/* convert to rate of irq's per second */
 20.1879 +	if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
 20.1880 +		adapter->itr_setting = ec->rx_coalesce_usecs;
 20.1881 +		adapter->itr = IGB_START_ITR;
 20.1882 +	} else {
 20.1883 +		adapter->itr_setting = ec->rx_coalesce_usecs << 2;
 20.1884 +		adapter->itr = adapter->itr_setting;
 20.1885 +	}
 20.1886 +
 20.1887 +	for (i = 0; i < adapter->num_rx_queues; i++)
 20.1888 +		wr32(adapter->rx_ring[i].itr_register, adapter->itr);
 20.1889 +
 20.1890 +	return 0;
 20.1891 +}
 20.1892 +
 20.1893 +static int igb_get_coalesce(struct net_device *netdev,
 20.1894 +			    struct ethtool_coalesce *ec)
 20.1895 +{
 20.1896 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1897 +
 20.1898 +	if (adapter->itr_setting <= 3)
 20.1899 +		ec->rx_coalesce_usecs = adapter->itr_setting;
 20.1900 +	else
 20.1901 +		ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
 20.1902 +
 20.1903 +	return 0;
 20.1904 +}
 20.1905 +
 20.1906 +
 20.1907 +static int igb_nway_reset(struct net_device *netdev)
 20.1908 +{
 20.1909 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1910 +	if (netif_running(netdev))
 20.1911 +		igb_reinit_locked(adapter);
 20.1912 +	return 0;
 20.1913 +}
 20.1914 +
 20.1915 +static int igb_get_stats_count(struct net_device *netdev)
 20.1916 +{
 20.1917 +	return IGB_STATS_LEN;
 20.1918 +}
 20.1919 +
 20.1920 +static void igb_get_ethtool_stats(struct net_device *netdev,
 20.1921 +				  struct ethtool_stats *stats, u64 *data)
 20.1922 +{
 20.1923 +	struct igb_adapter *adapter = netdev_priv(netdev);
 20.1924 +	u64 *queue_stat;
 20.1925 +	int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
 20.1926 +	int j;
 20.1927 +	int i;
 20.1928 +#ifdef CONFIG_IGB_LRO
 20.1929 +	int aggregated = 0, flushed = 0, no_desc = 0;
 20.1930 +
 20.1931 +	for (i = 0; i < adapter->num_rx_queues; i++) {
 20.1932 +		aggregated += adapter->rx_ring[i].lro_mgr.stats.aggregated;
 20.1933 +		flushed += adapter->rx_ring[i].lro_mgr.stats.flushed;
 20.1934 +		no_desc += adapter->rx_ring[i].lro_mgr.stats.no_desc;
 20.1935 +	}
 20.1936 +	adapter->lro_aggregated = aggregated;