ia64/linux-2.6.18-xen.hg

changeset 699:9c0f24bdbe3a

Merge with IA64 tree
author Keir Fraser <keir.fraser@citrix.com>
date Fri Oct 10 10:17:40 2008 +0100 (2008-10-10)
parents 9010d63470ff a4b25d49459d
children 70fb735a8e28
files
line diff
     1.1 --- a/drivers/scsi/ahci.c	Fri Oct 10 12:07:01 2008 +0900
     1.2 +++ b/drivers/scsi/ahci.c	Fri Oct 10 10:17:40 2008 +0100
     1.3 @@ -93,7 +93,9 @@ enum {
     1.4  	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
     1.5  
     1.6  	/* HOST_CAP bits */
     1.7 +	HOST_CAP_SSC		= (1 << 14), /* Slumber capable */
     1.8  	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
     1.9 +	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
    1.10  	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
    1.11  	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
    1.12  
    1.13 @@ -156,6 +158,7 @@ enum {
    1.14  	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
    1.15  	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
    1.16  
    1.17 +	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
    1.18  	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
    1.19  	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
    1.20  	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
    1.21 @@ -213,6 +216,10 @@ static void ahci_freeze(struct ata_port 
    1.22  static void ahci_thaw(struct ata_port *ap);
    1.23  static void ahci_error_handler(struct ata_port *ap);
    1.24  static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
    1.25 +static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
    1.26 +static int ahci_port_resume(struct ata_port *ap);
    1.27 +static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
    1.28 +static int ahci_pci_device_resume(struct pci_dev *pdev);
    1.29  static void ahci_remove_one (struct pci_dev *pdev);
    1.30  
    1.31  static struct scsi_host_template ahci_sht = {
    1.32 @@ -232,6 +239,8 @@ static struct scsi_host_template ahci_sh
    1.33  	.slave_configure	= ata_scsi_slave_config,
    1.34  	.slave_destroy		= ata_scsi_slave_destroy,
    1.35  	.bios_param		= ata_std_bios_param,
    1.36 +	.suspend		= ata_scsi_device_suspend,
    1.37 +	.resume			= ata_scsi_device_resume,
    1.38  };
    1.39  
    1.40  static const struct ata_port_operations ahci_ops = {
    1.41 @@ -258,6 +267,9 @@ static const struct ata_port_operations 
    1.42  	.error_handler		= ahci_error_handler,
    1.43  	.post_internal_cmd	= ahci_post_internal_cmd,
    1.44  
    1.45 +	.port_suspend		= ahci_port_suspend,
    1.46 +	.port_resume		= ahci_port_resume,
    1.47 +
    1.48  	.port_start		= ahci_port_start,
    1.49  	.port_stop		= ahci_port_stop,
    1.50  };
    1.51 @@ -411,6 +423,8 @@ static struct pci_driver ahci_pci_driver
    1.52  	.name			= DRV_NAME,
    1.53  	.id_table		= ahci_pci_tbl,
    1.54  	.probe			= ahci_init_one,
    1.55 +	.suspend		= ahci_pci_device_suspend,
    1.56 +	.resume			= ahci_pci_device_resume,
    1.57  	.remove			= ahci_remove_one,
    1.58  };
    1.59  
    1.60 @@ -425,108 +439,6 @@ static inline void __iomem *ahci_port_ba
    1.61  	return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
    1.62  }
    1.63  
    1.64 -static int ahci_port_start(struct ata_port *ap)
    1.65 -{
    1.66 -	struct device *dev = ap->host_set->dev;
    1.67 -	struct ahci_host_priv *hpriv = ap->host_set->private_data;
    1.68 -	struct ahci_port_priv *pp;
    1.69 -	void __iomem *mmio = ap->host_set->mmio_base;
    1.70 -	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
    1.71 -	void *mem;
    1.72 -	dma_addr_t mem_dma;
    1.73 -	int rc;
    1.74 -
    1.75 -	pp = kmalloc(sizeof(*pp), GFP_KERNEL);
    1.76 -	if (!pp)
    1.77 -		return -ENOMEM;
    1.78 -	memset(pp, 0, sizeof(*pp));
    1.79 -
    1.80 -	rc = ata_pad_alloc(ap, dev);
    1.81 -	if (rc) {
    1.82 -		kfree(pp);
    1.83 -		return rc;
    1.84 -	}
    1.85 -
    1.86 -	mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
    1.87 -	if (!mem) {
    1.88 -		ata_pad_free(ap, dev);
    1.89 -		kfree(pp);
    1.90 -		return -ENOMEM;
    1.91 -	}
    1.92 -	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
    1.93 -
    1.94 -	/*
    1.95 -	 * First item in chunk of DMA memory: 32-slot command table,
    1.96 -	 * 32 bytes each in size
    1.97 -	 */
    1.98 -	pp->cmd_slot = mem;
    1.99 -	pp->cmd_slot_dma = mem_dma;
   1.100 -
   1.101 -	mem += AHCI_CMD_SLOT_SZ;
   1.102 -	mem_dma += AHCI_CMD_SLOT_SZ;
   1.103 -
   1.104 -	/*
   1.105 -	 * Second item: Received-FIS area
   1.106 -	 */
   1.107 -	pp->rx_fis = mem;
   1.108 -	pp->rx_fis_dma = mem_dma;
   1.109 -
   1.110 -	mem += AHCI_RX_FIS_SZ;
   1.111 -	mem_dma += AHCI_RX_FIS_SZ;
   1.112 -
   1.113 -	/*
   1.114 -	 * Third item: data area for storing a single command
   1.115 -	 * and its scatter-gather table
   1.116 -	 */
   1.117 -	pp->cmd_tbl = mem;
   1.118 -	pp->cmd_tbl_dma = mem_dma;
   1.119 -
   1.120 -	ap->private_data = pp;
   1.121 -
   1.122 -	if (hpriv->cap & HOST_CAP_64)
   1.123 -		writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
   1.124 -	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
   1.125 -	readl(port_mmio + PORT_LST_ADDR); /* flush */
   1.126 -
   1.127 -	if (hpriv->cap & HOST_CAP_64)
   1.128 -		writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
   1.129 -	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
   1.130 -	readl(port_mmio + PORT_FIS_ADDR); /* flush */
   1.131 -
   1.132 -	writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
   1.133 -	       PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
   1.134 -	       PORT_CMD_START, port_mmio + PORT_CMD);
   1.135 -	readl(port_mmio + PORT_CMD); /* flush */
   1.136 -
   1.137 -	return 0;
   1.138 -}
   1.139 -
   1.140 -
   1.141 -static void ahci_port_stop(struct ata_port *ap)
   1.142 -{
   1.143 -	struct device *dev = ap->host_set->dev;
   1.144 -	struct ahci_port_priv *pp = ap->private_data;
   1.145 -	void __iomem *mmio = ap->host_set->mmio_base;
   1.146 -	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.147 -	u32 tmp;
   1.148 -
   1.149 -	tmp = readl(port_mmio + PORT_CMD);
   1.150 -	tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
   1.151 -	writel(tmp, port_mmio + PORT_CMD);
   1.152 -	readl(port_mmio + PORT_CMD); /* flush */
   1.153 -
   1.154 -	/* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
   1.155 -	 * this is slightly incorrect.
   1.156 -	 */
   1.157 -	msleep(500);
   1.158 -
   1.159 -	ap->private_data = NULL;
   1.160 -	dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
   1.161 -			  pp->cmd_slot, pp->cmd_slot_dma);
   1.162 -	ata_pad_free(ap, dev);
   1.163 -	kfree(pp);
   1.164 -}
   1.165 -
   1.166  static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
   1.167  {
   1.168  	unsigned int sc_reg;
   1.169 @@ -561,43 +473,257 @@ static void ahci_scr_write (struct ata_p
   1.170  	writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
   1.171  }
   1.172  
   1.173 -static int ahci_stop_engine(struct ata_port *ap)
   1.174 +static void ahci_start_engine(void __iomem *port_mmio)
   1.175  {
   1.176 -	void __iomem *mmio = ap->host_set->mmio_base;
   1.177 -	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.178 -	int work;
   1.179  	u32 tmp;
   1.180  
   1.181 -	tmp = readl(port_mmio + PORT_CMD);
   1.182 -	tmp &= ~PORT_CMD_START;
   1.183 -	writel(tmp, port_mmio + PORT_CMD);
   1.184 -
   1.185 -	/* wait for engine to stop.  TODO: this could be
   1.186 -	 * as long as 500 msec
   1.187 -	 */
   1.188 -	work = 1000;
   1.189 -	while (work-- > 0) {
   1.190 -		tmp = readl(port_mmio + PORT_CMD);
   1.191 -		if ((tmp & PORT_CMD_LIST_ON) == 0)
   1.192 -			return 0;
   1.193 -		udelay(10);
   1.194 -	}
   1.195 -
   1.196 -	return -EIO;
   1.197 -}
   1.198 -
   1.199 -static void ahci_start_engine(struct ata_port *ap)
   1.200 -{
   1.201 -	void __iomem *mmio = ap->host_set->mmio_base;
   1.202 -	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.203 -	u32 tmp;
   1.204 -
   1.205 +	/* start DMA */
   1.206  	tmp = readl(port_mmio + PORT_CMD);
   1.207  	tmp |= PORT_CMD_START;
   1.208  	writel(tmp, port_mmio + PORT_CMD);
   1.209  	readl(port_mmio + PORT_CMD); /* flush */
   1.210  }
   1.211  
   1.212 +static int ahci_stop_engine(void __iomem *port_mmio)
   1.213 +{
   1.214 +	u32 tmp;
   1.215 +
   1.216 +	tmp = readl(port_mmio + PORT_CMD);
   1.217 +
   1.218 +	/* check if the HBA is idle */
   1.219 +	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
   1.220 +		return 0;
   1.221 +
   1.222 +	/* setting HBA to idle */
   1.223 +	tmp &= ~PORT_CMD_START;
   1.224 +	writel(tmp, port_mmio + PORT_CMD);
   1.225 +
   1.226 +	/* wait for engine to stop. This could be as long as 500 msec */
   1.227 +	tmp = ata_wait_register(port_mmio + PORT_CMD,
   1.228 +			        PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
   1.229 +	if (tmp & PORT_CMD_LIST_ON)
   1.230 +		return -EIO;
   1.231 +
   1.232 +	return 0;
   1.233 +}
   1.234 +
   1.235 +static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
   1.236 +			      dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
   1.237 +{
   1.238 +	u32 tmp;
   1.239 +
   1.240 +	/* set FIS registers */
   1.241 +	if (cap & HOST_CAP_64)
   1.242 +		writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
   1.243 +	writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
   1.244 +
   1.245 +	if (cap & HOST_CAP_64)
   1.246 +		writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
   1.247 +	writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
   1.248 +
   1.249 +	/* enable FIS reception */
   1.250 +	tmp = readl(port_mmio + PORT_CMD);
   1.251 +	tmp |= PORT_CMD_FIS_RX;
   1.252 +	writel(tmp, port_mmio + PORT_CMD);
   1.253 +
   1.254 +	/* flush */
   1.255 +	readl(port_mmio + PORT_CMD);
   1.256 +}
   1.257 +
   1.258 +static int ahci_stop_fis_rx(void __iomem *port_mmio)
   1.259 +{
   1.260 +	u32 tmp;
   1.261 +
   1.262 +	/* disable FIS reception */
   1.263 +	tmp = readl(port_mmio + PORT_CMD);
   1.264 +	tmp &= ~PORT_CMD_FIS_RX;
   1.265 +	writel(tmp, port_mmio + PORT_CMD);
   1.266 +
   1.267 +	/* wait for completion, spec says 500ms, give it 1000 */
   1.268 +	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
   1.269 +				PORT_CMD_FIS_ON, 10, 1000);
   1.270 +	if (tmp & PORT_CMD_FIS_ON)
   1.271 +		return -EBUSY;
   1.272 +
   1.273 +	return 0;
   1.274 +}
   1.275 +
   1.276 +static void ahci_power_up(void __iomem *port_mmio, u32 cap)
   1.277 +{
   1.278 +	u32 cmd;
   1.279 +
   1.280 +	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
   1.281 +
   1.282 +	/* spin up device */
   1.283 +	if (cap & HOST_CAP_SSS) {
   1.284 +		cmd |= PORT_CMD_SPIN_UP;
   1.285 +		writel(cmd, port_mmio + PORT_CMD);
   1.286 +	}
   1.287 +
   1.288 +	/* wake up link */
   1.289 +	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
   1.290 +}
   1.291 +
   1.292 +static void ahci_power_down(void __iomem *port_mmio, u32 cap)
   1.293 +{
   1.294 +	u32 cmd, scontrol;
   1.295 +
   1.296 +	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
   1.297 +
   1.298 +	if (cap & HOST_CAP_SSC) {
   1.299 +		/* enable transitions to slumber mode */
   1.300 +		scontrol = readl(port_mmio + PORT_SCR_CTL);
   1.301 +		if ((scontrol & 0x0f00) > 0x100) {
   1.302 +			scontrol &= ~0xf00;
   1.303 +			writel(scontrol, port_mmio + PORT_SCR_CTL);
   1.304 +		}
   1.305 +
   1.306 +		/* put device into slumber mode */
   1.307 +		writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
   1.308 +
   1.309 +		/* wait for the transition to complete */
   1.310 +		ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
   1.311 +				  PORT_CMD_ICC_SLUMBER, 1, 50);
   1.312 +	}
   1.313 +
   1.314 +	/* put device into listen mode */
   1.315 +	if (cap & HOST_CAP_SSS) {
   1.316 +		/* first set PxSCTL.DET to 0 */
   1.317 +		scontrol = readl(port_mmio + PORT_SCR_CTL);
   1.318 +		scontrol &= ~0xf;
   1.319 +		writel(scontrol, port_mmio + PORT_SCR_CTL);
   1.320 +
   1.321 +		/* then set PxCMD.SUD to 0 */
   1.322 +		cmd &= ~PORT_CMD_SPIN_UP;
   1.323 +		writel(cmd, port_mmio + PORT_CMD);
   1.324 +	}
   1.325 +}
   1.326 +
   1.327 +static void ahci_init_port(void __iomem *port_mmio, u32 cap,
   1.328 +			   dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
   1.329 +{
   1.330 +	/* power up */
   1.331 +	ahci_power_up(port_mmio, cap);
   1.332 +
   1.333 +	/* enable FIS reception */
   1.334 +	ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
   1.335 +
   1.336 +	/* enable DMA */
   1.337 +	ahci_start_engine(port_mmio);
   1.338 +}
   1.339 +
   1.340 +static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
   1.341 +{
   1.342 +	int rc;
   1.343 +
   1.344 +	/* disable DMA */
   1.345 +	rc = ahci_stop_engine(port_mmio);
   1.346 +	if (rc) {
   1.347 +		*emsg = "failed to stop engine";
   1.348 +		return rc;
   1.349 +	}
   1.350 +
   1.351 +	/* disable FIS reception */
   1.352 +	rc = ahci_stop_fis_rx(port_mmio);
   1.353 +	if (rc) {
   1.354 +		*emsg = "failed stop FIS RX";
   1.355 +		return rc;
   1.356 +	}
   1.357 +
   1.358 +	/* put device into slumber mode */
   1.359 +	ahci_power_down(port_mmio, cap);
   1.360 +
   1.361 +	return 0;
   1.362 +}
   1.363 +
   1.364 +static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
   1.365 +{
   1.366 +	u32 cap_save, tmp;
   1.367 +
   1.368 +	cap_save = readl(mmio + HOST_CAP);
   1.369 +	cap_save &= ( (1<<28) | (1<<17) );
   1.370 +	cap_save |= (1 << 27);
   1.371 +
   1.372 +	/* global controller reset */
   1.373 +	tmp = readl(mmio + HOST_CTL);
   1.374 +	if ((tmp & HOST_RESET) == 0) {
   1.375 +		writel(tmp | HOST_RESET, mmio + HOST_CTL);
   1.376 +		readl(mmio + HOST_CTL); /* flush */
   1.377 +	}
   1.378 +
   1.379 +	/* reset must complete within 1 second, or
   1.380 +	 * the hardware should be considered fried.
   1.381 +	 */
   1.382 +	ssleep(1);
   1.383 +
   1.384 +	tmp = readl(mmio + HOST_CTL);
   1.385 +	if (tmp & HOST_RESET) {
   1.386 +		dev_printk(KERN_ERR, &pdev->dev,
   1.387 +			   "controller reset failed (0x%x)\n", tmp);
   1.388 +		return -EIO;
   1.389 +	}
   1.390 +
   1.391 +	writel(HOST_AHCI_EN, mmio + HOST_CTL);
   1.392 +	(void) readl(mmio + HOST_CTL);	/* flush */
   1.393 +	writel(cap_save, mmio + HOST_CAP);
   1.394 +	writel(0xf, mmio + HOST_PORTS_IMPL);
   1.395 +	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
   1.396 +
   1.397 +	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
   1.398 +		u16 tmp16;
   1.399 +
   1.400 +		/* configure PCS */
   1.401 +		pci_read_config_word(pdev, 0x92, &tmp16);
   1.402 +		tmp16 |= 0xf;
   1.403 +		pci_write_config_word(pdev, 0x92, tmp16);
   1.404 +	}
   1.405 +
   1.406 +	return 0;
   1.407 +}
   1.408 +
   1.409 +static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
   1.410 +				 int n_ports, u32 cap)
   1.411 +{
   1.412 +	int i, rc;
   1.413 +	u32 tmp;
   1.414 +
   1.415 +	for (i = 0; i < n_ports; i++) {
   1.416 +		void __iomem *port_mmio = ahci_port_base(mmio, i);
   1.417 +		const char *emsg = NULL;
   1.418 +
   1.419 +#if 0 /* BIOSen initialize this incorrectly */
   1.420 +		if (!(hpriv->port_map & (1 << i)))
   1.421 +			continue;
   1.422 +#endif
   1.423 +
   1.424 +		/* make sure port is not active */
   1.425 +		rc = ahci_deinit_port(port_mmio, cap, &emsg);
   1.426 +		if (rc)
   1.427 +			dev_printk(KERN_WARNING, &pdev->dev,
   1.428 +				   "%s (%d)\n", emsg, rc);
   1.429 +
   1.430 +		/* clear SError */
   1.431 +		tmp = readl(port_mmio + PORT_SCR_ERR);
   1.432 +		VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
   1.433 +		writel(tmp, port_mmio + PORT_SCR_ERR);
   1.434 +
   1.435 +		/* clear & turn off port IRQ */
   1.436 +		tmp = readl(port_mmio + PORT_IRQ_STAT);
   1.437 +		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
   1.438 +		if (tmp)
   1.439 +			writel(tmp, port_mmio + PORT_IRQ_STAT);
   1.440 +
   1.441 +		writel(1 << i, mmio + HOST_IRQ_STAT);
   1.442 +		writel(0, port_mmio + PORT_IRQ_MASK);
   1.443 +	}
   1.444 +
   1.445 +	tmp = readl(mmio + HOST_CTL);
   1.446 +	VPRINTK("HOST_CTL 0x%x\n", tmp);
   1.447 +	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
   1.448 +	tmp = readl(mmio + HOST_CTL);
   1.449 +	VPRINTK("HOST_CTL 0x%x\n", tmp);
   1.450 +}
   1.451 +
   1.452  static unsigned int ahci_dev_classify(struct ata_port *ap)
   1.453  {
   1.454  	void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
   1.455 @@ -679,7 +805,7 @@ static int ahci_softreset(struct ata_por
   1.456  	}
   1.457  
   1.458  	/* prepare for SRST (AHCI-1.1 10.4.1) */
   1.459 -	rc = ahci_stop_engine(ap);
   1.460 +	rc = ahci_stop_engine(port_mmio);
   1.461  	if (rc) {
   1.462  		reason = "failed to stop engine";
   1.463  		goto fail_restart;
   1.464 @@ -700,7 +826,7 @@ static int ahci_softreset(struct ata_por
   1.465  	}
   1.466  
   1.467  	/* restart engine */
   1.468 -	ahci_start_engine(ap);
   1.469 +	ahci_start_engine(port_mmio);
   1.470  
   1.471  	ata_tf_init(ap->device, &tf);
   1.472  	fis = pp->cmd_tbl;
   1.473 @@ -759,7 +885,7 @@ static int ahci_softreset(struct ata_por
   1.474  	return 0;
   1.475  
   1.476   fail_restart:
   1.477 -	ahci_start_engine(ap);
   1.478 +	ahci_start_engine(port_mmio);
   1.479   fail:
   1.480  	ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
   1.481  	return rc;
   1.482 @@ -770,11 +896,13 @@ static int ahci_hardreset(struct ata_por
   1.483  	struct ahci_port_priv *pp = ap->private_data;
   1.484  	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
   1.485  	struct ata_taskfile tf;
   1.486 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.487 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.488  	int rc;
   1.489  
   1.490  	DPRINTK("ENTER\n");
   1.491  
   1.492 -	ahci_stop_engine(ap);
   1.493 +	ahci_stop_engine(port_mmio);
   1.494  
   1.495  	/* clear D2H reception area to properly wait for D2H FIS */
   1.496  	ata_tf_init(ap->device, &tf);
   1.497 @@ -783,7 +911,7 @@ static int ahci_hardreset(struct ata_por
   1.498  
   1.499  	rc = sata_std_hardreset(ap, class);
   1.500  
   1.501 -	ahci_start_engine(ap);
   1.502 +	ahci_start_engine(port_mmio);
   1.503  
   1.504  	if (rc == 0 && ata_port_online(ap))
   1.505  		*class = ahci_dev_classify(ap);
   1.506 @@ -993,8 +1121,14 @@ static void ahci_host_intr(struct ata_po
   1.507  		return;
   1.508  
   1.509  	/* ignore interim PIO setup fis interrupts */
   1.510 -	if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS)) 
   1.511 -		return;
   1.512 +	if (ata_tag_valid(ap->active_tag)) {
   1.513 +		struct ata_queued_cmd *qc =
   1.514 +			ata_qc_from_tag(ap, ap->active_tag);
   1.515 +
   1.516 +		if (qc && qc->tf.protocol == ATA_PROT_PIO &&
   1.517 +		    (status & PORT_IRQ_PIOS_FIS))
   1.518 +			return;
   1.519 +	}
   1.520  
   1.521  	if (ata_ratelimit())
   1.522  		ata_port_printk(ap, KERN_INFO, "spurious interrupt "
   1.523 @@ -1099,10 +1233,13 @@ static void ahci_thaw(struct ata_port *a
   1.524  
   1.525  static void ahci_error_handler(struct ata_port *ap)
   1.526  {
   1.527 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.528 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.529 +
   1.530  	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
   1.531  		/* restart engine */
   1.532 -		ahci_stop_engine(ap);
   1.533 -		ahci_start_engine(ap);
   1.534 +		ahci_stop_engine(port_mmio);
   1.535 +		ahci_start_engine(port_mmio);
   1.536  	}
   1.537  
   1.538  	/* perform recovery */
   1.539 @@ -1113,17 +1250,178 @@ static void ahci_error_handler(struct at
   1.540  static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
   1.541  {
   1.542  	struct ata_port *ap = qc->ap;
   1.543 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.544 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.545  
   1.546  	if (qc->flags & ATA_QCFLAG_FAILED)
   1.547  		qc->err_mask |= AC_ERR_OTHER;
   1.548  
   1.549  	if (qc->err_mask) {
   1.550  		/* make DMA engine forget about the failed command */
   1.551 -		ahci_stop_engine(ap);
   1.552 -		ahci_start_engine(ap);
   1.553 +		ahci_stop_engine(port_mmio);
   1.554 +		ahci_start_engine(port_mmio);
   1.555  	}
   1.556  }
   1.557  
   1.558 +static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
   1.559 +{
   1.560 +	struct ahci_host_priv *hpriv = ap->host_set->private_data;
   1.561 +	struct ahci_port_priv *pp = ap->private_data;
   1.562 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.563 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.564 +	const char *emsg = NULL;
   1.565 +	int rc;
   1.566 +
   1.567 +	rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
   1.568 +	if (rc) {
   1.569 +		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
   1.570 +		ahci_init_port(port_mmio, hpriv->cap,
   1.571 +			       pp->cmd_slot_dma, pp->rx_fis_dma);
   1.572 +	}
   1.573 +
   1.574 +	return rc;
   1.575 +}
   1.576 +
   1.577 +static int ahci_port_resume(struct ata_port *ap)
   1.578 +{
   1.579 +	struct ahci_port_priv *pp = ap->private_data;
   1.580 +	struct ahci_host_priv *hpriv = ap->host_set->private_data;
   1.581 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.582 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.583 +
   1.584 +	ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
   1.585 +
   1.586 +	return 0;
   1.587 +}
   1.588 +
   1.589 +static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
   1.590 +{
   1.591 +	struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
   1.592 +	void __iomem *mmio = host_set->mmio_base;
   1.593 +	u32 ctl;
   1.594 +
   1.595 +	if (mesg.event == PM_EVENT_SUSPEND) {
   1.596 +		/* AHCI spec rev1.1 section 8.3.3:
   1.597 +		 * Software must disable interrupts prior to requesting a
   1.598 +		 * transition of the HBA to D3 state.
   1.599 +		 */
   1.600 +		ctl = readl(mmio + HOST_CTL);
   1.601 +		ctl &= ~HOST_IRQ_EN;
   1.602 +		writel(ctl, mmio + HOST_CTL);
   1.603 +		readl(mmio + HOST_CTL); /* flush */
   1.604 +	}
   1.605 +
   1.606 +	return ata_pci_device_suspend(pdev, mesg);
   1.607 +}
   1.608 +
   1.609 +static int ahci_pci_device_resume(struct pci_dev *pdev)
   1.610 +{
   1.611 +	struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
   1.612 +	struct ahci_host_priv *hpriv = host_set->private_data;
   1.613 +	void __iomem *mmio = host_set->mmio_base;
   1.614 +	int rc;
   1.615 +
   1.616 +	ata_pci_device_do_resume(pdev);
   1.617 +
   1.618 +	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
   1.619 +		rc = ahci_reset_controller(mmio, pdev);
   1.620 +		if (rc)
   1.621 +			return rc;
   1.622 +
   1.623 +		ahci_init_controller(mmio, pdev, host_set->n_ports, hpriv->cap);
   1.624 +	}
   1.625 +
   1.626 +	ata_host_set_resume(host_set);
   1.627 +
   1.628 +	return 0;
   1.629 +}
   1.630 +
   1.631 +static int ahci_port_start(struct ata_port *ap)
   1.632 +{
   1.633 +	struct device *dev = ap->host_set->dev;
   1.634 +	struct ahci_host_priv *hpriv = ap->host_set->private_data;
   1.635 +	struct ahci_port_priv *pp;
   1.636 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.637 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.638 +	void *mem;
   1.639 +	dma_addr_t mem_dma;
   1.640 +	int rc;
   1.641 +
   1.642 +	pp = kmalloc(sizeof(*pp), GFP_KERNEL);
   1.643 +	if (!pp)
   1.644 +		return -ENOMEM;
   1.645 +	memset(pp, 0, sizeof(*pp));
   1.646 +
   1.647 +	rc = ata_pad_alloc(ap, dev);
   1.648 +	if (rc) {
   1.649 +		kfree(pp);
   1.650 +		return rc;
   1.651 +	}
   1.652 +
   1.653 +	mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
   1.654 +	if (!mem) {
   1.655 +		ata_pad_free(ap, dev);
   1.656 +		kfree(pp);
   1.657 +		return -ENOMEM;
   1.658 +	}
   1.659 +	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
   1.660 +
   1.661 +	/*
   1.662 +	 * First item in chunk of DMA memory: 32-slot command table,
   1.663 +	 * 32 bytes each in size
   1.664 +	 */
   1.665 +	pp->cmd_slot = mem;
   1.666 +	pp->cmd_slot_dma = mem_dma;
   1.667 +
   1.668 +	mem += AHCI_CMD_SLOT_SZ;
   1.669 +	mem_dma += AHCI_CMD_SLOT_SZ;
   1.670 +
   1.671 +	/*
   1.672 +	 * Second item: Received-FIS area
   1.673 +	 */
   1.674 +	pp->rx_fis = mem;
   1.675 +	pp->rx_fis_dma = mem_dma;
   1.676 +
   1.677 +	mem += AHCI_RX_FIS_SZ;
   1.678 +	mem_dma += AHCI_RX_FIS_SZ;
   1.679 +
   1.680 +	/*
   1.681 +	 * Third item: data area for storing a single command
   1.682 +	 * and its scatter-gather table
   1.683 +	 */
   1.684 +	pp->cmd_tbl = mem;
   1.685 +	pp->cmd_tbl_dma = mem_dma;
   1.686 +
   1.687 +	ap->private_data = pp;
   1.688 +
   1.689 +	/* initialize port */
   1.690 +	ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
   1.691 +
   1.692 +	return 0;
   1.693 +}
   1.694 +
   1.695 +static void ahci_port_stop(struct ata_port *ap)
   1.696 +{
   1.697 +	struct device *dev = ap->host_set->dev;
   1.698 +	struct ahci_host_priv *hpriv = ap->host_set->private_data;
   1.699 +	struct ahci_port_priv *pp = ap->private_data;
   1.700 +	void __iomem *mmio = ap->host_set->mmio_base;
   1.701 +	void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
   1.702 +	const char *emsg = NULL;
   1.703 +	int rc;
   1.704 +
   1.705 +	/* de-initialize port */
   1.706 +	rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
   1.707 +	if (rc)
   1.708 +		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
   1.709 +
   1.710 +	ap->private_data = NULL;
   1.711 +	dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
   1.712 +			  pp->cmd_slot, pp->cmd_slot_dma);
   1.713 +	ata_pad_free(ap, dev);
   1.714 +	kfree(pp);
   1.715 +}
   1.716 +
   1.717  static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
   1.718  			    unsigned int port_idx)
   1.719  {
   1.720 @@ -1142,47 +1440,12 @@ static int ahci_host_init(struct ata_pro
   1.721  	struct ahci_host_priv *hpriv = probe_ent->private_data;
   1.722  	struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
   1.723  	void __iomem *mmio = probe_ent->mmio_base;
   1.724 -	u32 tmp, cap_save;
   1.725 -	unsigned int i, j, using_dac;
   1.726 +	unsigned int i, using_dac;
   1.727  	int rc;
   1.728 -	void __iomem *port_mmio;
   1.729 -
   1.730 -	cap_save = readl(mmio + HOST_CAP);
   1.731 -	cap_save &= ( (1<<28) | (1<<17) );
   1.732 -	cap_save |= (1 << 27);
   1.733 -
   1.734 -	/* global controller reset */
   1.735 -	tmp = readl(mmio + HOST_CTL);
   1.736 -	if ((tmp & HOST_RESET) == 0) {
   1.737 -		writel(tmp | HOST_RESET, mmio + HOST_CTL);
   1.738 -		readl(mmio + HOST_CTL); /* flush */
   1.739 -	}
   1.740  
   1.741 -	/* reset must complete within 1 second, or
   1.742 -	 * the hardware should be considered fried.
   1.743 -	 */
   1.744 -	ssleep(1);
   1.745 -
   1.746 -	tmp = readl(mmio + HOST_CTL);
   1.747 -	if (tmp & HOST_RESET) {
   1.748 -		dev_printk(KERN_ERR, &pdev->dev,
   1.749 -			   "controller reset failed (0x%x)\n", tmp);
   1.750 -		return -EIO;
   1.751 -	}
   1.752 -
   1.753 -	writel(HOST_AHCI_EN, mmio + HOST_CTL);
   1.754 -	(void) readl(mmio + HOST_CTL);	/* flush */
   1.755 -	writel(cap_save, mmio + HOST_CAP);
   1.756 -	writel(0xf, mmio + HOST_PORTS_IMPL);
   1.757 -	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
   1.758 -
   1.759 -	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
   1.760 -		u16 tmp16;
   1.761 -
   1.762 -		pci_read_config_word(pdev, 0x92, &tmp16);
   1.763 -		tmp16 |= 0xf;
   1.764 -		pci_write_config_word(pdev, 0x92, tmp16);
   1.765 -	}
   1.766 +	rc = ahci_reset_controller(mmio, pdev);
   1.767 +	if (rc)
   1.768 +		return rc;
   1.769  
   1.770  	hpriv->cap = readl(mmio + HOST_CAP);
   1.771  	hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
   1.772 @@ -1218,63 +1481,10 @@ static int ahci_host_init(struct ata_pro
   1.773  		}
   1.774  	}
   1.775  
   1.776 -	for (i = 0; i < probe_ent->n_ports; i++) {
   1.777 -#if 0 /* BIOSen initialize this incorrectly */
   1.778 -		if (!(hpriv->port_map & (1 << i)))
   1.779 -			continue;
   1.780 -#endif
   1.781 -
   1.782 -		port_mmio = ahci_port_base(mmio, i);
   1.783 -		VPRINTK("mmio %p  port_mmio %p\n", mmio, port_mmio);
   1.784 -
   1.785 -		ahci_setup_port(&probe_ent->port[i],
   1.786 -				(unsigned long) mmio, i);
   1.787 -
   1.788 -		/* make sure port is not active */
   1.789 -		tmp = readl(port_mmio + PORT_CMD);
   1.790 -		VPRINTK("PORT_CMD 0x%x\n", tmp);
   1.791 -		if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
   1.792 -			   PORT_CMD_FIS_RX | PORT_CMD_START)) {
   1.793 -			tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
   1.794 -				 PORT_CMD_FIS_RX | PORT_CMD_START);
   1.795 -			writel(tmp, port_mmio + PORT_CMD);
   1.796 -			readl(port_mmio + PORT_CMD); /* flush */
   1.797 -
   1.798 -			/* spec says 500 msecs for each bit, so
   1.799 -			 * this is slightly incorrect.
   1.800 -			 */
   1.801 -			msleep(500);
   1.802 -		}
   1.803 +	for (i = 0; i < probe_ent->n_ports; i++)
   1.804 +		ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
   1.805  
   1.806 -		writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
   1.807 -
   1.808 -		j = 0;
   1.809 -		while (j < 100) {
   1.810 -			msleep(10);
   1.811 -			tmp = readl(port_mmio + PORT_SCR_STAT);
   1.812 -			if ((tmp & 0xf) == 0x3)
   1.813 -				break;
   1.814 -			j++;
   1.815 -		}
   1.816 -
   1.817 -		tmp = readl(port_mmio + PORT_SCR_ERR);
   1.818 -		VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
   1.819 -		writel(tmp, port_mmio + PORT_SCR_ERR);
   1.820 -
   1.821 -		/* ack any pending irq events for this port */
   1.822 -		tmp = readl(port_mmio + PORT_IRQ_STAT);
   1.823 -		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
   1.824 -		if (tmp)
   1.825 -			writel(tmp, port_mmio + PORT_IRQ_STAT);
   1.826 -
   1.827 -		writel(1 << i, mmio + HOST_IRQ_STAT);
   1.828 -	}
   1.829 -
   1.830 -	tmp = readl(mmio + HOST_CTL);
   1.831 -	VPRINTK("HOST_CTL 0x%x\n", tmp);
   1.832 -	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
   1.833 -	tmp = readl(mmio + HOST_CTL);
   1.834 -	VPRINTK("HOST_CTL 0x%x\n", tmp);
   1.835 +	ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
   1.836  
   1.837  	pci_set_master(pdev);
   1.838