ia64/linux-2.6.18-xen.hg

changeset 697:9010d63470ff

merge with linux-2.6.18-xen.hg
author Isaku Yamahata <yamahata@valinux.co.jp>
date Fri Oct 10 12:07:01 2008 +0900 (2008-10-10)
parents 55ec2b18fe7f 2b5cc22ab406
children 9c0f24bdbe3a
files
line diff
     1.1 --- a/arch/i386/kernel/cpu/amd.c	Thu Oct 09 15:23:54 2008 +0900
     1.2 +++ b/arch/i386/kernel/cpu/amd.c	Fri Oct 10 12:07:01 2008 +0900
     1.3 @@ -22,7 +22,7 @@
     1.4  extern void vide(void);
     1.5  __asm__(".align 4\nvide: ret");
     1.6  
     1.7 -static void __init init_amd(struct cpuinfo_x86 *c)
     1.8 +static void __cpuinit init_amd(struct cpuinfo_x86 *c)
     1.9  {
    1.10  	u32 l, h;
    1.11  	int mbytes = num_physpages >> (20-PAGE_SHIFT);
    1.12 @@ -246,7 +246,7 @@ static void __init init_amd(struct cpuin
    1.13  		num_cache_leaves = 3;
    1.14  }
    1.15  
    1.16 -static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
    1.17 +static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
    1.18  {
    1.19  	/* AMD errata T13 (order #21922) */
    1.20  	if ((c->x86 == 6)) {
    1.21 @@ -259,7 +259,7 @@ static unsigned int amd_size_cache(struc
    1.22  	return size;
    1.23  }
    1.24  
    1.25 -static struct cpu_dev amd_cpu_dev __initdata = {
    1.26 +static struct cpu_dev amd_cpu_dev __cpuinitdata = {
    1.27  	.c_vendor	= "AMD",
    1.28  	.c_ident 	= { "AuthenticAMD" },
    1.29  	.c_models = {
    1.30 @@ -284,13 +284,3 @@ int __init amd_init_cpu(void)
    1.31  	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
    1.32  	return 0;
    1.33  }
    1.34 -
    1.35 -//early_arch_initcall(amd_init_cpu);
    1.36 -
    1.37 -static int __init amd_exit_cpu(void)
    1.38 -{
    1.39 -	cpu_devs[X86_VENDOR_AMD] = NULL;
    1.40 -	return 0;
    1.41 -}
    1.42 -
    1.43 -late_initcall(amd_exit_cpu);
     2.1 --- a/arch/i386/kernel/cpu/centaur.c	Thu Oct 09 15:23:54 2008 +0900
     2.2 +++ b/arch/i386/kernel/cpu/centaur.c	Fri Oct 10 12:07:01 2008 +0900
     2.3 @@ -9,7 +9,7 @@
     2.4  
     2.5  #ifdef CONFIG_X86_OOSTORE
     2.6  
     2.7 -static u32 __init power2(u32 x)
     2.8 +static u32 __cpuinit power2(u32 x)
     2.9  {
    2.10  	u32 s=1;
    2.11  	while(s<=x)
    2.12 @@ -22,7 +22,7 @@ static u32 __init power2(u32 x)
    2.13   *	Set up an actual MCR
    2.14   */
    2.15   
    2.16 -static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key)
    2.17 +static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
    2.18  {
    2.19  	u32 lo, hi;
    2.20  	
    2.21 @@ -40,7 +40,7 @@ static void __init centaur_mcr_insert(in
    2.22   *	Shortcut: We know you can't put 4Gig of RAM on a winchip
    2.23   */
    2.24  
    2.25 -static u32 __init ramtop(void)		/* 16388 */
    2.26 +static u32 __cpuinit ramtop(void)		/* 16388 */
    2.27  {
    2.28  	int i;
    2.29  	u32 top = 0;
    2.30 @@ -91,7 +91,7 @@ static u32 __init ramtop(void)		/* 16388
    2.31   *	Compute a set of MCR's to give maximum coverage
    2.32   */
    2.33  
    2.34 -static int __init centaur_mcr_compute(int nr, int key)
    2.35 +static int __cpuinit centaur_mcr_compute(int nr, int key)
    2.36  {
    2.37  	u32 mem = ramtop();
    2.38  	u32 root = power2(mem);
    2.39 @@ -166,7 +166,7 @@ static int __init centaur_mcr_compute(in
    2.40  	return ct;
    2.41  }
    2.42  
    2.43 -static void __init centaur_create_optimal_mcr(void)
    2.44 +static void __cpuinit centaur_create_optimal_mcr(void)
    2.45  {
    2.46  	int i;
    2.47  	/*
    2.48 @@ -189,7 +189,7 @@ static void __init centaur_create_optima
    2.49  		wrmsr(MSR_IDT_MCR0+i, 0, 0);
    2.50  }
    2.51  
    2.52 -static void __init winchip2_create_optimal_mcr(void)
    2.53 +static void __cpuinit winchip2_create_optimal_mcr(void)
    2.54  {
    2.55  	u32 lo, hi;
    2.56  	int i;
    2.57 @@ -227,7 +227,7 @@ static void __init winchip2_create_optim
    2.58   *	Handle the MCR key on the Winchip 2.
    2.59   */
    2.60  
    2.61 -static void __init winchip2_unprotect_mcr(void)
    2.62 +static void __cpuinit winchip2_unprotect_mcr(void)
    2.63  {
    2.64  	u32 lo, hi;
    2.65  	u32 key;
    2.66 @@ -239,7 +239,7 @@ static void __init winchip2_unprotect_mc
    2.67  	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
    2.68  }
    2.69  
    2.70 -static void __init winchip2_protect_mcr(void)
    2.71 +static void __cpuinit winchip2_protect_mcr(void)
    2.72  {
    2.73  	u32 lo, hi;
    2.74  	
    2.75 @@ -257,7 +257,7 @@ static void __init winchip2_protect_mcr(
    2.76  #define RNG_ENABLED	(1 << 3)
    2.77  #define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */
    2.78  
    2.79 -static void __init init_c3(struct cpuinfo_x86 *c)
    2.80 +static void __cpuinit init_c3(struct cpuinfo_x86 *c)
    2.81  {
    2.82  	u32  lo, hi;
    2.83  
    2.84 @@ -303,7 +303,7 @@ static void __init init_c3(struct cpuinf
    2.85  	display_cacheinfo(c);
    2.86  }
    2.87  
    2.88 -static void __init init_centaur(struct cpuinfo_x86 *c)
    2.89 +static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
    2.90  {
    2.91  	enum {
    2.92  		ECX8=1<<1,
    2.93 @@ -442,7 +442,7 @@ static void __init init_centaur(struct c
    2.94  	}
    2.95  }
    2.96  
    2.97 -static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size)
    2.98 +static unsigned int __cpuinit centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size)
    2.99  {
   2.100  	/* VIA C3 CPUs (670-68F) need further shifting. */
   2.101  	if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
   2.102 @@ -457,7 +457,7 @@ static unsigned int centaur_size_cache(s
   2.103  	return size;
   2.104  }
   2.105  
   2.106 -static struct cpu_dev centaur_cpu_dev __initdata = {
   2.107 +static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
   2.108  	.c_vendor	= "Centaur",
   2.109  	.c_ident	= { "CentaurHauls" },
   2.110  	.c_init		= init_centaur,
   2.111 @@ -469,13 +469,3 @@ int __init centaur_init_cpu(void)
   2.112  	cpu_devs[X86_VENDOR_CENTAUR] = &centaur_cpu_dev;
   2.113  	return 0;
   2.114  }
   2.115 -
   2.116 -//early_arch_initcall(centaur_init_cpu);
   2.117 -
   2.118 -static int __init centaur_exit_cpu(void)
   2.119 -{
   2.120 -	cpu_devs[X86_VENDOR_CENTAUR] = NULL;
   2.121 -	return 0;
   2.122 -}
   2.123 -
   2.124 -late_initcall(centaur_exit_cpu);
     3.1 --- a/arch/i386/kernel/cpu/common.c	Thu Oct 09 15:23:54 2008 +0900
     3.2 +++ b/arch/i386/kernel/cpu/common.c	Fri Oct 10 12:07:01 2008 +0900
     3.3 @@ -36,7 +36,7 @@ struct cpu_dev * cpu_devs[X86_VENDOR_NUM
     3.4  
     3.5  extern int disable_pse;
     3.6  
     3.7 -static void default_init(struct cpuinfo_x86 * c)
     3.8 +static void __cpuinit default_init(struct cpuinfo_x86 * c)
     3.9  {
    3.10  	/* Not much we can do here... */
    3.11  	/* Check if at least it has cpuid */
    3.12 @@ -49,7 +49,7 @@ static void default_init(struct cpuinfo_
    3.13  	}
    3.14  }
    3.15  
    3.16 -static struct cpu_dev default_cpu = {
    3.17 +static struct cpu_dev __cpuinitdata default_cpu = {
    3.18  	.c_init	= default_init,
    3.19  	.c_vendor = "Unknown",
    3.20  };
     4.1 --- a/arch/i386/kernel/cpu/cyrix.c	Thu Oct 09 15:23:54 2008 +0900
     4.2 +++ b/arch/i386/kernel/cpu/cyrix.c	Fri Oct 10 12:07:01 2008 +0900
     4.3 @@ -52,25 +52,25 @@ static void __init do_cyrix_devid(unsign
     4.4   * Actually since bugs.h doesn't even reference this perhaps someone should
     4.5   * fix the documentation ???
     4.6   */
     4.7 -static unsigned char Cx86_dir0_msb __initdata = 0;
     4.8 +static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
     4.9  
    4.10 -static char Cx86_model[][9] __initdata = {
    4.11 +static char Cx86_model[][9] __cpuinitdata = {
    4.12  	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
    4.13  	"M II ", "Unknown"
    4.14  };
    4.15 -static char Cx486_name[][5] __initdata = {
    4.16 +static char Cx486_name[][5] __cpuinitdata = {
    4.17  	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
    4.18  	"SRx2", "DRx2"
    4.19  };
    4.20 -static char Cx486S_name[][4] __initdata = {
    4.21 +static char Cx486S_name[][4] __cpuinitdata = {
    4.22  	"S", "S2", "Se", "S2e"
    4.23  };
    4.24 -static char Cx486D_name[][4] __initdata = {
    4.25 +static char Cx486D_name[][4] __cpuinitdata = {
    4.26  	"DX", "DX2", "?", "?", "?", "DX4"
    4.27  };
    4.28 -static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";
    4.29 -static char cyrix_model_mult1[] __initdata = "12??43";
    4.30 -static char cyrix_model_mult2[] __initdata = "12233445";
    4.31 +static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
    4.32 +static char cyrix_model_mult1[] __cpuinitdata = "12??43";
    4.33 +static char cyrix_model_mult2[] __cpuinitdata = "12233445";
    4.34  
    4.35  /*
    4.36   * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
    4.37 @@ -82,7 +82,7 @@ static char cyrix_model_mult2[] __initda
    4.38  
    4.39  extern void calibrate_delay(void) __init;
    4.40  
    4.41 -static void __init check_cx686_slop(struct cpuinfo_x86 *c)
    4.42 +static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
    4.43  {
    4.44  	unsigned long flags;
    4.45  	
    4.46 @@ -107,7 +107,7 @@ static void __init check_cx686_slop(stru
    4.47  }
    4.48  
    4.49  
    4.50 -static void __init set_cx86_reorder(void)
    4.51 +static void __cpuinit set_cx86_reorder(void)
    4.52  {
    4.53  	u8 ccr3;
    4.54  
    4.55 @@ -122,7 +122,7 @@ static void __init set_cx86_reorder(void
    4.56  	setCx86(CX86_CCR3, ccr3);
    4.57  }
    4.58  
    4.59 -static void __init set_cx86_memwb(void)
    4.60 +static void __cpuinit set_cx86_memwb(void)
    4.61  {
    4.62  	u32 cr0;
    4.63  
    4.64 @@ -137,7 +137,7 @@ static void __init set_cx86_memwb(void)
    4.65  	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
    4.66  }
    4.67  
    4.68 -static void __init set_cx86_inc(void)
    4.69 +static void __cpuinit set_cx86_inc(void)
    4.70  {
    4.71  	unsigned char ccr3;
    4.72  
    4.73 @@ -158,7 +158,7 @@ static void __init set_cx86_inc(void)
    4.74   *	Configure later MediaGX and/or Geode processor.
    4.75   */
    4.76  
    4.77 -static void __init geode_configure(void)
    4.78 +static void __cpuinit geode_configure(void)
    4.79  {
    4.80  	unsigned long flags;
    4.81  	u8 ccr3, ccr4;
    4.82 @@ -184,14 +184,14 @@ static void __init geode_configure(void)
    4.83  
    4.84  
    4.85  #ifdef CONFIG_PCI
    4.86 -static struct pci_device_id __initdata cyrix_55x0[] = {
    4.87 +static struct pci_device_id __cpuinitdata cyrix_55x0[] = {
    4.88  	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },
    4.89  	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },
    4.90  	{ },
    4.91  };
    4.92  #endif
    4.93  
    4.94 -static void __init init_cyrix(struct cpuinfo_x86 *c)
    4.95 +static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
    4.96  {
    4.97  	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
    4.98  	char *buf = c->x86_model_id;
    4.99 @@ -346,7 +346,7 @@ static void __init init_cyrix(struct cpu
   4.100  /*
   4.101   * Handle National Semiconductor branded processors
   4.102   */
   4.103 -static void __init init_nsc(struct cpuinfo_x86 *c)
   4.104 +static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
   4.105  {
   4.106  	/* There may be GX1 processors in the wild that are branded
   4.107  	 * NSC and not Cyrix.
   4.108 @@ -430,7 +430,7 @@ static void cyrix_identify(struct cpuinf
   4.109  	generic_identify(c);
   4.110  }
   4.111  
   4.112 -static struct cpu_dev cyrix_cpu_dev __initdata = {
   4.113 +static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
   4.114  	.c_vendor	= "Cyrix",
   4.115  	.c_ident 	= { "CyrixInstead" },
   4.116  	.c_init		= init_cyrix,
   4.117 @@ -443,17 +443,7 @@ int __init cyrix_init_cpu(void)
   4.118  	return 0;
   4.119  }
   4.120  
   4.121 -//early_arch_initcall(cyrix_init_cpu);
   4.122 -
   4.123 -static int __init cyrix_exit_cpu(void)
   4.124 -{
   4.125 -	cpu_devs[X86_VENDOR_CYRIX] = NULL;
   4.126 -	return 0;
   4.127 -}
   4.128 -
   4.129 -late_initcall(cyrix_exit_cpu);
   4.130 -
   4.131 -static struct cpu_dev nsc_cpu_dev __initdata = {
   4.132 +static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
   4.133  	.c_vendor	= "NSC",
   4.134  	.c_ident 	= { "Geode by NSC" },
   4.135  	.c_init		= init_nsc,
   4.136 @@ -466,12 +456,3 @@ int __init nsc_init_cpu(void)
   4.137  	return 0;
   4.138  }
   4.139  
   4.140 -//early_arch_initcall(nsc_init_cpu);
   4.141 -
   4.142 -static int __init nsc_exit_cpu(void)
   4.143 -{
   4.144 -	cpu_devs[X86_VENDOR_NSC] = NULL;
   4.145 -	return 0;
   4.146 -}
   4.147 -
   4.148 -late_initcall(nsc_exit_cpu);
     5.1 --- a/arch/i386/kernel/cpu/intel.c	Thu Oct 09 15:23:54 2008 +0900
     5.2 +++ b/arch/i386/kernel/cpu/intel.c	Fri Oct 10 12:07:01 2008 +0900
     5.3 @@ -198,7 +198,7 @@ static void __cpuinit init_intel(struct 
     5.4  }
     5.5  
     5.6  
     5.7 -static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
     5.8 +static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
     5.9  {
    5.10  	/* Intel PIII Tualatin. This comes in two flavours.
    5.11  	 * One has 256kb of cache, the other 512. We have no way
     6.1 --- a/arch/i386/kernel/cpu/nexgen.c	Thu Oct 09 15:23:54 2008 +0900
     6.2 +++ b/arch/i386/kernel/cpu/nexgen.c	Fri Oct 10 12:07:01 2008 +0900
     6.3 @@ -27,7 +27,7 @@ static int __init deep_magic_nexgen_prob
     6.4  	return  ret;
     6.5  }
     6.6  
     6.7 -static void __init init_nexgen(struct cpuinfo_x86 * c)
     6.8 +static void __cpuinit init_nexgen(struct cpuinfo_x86 * c)
     6.9  {
    6.10  	c->x86_cache_size = 256; /* A few had 1 MB... */
    6.11  }
    6.12 @@ -41,7 +41,7 @@ static void __init nexgen_identify(struc
    6.13  	generic_identify(c);
    6.14  }
    6.15  
    6.16 -static struct cpu_dev nexgen_cpu_dev __initdata = {
    6.17 +static struct cpu_dev nexgen_cpu_dev __cpuinitdata = {
    6.18  	.c_vendor	= "Nexgen",
    6.19  	.c_ident	= { "NexGenDriven" },
    6.20  	.c_models = {
    6.21 @@ -59,13 +59,3 @@ int __init nexgen_init_cpu(void)
    6.22  	cpu_devs[X86_VENDOR_NEXGEN] = &nexgen_cpu_dev;
    6.23  	return 0;
    6.24  }
    6.25 -
    6.26 -//early_arch_initcall(nexgen_init_cpu);
    6.27 -
    6.28 -static int __init nexgen_exit_cpu(void)
    6.29 -{
    6.30 -	cpu_devs[X86_VENDOR_NEXGEN] = NULL;
    6.31 -	return 0;
    6.32 -}
    6.33 -
    6.34 -late_initcall(nexgen_exit_cpu);
     7.1 --- a/arch/i386/kernel/cpu/rise.c	Thu Oct 09 15:23:54 2008 +0900
     7.2 +++ b/arch/i386/kernel/cpu/rise.c	Fri Oct 10 12:07:01 2008 +0900
     7.3 @@ -5,7 +5,7 @@
     7.4  
     7.5  #include "cpu.h"
     7.6  
     7.7 -static void __init init_rise(struct cpuinfo_x86 *c)
     7.8 +static void __cpuinit init_rise(struct cpuinfo_x86 *c)
     7.9  {
    7.10  	printk("CPU: Rise iDragon");
    7.11  	if (c->x86_model > 2)
    7.12 @@ -28,7 +28,7 @@ static void __init init_rise(struct cpui
    7.13  	set_bit(X86_FEATURE_CX8, c->x86_capability);
    7.14  }
    7.15  
    7.16 -static struct cpu_dev rise_cpu_dev __initdata = {
    7.17 +static struct cpu_dev rise_cpu_dev __cpuinitdata = {
    7.18  	.c_vendor	= "Rise",
    7.19  	.c_ident	= { "RiseRiseRise" },
    7.20  	.c_models = {
    7.21 @@ -50,12 +50,3 @@ int __init rise_init_cpu(void)
    7.22  	return 0;
    7.23  }
    7.24  
    7.25 -//early_arch_initcall(rise_init_cpu);
    7.26 -
    7.27 -static int __init rise_exit_cpu(void)
    7.28 -{
    7.29 -	cpu_devs[X86_VENDOR_RISE] = NULL;
    7.30 -	return 0;
    7.31 -}
    7.32 -
    7.33 -late_initcall(rise_exit_cpu);
     8.1 --- a/arch/i386/kernel/cpu/transmeta.c	Thu Oct 09 15:23:54 2008 +0900
     8.2 +++ b/arch/i386/kernel/cpu/transmeta.c	Fri Oct 10 12:07:01 2008 +0900
     8.3 @@ -5,7 +5,7 @@
     8.4  #include <asm/msr.h>
     8.5  #include "cpu.h"
     8.6  
     8.7 -static void __init init_transmeta(struct cpuinfo_x86 *c)
     8.8 +static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
     8.9  {
    8.10  	unsigned int cap_mask, uk, max, dummy;
    8.11  	unsigned int cms_rev1, cms_rev2;
    8.12 @@ -98,7 +98,7 @@ static void __init transmeta_identify(st
    8.13  	}
    8.14  }
    8.15  
    8.16 -static struct cpu_dev transmeta_cpu_dev __initdata = {
    8.17 +static struct cpu_dev transmeta_cpu_dev __cpuinitdata = {
    8.18  	.c_vendor	= "Transmeta",
    8.19  	.c_ident	= { "GenuineTMx86", "TransmetaCPU" },
    8.20  	.c_init		= init_transmeta,
    8.21 @@ -110,13 +110,3 @@ int __init transmeta_init_cpu(void)
    8.22  	cpu_devs[X86_VENDOR_TRANSMETA] = &transmeta_cpu_dev;
    8.23  	return 0;
    8.24  }
    8.25 -
    8.26 -//early_arch_initcall(transmeta_init_cpu);
    8.27 -
    8.28 -static int __init transmeta_exit_cpu(void)
    8.29 -{
    8.30 -	cpu_devs[X86_VENDOR_TRANSMETA] = NULL;
    8.31 -	return 0;
    8.32 -}
    8.33 -
    8.34 -late_initcall(transmeta_exit_cpu);
     9.1 --- a/arch/i386/kernel/cpu/umc.c	Thu Oct 09 15:23:54 2008 +0900
     9.2 +++ b/arch/i386/kernel/cpu/umc.c	Fri Oct 10 12:07:01 2008 +0900
     9.3 @@ -5,12 +5,8 @@
     9.4  
     9.5  /* UMC chips appear to be only either 386 or 486, so no special init takes place.
     9.6   */
     9.7 -static void __init init_umc(struct cpuinfo_x86 * c)
     9.8 -{
     9.9  
    9.10 -}
    9.11 -
    9.12 -static struct cpu_dev umc_cpu_dev __initdata = {
    9.13 +static struct cpu_dev umc_cpu_dev __cpuinitdata = {
    9.14  	.c_vendor	= "UMC",
    9.15  	.c_ident 	= { "UMC UMC UMC" },
    9.16  	.c_models = {
    9.17 @@ -21,7 +17,6 @@ static struct cpu_dev umc_cpu_dev __init
    9.18  		  }
    9.19  		},
    9.20  	},
    9.21 -	.c_init		= init_umc,
    9.22  };
    9.23  
    9.24  int __init umc_init_cpu(void)
    9.25 @@ -29,13 +24,3 @@ int __init umc_init_cpu(void)
    9.26  	cpu_devs[X86_VENDOR_UMC] = &umc_cpu_dev;
    9.27  	return 0;
    9.28  }
    9.29 -
    9.30 -//early_arch_initcall(umc_init_cpu);
    9.31 -
    9.32 -static int __init umc_exit_cpu(void)
    9.33 -{
    9.34 -	cpu_devs[X86_VENDOR_UMC] = NULL;
    9.35 -	return 0;
    9.36 -}
    9.37 -
    9.38 -late_initcall(umc_exit_cpu);
    10.1 --- a/arch/x86_64/mm/init-xen.c	Thu Oct 09 15:23:54 2008 +0900
    10.2 +++ b/arch/x86_64/mm/init-xen.c	Fri Oct 10 12:07:01 2008 +0900
    10.3 @@ -274,7 +274,7 @@ static __init void set_pte_phys(unsigned
    10.4  		new_pte = __pte(0);
    10.5  
    10.6  	pte = pte_offset_kernel(pmd, vaddr);
    10.7 -	if (!pte_none(*pte) &&
    10.8 +	if (!pte_none(*pte) && pte_val(new_pte) &&
    10.9  	    __pte_val(*pte) != (__pte_val(new_pte) & __supported_pte_mask))
   10.10  		pte_ERROR(*pte);
   10.11  	set_pte(pte, new_pte);
   10.12 @@ -325,7 +325,7 @@ static __init void set_pte_phys_ma(unsig
   10.13  	new_pte = pfn_pte_ma(phys >> PAGE_SHIFT, prot);
   10.14  
   10.15  	pte = pte_offset_kernel(pmd, vaddr);
   10.16 -	if (!pte_none(*pte) &&
   10.17 +	if (!pte_none(*pte) && pte_val(new_pte) &&
   10.18  #ifdef CONFIG_ACPI
   10.19  	    /* __acpi_map_table() fails to properly call clear_fixmap() */
   10.20  	    (vaddr < __fix_to_virt(FIX_ACPI_END) ||
    11.1 --- a/drivers/pci/Makefile	Thu Oct 09 15:23:54 2008 +0900
    11.2 +++ b/drivers/pci/Makefile	Fri Oct 10 12:07:01 2008 +0900
    11.3 @@ -3,7 +3,8 @@
    11.4  #
    11.5  
    11.6  obj-y		+= access.o bus.o probe.o remove.o pci.o quirks.o \
    11.7 -			pci-driver.o search.o pci-sysfs.o rom.o setup-res.o
    11.8 +			pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
    11.9 +			reassigndev.o
   11.10  obj-$(CONFIG_PROC_FS) += proc.o
   11.11  
   11.12  # Build PCI Express stuff if needed
    12.1 --- a/drivers/pci/msi-xen.c	Thu Oct 09 15:23:54 2008 +0900
    12.2 +++ b/drivers/pci/msi-xen.c	Fri Oct 10 12:07:01 2008 +0900
    12.3 @@ -67,7 +67,7 @@ static struct msi_dev_list *get_msi_dev_
    12.4  	}
    12.5  
    12.6  	/* Has not allocate msi_dev until now. */
    12.7 -	ret = kmalloc(sizeof(struct msi_dev_list), GFP_ATOMIC);
    12.8 +	ret = kzalloc(sizeof(struct msi_dev_list), GFP_ATOMIC);
    12.9  
   12.10  	/* Failed to allocate msi_dev structure */
   12.11  	if ( !ret ) {
   12.12 @@ -75,6 +75,7 @@ static struct msi_dev_list *get_msi_dev_
   12.13  		return NULL;
   12.14  	}
   12.15  
   12.16 +	ret->dev = dev;
   12.17  	spin_lock_init(&ret->pirq_list_lock);
   12.18  	INIT_LIST_HEAD(&ret->pirq_list_head);
   12.19  	list_add_tail(&ret->list, &msi_dev_head);
    13.1 --- a/drivers/pci/pci.h	Thu Oct 09 15:23:54 2008 +0900
    13.2 +++ b/drivers/pci/pci.h	Fri Oct 10 12:07:01 2008 +0900
    13.3 @@ -99,3 +99,8 @@ pci_match_one_device(const struct pci_de
    13.4  	return NULL;
    13.5  }
    13.6  
    13.7 +#define ROUND_UP_TO_PAGESIZE(size) ((size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1))
    13.8 +
    13.9 +extern int reassign_resources;
   13.10 +extern int is_reassigndev(struct pci_dev *dev);
   13.11 +extern void pci_update_bridge(struct pci_dev *dev, int resno);
    14.1 --- a/drivers/pci/quirks.c	Thu Oct 09 15:23:54 2008 +0900
    14.2 +++ b/drivers/pci/quirks.c	Fri Oct 10 12:07:01 2008 +0900
    14.3 @@ -33,6 +33,19 @@ static int __init set_pci_mem_align(char
    14.4  }
    14.5  __setup("pci-mem-align", set_pci_mem_align);
    14.6  
    14.7 +
    14.8 +int reassign_resources = 0;
    14.9 +
   14.10 +static int __init set_reassign_resources(char *str)
   14.11 +{
   14.12 +	/* resources reassign on */
   14.13 +	reassign_resources = 1;
   14.14 +	printk(KERN_DEBUG "PCI: resource reassign ON.\n");
   14.15 +
   14.16 +	return 1;
   14.17 +}
   14.18 +__setup("reassign_resources", set_reassign_resources);
   14.19 +
   14.20  /* This quirk function enables us to force all memory resources which are 
   14.21   * assigned to PCI devices, to be page-aligned.
   14.22   */
   14.23 @@ -42,6 +55,42 @@ static void __devinit quirk_align_mem_re
   14.24  	struct resource *r;
   14.25  	resource_size_t old_start;
   14.26  
   14.27 +	if (reassign_resources) {
   14.28 +		if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
   14.29 +		    (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
   14.30 +			/* PCI Host Bridge isn't a target device */
   14.31 +			return;
   14.32 +		}
   14.33 +		if (is_reassigndev(dev)) {
   14.34 +			printk(KERN_INFO 
   14.35 +				"PCI: Disable device and release resources"
   14.36 +				" [%s].\n", pci_name(dev));
   14.37 +			pci_disable_device(dev);
   14.38 +
   14.39 +			for (i=0; i < PCI_NUM_RESOURCES; i++) {
   14.40 +				r = &dev->resource[i];
   14.41 +				if ((r == NULL) || 
   14.42 +				   !(r->flags & IORESOURCE_MEM))
   14.43 +					continue;
   14.44 +
   14.45 +				r->end = r->end - r->start;
   14.46 +				r->start = 0;
   14.47 +
   14.48 +				if (i < PCI_BRIDGE_RESOURCES) {
   14.49 +					pci_update_resource(dev, r, i);
   14.50 +				} else if (i == 8 || i == 9) {
   14.51 +					/* need to update(clear) the Base/Limit
   14.52 +					 * register also, because PCI bridge is
   14.53 +					 * disabled and the resource is 
   14.54 +					 * released.
   14.55 +					 */
   14.56 +					pci_update_bridge(dev, i);
   14.57 +				}
   14.58 +			}
   14.59 +		}
   14.60 +		return;
   14.61 +	}
   14.62 +
   14.63  	if (!pci_mem_align)
   14.64  		return;
   14.65  
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/drivers/pci/reassigndev.c	Fri Oct 10 12:07:01 2008 +0900
    15.3 @@ -0,0 +1,80 @@
    15.4 +/*
    15.5 + * Copyright (c) 2008, NEC Corporation.
    15.6 + *
    15.7 + * This program is free software; you can redistribute it and/or modify it
    15.8 + * under the terms and conditions of the GNU General Public License,
    15.9 + * version 2, as published by the Free Software Foundation.
   15.10 + *
   15.11 + * This program is distributed in the hope it will be useful, but WITHOUT
   15.12 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   15.13 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   15.14 + * more details.
   15.15 + *
   15.16 + * You should have received a copy of the GNU General Public License along with
   15.17 + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
   15.18 + * Place - Suite 330, Boston, MA 02111-1307 USA.
   15.19 + */
   15.20 +
   15.21 +#include <linux/kernel.h>
   15.22 +#include <linux/pci.h>
   15.23 +#include <linux/string.h>
   15.24 +#include "pci.h"
   15.25 +
   15.26 +
   15.27 +#define	REASSIGNDEV_PARAM_MAX	(2048)
   15.28 +#define	TOKEN_MAX	(12)	/* "SSSS:BB:DD.F" length is 12 */
   15.29 +
   15.30 +static char param_reassigndev[REASSIGNDEV_PARAM_MAX] = {0};
   15.31 +
   15.32 +static int __init reassigndev_setup(char *str)
   15.33 +{
   15.34 +	strncpy(param_reassigndev, str, REASSIGNDEV_PARAM_MAX);
   15.35 +	param_reassigndev[REASSIGNDEV_PARAM_MAX - 1] = '\0';
   15.36 +	return 1;
   15.37 +}
   15.38 +__setup("reassigndev=", reassigndev_setup);
   15.39 +
   15.40 +int is_reassigndev(struct pci_dev *dev)
   15.41 +{
   15.42 +	char dev_str[TOKEN_MAX+1];
   15.43 +	int seg, bus, slot, func;
   15.44 +	int len;
   15.45 +	char *p, *next_str;
   15.46 +
   15.47 +	p = param_reassigndev;
   15.48 +	for (; p; p = next_str + 1) {
   15.49 +		next_str = strpbrk(p, ",");
   15.50 +		if (next_str) {
   15.51 +			len = next_str - p;
   15.52 +		} else {
   15.53 +			len = strlen(p);
   15.54 +		}
   15.55 +		if (len > 0 && len <= TOKEN_MAX) {
   15.56 +			strncpy(dev_str, p, len);
   15.57 +			*(dev_str + len) = '\0';
   15.58 +
   15.59 +			if (sscanf(dev_str, "%x:%x:%x.%x", 
   15.60 +				&seg, &bus, &slot, &func) != 4) {
   15.61 +				if (sscanf(dev_str, "%x:%x.%x", 
   15.62 +					&bus, &slot, &func) == 3) {
   15.63 +					seg = 0;
   15.64 +				} else {
   15.65 +					/* failed to scan strings */
   15.66 +					seg = -1;
   15.67 +					bus = -1;
   15.68 +				}
   15.69 +			}
   15.70 +			if (seg == pci_domain_nr(dev->bus) &&
   15.71 +			    bus == dev->bus->number &&
   15.72 +			    slot == PCI_SLOT(dev->devfn) &&
   15.73 +			    func == PCI_FUNC(dev->devfn)) {
   15.74 +				/* It's a target device */
   15.75 +				return 1;
   15.76 +			}
   15.77 +		}
   15.78 +		if (!next_str)
   15.79 +			break;
   15.80 +	}
   15.81 +
   15.82 +	return 0;
   15.83 +}
    16.1 --- a/drivers/pci/setup-bus.c	Thu Oct 09 15:23:54 2008 +0900
    16.2 +++ b/drivers/pci/setup-bus.c	Fri Oct 10 12:07:01 2008 +0900
    16.3 @@ -26,6 +26,7 @@
    16.4  #include <linux/cache.h>
    16.5  #include <linux/slab.h>
    16.6  
    16.7 +#include "pci.h"
    16.8  
    16.9  #define DEBUG_CONFIG 1
   16.10  #if DEBUG_CONFIG
   16.11 @@ -344,7 +345,8 @@ pbus_size_mem(struct pci_bus *bus, unsig
   16.12  
   16.13  	list_for_each_entry(dev, &bus->devices, bus_list) {
   16.14  		int i;
   16.15 -		
   16.16 +		int reassign = reassign_resources ? is_reassigndev(dev) : 0;
   16.17 +
   16.18  		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
   16.19  			struct resource *r = &dev->resource[i];
   16.20  			unsigned long r_size;
   16.21 @@ -352,6 +354,11 @@ pbus_size_mem(struct pci_bus *bus, unsig
   16.22  			if (r->parent || (r->flags & mask) != type)
   16.23  				continue;
   16.24  			r_size = r->end - r->start + 1;
   16.25 +
   16.26 +			if (reassign) {
   16.27 +				r_size = ROUND_UP_TO_PAGESIZE(r_size);
   16.28 +			}
   16.29 +
   16.30  			/* For bridges size != alignment */
   16.31  			align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
   16.32  			order = __ffs(align) - 20;
    17.1 --- a/drivers/pci/setup-res.c	Thu Oct 09 15:23:54 2008 +0900
    17.2 +++ b/drivers/pci/setup-res.c	Fri Oct 10 12:07:01 2008 +0900
    17.3 @@ -117,19 +117,96 @@ pci_claim_resource(struct pci_dev *dev, 
    17.4  }
    17.5  EXPORT_SYMBOL_GPL(pci_claim_resource);
    17.6  
    17.7 +void 
    17.8 +pci_update_bridge(struct pci_dev *dev, int resno)
    17.9 +{
   17.10 +	struct resource *res = &dev->resource[resno]; 
   17.11 +	struct pci_bus_region region;
   17.12 +	u32 l, dw, base_up32, limit_up32;
   17.13 +
   17.14 +	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE ||
   17.15 +	    (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) {
   17.16 +		return;
   17.17 +	}
   17.18 +
   17.19 +	if (!res->flags)
   17.20 +		return;
   17.21 +
   17.22 +	switch (resno) {
   17.23 +	case 8 :	/* MMIO Base/Limit */
   17.24 +		pcibios_resource_to_bus(dev, &region, res);
   17.25 +		if (res->flags & IORESOURCE_MEM &&
   17.26 +		    !(res->flags & IORESOURCE_PREFETCH)) {
   17.27 +			l = (region.start >> 16) & 0xfff0;
   17.28 +			l |= region.end & 0xfff00000;
   17.29 +		} else {
   17.30 +			l = 0x0000fff0;
   17.31 +		}
   17.32 +		pci_write_config_dword(dev, PCI_MEMORY_BASE, l);
   17.33 +
   17.34 +		break;
   17.35 +
   17.36 +	case 9 :	/* Prefetchable MMIO Base/Limit */
   17.37 +		/* Clear out the upper 32 bits of PREF limit.
   17.38 +		 * If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
   17.39 +		 * disables PREF range, which is ok.
   17.40 +		 */
   17.41 +		pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
   17.42 +
   17.43 +		/* Get PREF 32/64 bits Addressing mode */
   17.44 +		pci_read_config_dword(dev, PCI_PREF_MEMORY_BASE, &dw);
   17.45 +
   17.46 +		pcibios_resource_to_bus(dev, &region, res);
   17.47 +		if (res->flags & IORESOURCE_MEM &&
   17.48 +		    res->flags & IORESOURCE_PREFETCH) {
   17.49 +			l = (region.start >> 16) & 0xfff0;
   17.50 +			l |= region.end & 0xfff00000;
   17.51 +
   17.52 +			if (dw & PCI_PREF_RANGE_TYPE_64) {
   17.53 +				base_up32 = (region.start >> 32) & 0xffffffff;
   17.54 +				limit_up32 = (region.end >> 32) & 0xffffffff;
   17.55 +			} else {
   17.56 +				base_up32 = 0;
   17.57 +				limit_up32 = 0;
   17.58 +			}
   17.59 +		} else {
   17.60 +			l = 0x0000fff0;
   17.61 +			base_up32 = 0xffffffff;
   17.62 +			limit_up32 = 0;
   17.63 +		}
   17.64 +		pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, l);
   17.65 +		/* Set up the upper 32 bits of PREF base/limit. */
   17.66 +		pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, base_up32);
   17.67 +		pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, limit_up32);
   17.68 +		break;
   17.69 +	default :
   17.70 +		BUG();
   17.71 +		break;
   17.72 +	}
   17.73 +}
   17.74 +
   17.75  int pci_assign_resource(struct pci_dev *dev, int resno)
   17.76  {
   17.77  	struct pci_bus *bus = dev->bus;
   17.78  	struct resource *res = dev->resource + resno;
   17.79  	resource_size_t size, min, align;
   17.80  	int ret;
   17.81 +	int reassigndev = reassign_resources ? is_reassigndev(dev) : 0;
   17.82  
   17.83  	size = res->end - res->start + 1;
   17.84  	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
   17.85  	/* The bridge resources are special, as their
   17.86  	   size != alignment. Sizing routines return
   17.87  	   required alignment in the "start" field. */
   17.88 -	align = (resno < PCI_BRIDGE_RESOURCES) ? size : res->start;
   17.89 +	if (resno < PCI_BRIDGE_RESOURCES) {
   17.90 +		align = size;
   17.91 +		if ((reassigndev) &&
   17.92 +		    (res->flags & IORESOURCE_MEM)) {
   17.93 +			align = ROUND_UP_TO_PAGESIZE(align);
   17.94 +		}
   17.95 +	} else {
   17.96 +		align = res->start;
   17.97 +	}
   17.98  
   17.99  	/* First, try exact prefetching match.. */
  17.100  	ret = pci_bus_alloc_resource(bus, res, size, align, min,
  17.101 @@ -154,6 +231,9 @@ int pci_assign_resource(struct pci_dev *
  17.102  			resno, (unsigned long long)size,
  17.103  			(unsigned long long)res->start, pci_name(dev));
  17.104  	} else if (resno < PCI_BRIDGE_RESOURCES) {
  17.105 +		printk(KERN_DEBUG "PCI: Assign resource(%d) on %s "
  17.106 +			"%016llx - %016llx\n", resno, pci_name(dev),
  17.107 +			(u64)res->start, (u64)res->end);
  17.108  		pci_update_resource(dev, res, resno);
  17.109  	}
  17.110  
    18.1 --- a/drivers/xen/core/evtchn.c	Thu Oct 09 15:23:54 2008 +0900
    18.2 +++ b/drivers/xen/core/evtchn.c	Fri Oct 10 12:07:01 2008 +0900
    18.3 @@ -756,7 +756,16 @@ static struct hw_interrupt_type dynirq_t
    18.4  
    18.5  void evtchn_register_pirq(int irq)
    18.6  {
    18.7 +	struct irq_desc *desc;
    18.8 +	unsigned long flags;
    18.9 +
   18.10  	irq_info[irq] = mk_irq_info(IRQT_PIRQ, irq, 0);
   18.11 +
   18.12 +	/* Cannot call set_irq_probe(), as that's marked __init. */
   18.13 +	desc = irq_desc + irq;
   18.14 +	spin_lock_irqsave(&desc->lock, flags);
   18.15 +	desc->status &= ~IRQ_NOPROBE;
   18.16 +	spin_unlock_irqrestore(&desc->lock, flags);
   18.17  }
   18.18  
   18.19  #if defined(CONFIG_X86_IO_APIC)
   18.20 @@ -1105,7 +1114,7 @@ void __init xen_init_IRQ(void)
   18.21  	for (i = DYNIRQ_BASE; i < (DYNIRQ_BASE + NR_DYNIRQS); i++) {
   18.22  		irq_bindcount[i] = 0;
   18.23  
   18.24 -		irq_desc[i].status = IRQ_DISABLED;
   18.25 +		irq_desc[i].status = IRQ_DISABLED|IRQ_NOPROBE;
   18.26  		irq_desc[i].action = NULL;
   18.27  		irq_desc[i].depth = 1;
   18.28  		irq_desc[i].chip = &dynirq_type;
   18.29 @@ -1123,6 +1132,8 @@ void __init xen_init_IRQ(void)
   18.30  #endif
   18.31  
   18.32  		irq_desc[i].status = IRQ_DISABLED;
   18.33 +		if (!identity_mapped_irq(i))
   18.34 +			irq_desc[i].status |= IRQ_NOPROBE;
   18.35  		irq_desc[i].action = NULL;
   18.36  		irq_desc[i].depth = 1;
   18.37  		irq_desc[i].chip = &pirq_type;